1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Writer Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9/// getMnemonic - This method is automatically generated by tablegen
10/// from the instruction set description.
11std::pair<const char *, uint64_t> AArch64AppleInstPrinter::getMnemonic(const MCInst *MI) {
12
13#ifdef __GNUC__
14#pragma GCC diagnostic push
15#pragma GCC diagnostic ignored "-Woverlength-strings"
16#endif
17 static const char AsmStrs[] = {
18 /* 0 */ "st64bv0\t\0"
19 /* 9 */ "ld1\t\0"
20 /* 14 */ "trn1\t\0"
21 /* 20 */ "zip1\t\0"
22 /* 26 */ "uzp1\t\0"
23 /* 32 */ "dcps1\t\0"
24 /* 39 */ "st1\t\0"
25 /* 44 */ "rax1\t\0"
26 /* 50 */ "rev32\t\0"
27 /* 57 */ "ld2\t\0"
28 /* 62 */ "fmlal2\t\0"
29 /* 70 */ "fmlsl2\t\0"
30 /* 78 */ "fcvtl2\t\0"
31 /* 86 */ "trn2\t\0"
32 /* 92 */ "fcvtn2\t\0"
33 /* 100 */ "fcvtxn2\t\0"
34 /* 109 */ "zip2\t\0"
35 /* 115 */ "uzp2\t\0"
36 /* 121 */ "dcps2\t\0"
37 /* 128 */ "st2\t\0"
38 /* 133 */ "ld3\t\0"
39 /* 138 */ "eor3\t\0"
40 /* 144 */ "dcps3\t\0"
41 /* 151 */ "st3\t\0"
42 /* 156 */ "ld4\t\0"
43 /* 161 */ "st4\t\0"
44 /* 166 */ "rev16\t\0"
45 /* 173 */ "braa\t\0"
46 /* 179 */ "ldraa\t\0"
47 /* 186 */ "blraa\t\0"
48 /* 193 */ "saba\t\0"
49 /* 199 */ "uaba\t\0"
50 /* 205 */ "pacda\t\0"
51 /* 212 */ "ldadda\t\0"
52 /* 220 */ "fadda\t\0"
53 /* 227 */ "autda\t\0"
54 /* 234 */ "pacga\t\0"
55 /* 241 */ "pacia\t\0"
56 /* 248 */ "autia\t\0"
57 /* 255 */ "brka\t\0"
58 /* 261 */ "fcmla\t\0"
59 /* 268 */ "fmla\t\0"
60 /* 274 */ "bfmmla\t\0"
61 /* 282 */ "usmmla\t\0"
62 /* 290 */ "ummla\t\0"
63 /* 297 */ "fnmla\t\0"
64 /* 304 */ "ldsmina\t\0"
65 /* 313 */ "ldumina\t\0"
66 /* 322 */ "brkpa\t\0"
67 /* 329 */ "caspa\t\0"
68 /* 336 */ "swpa\t\0"
69 /* 342 */ "fexpa\t\0"
70 /* 349 */ "ldclra\t\0"
71 /* 357 */ "ldeora\t\0"
72 /* 365 */ "srsra\t\0"
73 /* 372 */ "ursra\t\0"
74 /* 379 */ "ssra\t\0"
75 /* 385 */ "usra\t\0"
76 /* 391 */ "casa\t\0"
77 /* 397 */ "ldseta\t\0"
78 /* 405 */ "frinta\t\0"
79 /* 413 */ "clasta\t\0"
80 /* 421 */ "ldsmaxa\t\0"
81 /* 430 */ "ldumaxa\t\0"
82 /* 439 */ "pacdza\t\0"
83 /* 447 */ "autdza\t\0"
84 /* 455 */ "paciza\t\0"
85 /* 463 */ "autiza\t\0"
86 /* 471 */ "ins.b\t\0"
87 /* 478 */ "smov.b\t\0"
88 /* 486 */ "umov.b\t\0"
89 /* 494 */ "ld1b\t\0"
90 /* 500 */ "ldff1b\t\0"
91 /* 508 */ "ldnf1b\t\0"
92 /* 516 */ "ldnt1b\t\0"
93 /* 524 */ "stnt1b\t\0"
94 /* 532 */ "st1b\t\0"
95 /* 538 */ "crc32b\t\0"
96 /* 546 */ "ld2b\t\0"
97 /* 552 */ "st2b\t\0"
98 /* 558 */ "ld3b\t\0"
99 /* 564 */ "st3b\t\0"
100 /* 570 */ "ld64b\t\0"
101 /* 577 */ "st64b\t\0"
102 /* 584 */ "ld4b\t\0"
103 /* 590 */ "st4b\t\0"
104 /* 596 */ "trn1.16b\t\0"
105 /* 606 */ "zip1.16b\t\0"
106 /* 616 */ "uzp1.16b\t\0"
107 /* 626 */ "rev32.16b\t\0"
108 /* 637 */ "rsubhn2.16b\t\0"
109 /* 650 */ "raddhn2.16b\t\0"
110 /* 663 */ "sqshrn2.16b\t\0"
111 /* 676 */ "uqshrn2.16b\t\0"
112 /* 689 */ "sqrshrn2.16b\t\0"
113 /* 703 */ "uqrshrn2.16b\t\0"
114 /* 717 */ "trn2.16b\t\0"
115 /* 727 */ "sqxtn2.16b\t\0"
116 /* 739 */ "uqxtn2.16b\t\0"
117 /* 751 */ "sqshrun2.16b\t\0"
118 /* 765 */ "sqrshrun2.16b\t\0"
119 /* 780 */ "sqxtun2.16b\t\0"
120 /* 793 */ "zip2.16b\t\0"
121 /* 803 */ "uzp2.16b\t\0"
122 /* 813 */ "eor3.16b\t\0"
123 /* 823 */ "rev64.16b\t\0"
124 /* 834 */ "rev16.16b\t\0"
125 /* 845 */ "saba.16b\t\0"
126 /* 855 */ "uaba.16b\t\0"
127 /* 865 */ "mla.16b\t\0"
128 /* 874 */ "srsra.16b\t\0"
129 /* 885 */ "ursra.16b\t\0"
130 /* 896 */ "ssra.16b\t\0"
131 /* 906 */ "usra.16b\t\0"
132 /* 916 */ "shsub.16b\t\0"
133 /* 927 */ "uhsub.16b\t\0"
134 /* 938 */ "sqsub.16b\t\0"
135 /* 949 */ "uqsub.16b\t\0"
136 /* 960 */ "bic.16b\t\0"
137 /* 969 */ "aesimc.16b\t\0"
138 /* 981 */ "aesmc.16b\t\0"
139 /* 992 */ "sabd.16b\t\0"
140 /* 1002 */ "uabd.16b\t\0"
141 /* 1012 */ "srhadd.16b\t\0"
142 /* 1024 */ "urhadd.16b\t\0"
143 /* 1036 */ "shadd.16b\t\0"
144 /* 1047 */ "uhadd.16b\t\0"
145 /* 1058 */ "usqadd.16b\t\0"
146 /* 1070 */ "suqadd.16b\t\0"
147 /* 1082 */ "and.16b\t\0"
148 /* 1091 */ "aesd.16b\t\0"
149 /* 1101 */ "cmge.16b\t\0"
150 /* 1111 */ "cmle.16b\t\0"
151 /* 1121 */ "aese.16b\t\0"
152 /* 1131 */ "bif.16b\t\0"
153 /* 1140 */ "sqneg.16b\t\0"
154 /* 1151 */ "cmhi.16b\t\0"
155 /* 1161 */ "sli.16b\t\0"
156 /* 1170 */ "sri.16b\t\0"
157 /* 1179 */ "movi.16b\t\0"
158 /* 1189 */ "sqshl.16b\t\0"
159 /* 1200 */ "uqshl.16b\t\0"
160 /* 1211 */ "sqrshl.16b\t\0"
161 /* 1223 */ "uqrshl.16b\t\0"
162 /* 1235 */ "srshl.16b\t\0"
163 /* 1246 */ "urshl.16b\t\0"
164 /* 1257 */ "sshl.16b\t\0"
165 /* 1267 */ "ushl.16b\t\0"
166 /* 1277 */ "bsl.16b\t\0"
167 /* 1286 */ "pmul.16b\t\0"
168 /* 1296 */ "smin.16b\t\0"
169 /* 1306 */ "umin.16b\t\0"
170 /* 1316 */ "orn.16b\t\0"
171 /* 1325 */ "addp.16b\t\0"
172 /* 1335 */ "sminp.16b\t\0"
173 /* 1346 */ "uminp.16b\t\0"
174 /* 1357 */ "dup.16b\t\0"
175 /* 1366 */ "smaxp.16b\t\0"
176 /* 1377 */ "umaxp.16b\t\0"
177 /* 1388 */ "cmeq.16b\t\0"
178 /* 1398 */ "srshr.16b\t\0"
179 /* 1409 */ "urshr.16b\t\0"
180 /* 1420 */ "sshr.16b\t\0"
181 /* 1430 */ "ushr.16b\t\0"
182 /* 1440 */ "eor.16b\t\0"
183 /* 1449 */ "orr.16b\t\0"
184 /* 1458 */ "sqabs.16b\t\0"
185 /* 1469 */ "cmhs.16b\t\0"
186 /* 1479 */ "cls.16b\t\0"
187 /* 1488 */ "mls.16b\t\0"
188 /* 1497 */ "cmgt.16b\t\0"
189 /* 1507 */ "rbit.16b\t\0"
190 /* 1517 */ "cmlt.16b\t\0"
191 /* 1527 */ "cnt.16b\t\0"
192 /* 1536 */ "not.16b\t\0"
193 /* 1545 */ "cmtst.16b\t\0"
194 /* 1556 */ "ext.16b\t\0"
195 /* 1565 */ "sqshlu.16b\t\0"
196 /* 1577 */ "addv.16b\t\0"
197 /* 1587 */ "saddlv.16b\t\0"
198 /* 1599 */ "uaddlv.16b\t\0"
199 /* 1611 */ "sminv.16b\t\0"
200 /* 1622 */ "uminv.16b\t\0"
201 /* 1633 */ "smaxv.16b\t\0"
202 /* 1644 */ "umaxv.16b\t\0"
203 /* 1655 */ "bcax.16b\t\0"
204 /* 1665 */ "smax.16b\t\0"
205 /* 1675 */ "umax.16b\t\0"
206 /* 1685 */ "clz.16b\t\0"
207 /* 1694 */ "trn1.8b\t\0"
208 /* 1703 */ "zip1.8b\t\0"
209 /* 1712 */ "uzp1.8b\t\0"
210 /* 1721 */ "rev32.8b\t\0"
211 /* 1731 */ "trn2.8b\t\0"
212 /* 1740 */ "zip2.8b\t\0"
213 /* 1749 */ "uzp2.8b\t\0"
214 /* 1758 */ "rev64.8b\t\0"
215 /* 1768 */ "rev16.8b\t\0"
216 /* 1778 */ "saba.8b\t\0"
217 /* 1787 */ "uaba.8b\t\0"
218 /* 1796 */ "mla.8b\t\0"
219 /* 1804 */ "srsra.8b\t\0"
220 /* 1814 */ "ursra.8b\t\0"
221 /* 1824 */ "ssra.8b\t\0"
222 /* 1833 */ "usra.8b\t\0"
223 /* 1842 */ "shsub.8b\t\0"
224 /* 1852 */ "uhsub.8b\t\0"
225 /* 1862 */ "sqsub.8b\t\0"
226 /* 1872 */ "uqsub.8b\t\0"
227 /* 1882 */ "bic.8b\t\0"
228 /* 1890 */ "sabd.8b\t\0"
229 /* 1899 */ "uabd.8b\t\0"
230 /* 1908 */ "srhadd.8b\t\0"
231 /* 1919 */ "urhadd.8b\t\0"
232 /* 1930 */ "shadd.8b\t\0"
233 /* 1940 */ "uhadd.8b\t\0"
234 /* 1950 */ "usqadd.8b\t\0"
235 /* 1961 */ "suqadd.8b\t\0"
236 /* 1972 */ "and.8b\t\0"
237 /* 1980 */ "cmge.8b\t\0"
238 /* 1989 */ "cmle.8b\t\0"
239 /* 1998 */ "bif.8b\t\0"
240 /* 2006 */ "sqneg.8b\t\0"
241 /* 2016 */ "cmhi.8b\t\0"
242 /* 2025 */ "sli.8b\t\0"
243 /* 2033 */ "sri.8b\t\0"
244 /* 2041 */ "movi.8b\t\0"
245 /* 2050 */ "sqshl.8b\t\0"
246 /* 2060 */ "uqshl.8b\t\0"
247 /* 2070 */ "sqrshl.8b\t\0"
248 /* 2081 */ "uqrshl.8b\t\0"
249 /* 2092 */ "srshl.8b\t\0"
250 /* 2102 */ "urshl.8b\t\0"
251 /* 2112 */ "sshl.8b\t\0"
252 /* 2121 */ "ushl.8b\t\0"
253 /* 2130 */ "bsl.8b\t\0"
254 /* 2138 */ "pmul.8b\t\0"
255 /* 2147 */ "rsubhn.8b\t\0"
256 /* 2158 */ "raddhn.8b\t\0"
257 /* 2169 */ "smin.8b\t\0"
258 /* 2178 */ "umin.8b\t\0"
259 /* 2187 */ "sqshrn.8b\t\0"
260 /* 2198 */ "uqshrn.8b\t\0"
261 /* 2209 */ "sqrshrn.8b\t\0"
262 /* 2221 */ "uqrshrn.8b\t\0"
263 /* 2233 */ "orn.8b\t\0"
264 /* 2241 */ "sqxtn.8b\t\0"
265 /* 2251 */ "uqxtn.8b\t\0"
266 /* 2261 */ "sqshrun.8b\t\0"
267 /* 2273 */ "sqrshrun.8b\t\0"
268 /* 2286 */ "sqxtun.8b\t\0"
269 /* 2297 */ "addp.8b\t\0"
270 /* 2306 */ "sminp.8b\t\0"
271 /* 2316 */ "uminp.8b\t\0"
272 /* 2326 */ "dup.8b\t\0"
273 /* 2334 */ "smaxp.8b\t\0"
274 /* 2344 */ "umaxp.8b\t\0"
275 /* 2354 */ "cmeq.8b\t\0"
276 /* 2363 */ "srshr.8b\t\0"
277 /* 2373 */ "urshr.8b\t\0"
278 /* 2383 */ "sshr.8b\t\0"
279 /* 2392 */ "ushr.8b\t\0"
280 /* 2401 */ "eor.8b\t\0"
281 /* 2409 */ "orr.8b\t\0"
282 /* 2417 */ "sqabs.8b\t\0"
283 /* 2427 */ "cmhs.8b\t\0"
284 /* 2436 */ "cls.8b\t\0"
285 /* 2444 */ "mls.8b\t\0"
286 /* 2452 */ "cmgt.8b\t\0"
287 /* 2461 */ "rbit.8b\t\0"
288 /* 2470 */ "cmlt.8b\t\0"
289 /* 2479 */ "cnt.8b\t\0"
290 /* 2487 */ "not.8b\t\0"
291 /* 2495 */ "cmtst.8b\t\0"
292 /* 2505 */ "ext.8b\t\0"
293 /* 2513 */ "sqshlu.8b\t\0"
294 /* 2524 */ "addv.8b\t\0"
295 /* 2533 */ "saddlv.8b\t\0"
296 /* 2544 */ "uaddlv.8b\t\0"
297 /* 2555 */ "sminv.8b\t\0"
298 /* 2565 */ "uminv.8b\t\0"
299 /* 2575 */ "smaxv.8b\t\0"
300 /* 2585 */ "umaxv.8b\t\0"
301 /* 2595 */ "smax.8b\t\0"
302 /* 2604 */ "umax.8b\t\0"
303 /* 2613 */ "clz.8b\t\0"
304 /* 2621 */ "ldaddab\t\0"
305 /* 2630 */ "ldsminab\t\0"
306 /* 2640 */ "lduminab\t\0"
307 /* 2650 */ "swpab\t\0"
308 /* 2657 */ "brab\t\0"
309 /* 2663 */ "ldrab\t\0"
310 /* 2670 */ "blrab\t\0"
311 /* 2677 */ "ldclrab\t\0"
312 /* 2686 */ "ldeorab\t\0"
313 /* 2695 */ "casab\t\0"
314 /* 2702 */ "ldsetab\t\0"
315 /* 2711 */ "ldsmaxab\t\0"
316 /* 2721 */ "ldumaxab\t\0"
317 /* 2731 */ "crc32cb\t\0"
318 /* 2740 */ "sqdecb\t\0"
319 /* 2748 */ "uqdecb\t\0"
320 /* 2756 */ "sqincb\t\0"
321 /* 2764 */ "uqincb\t\0"
322 /* 2772 */ "pacdb\t\0"
323 /* 2779 */ "ldaddb\t\0"
324 /* 2787 */ "autdb\t\0"
325 /* 2794 */ "prfb\t\0"
326 /* 2800 */ "flogb\t\0"
327 /* 2807 */ "pacib\t\0"
328 /* 2814 */ "autib\t\0"
329 /* 2821 */ "brkb\t\0"
330 /* 2827 */ "sabalb\t\0"
331 /* 2835 */ "uabalb\t\0"
332 /* 2843 */ "ldaddalb\t\0"
333 /* 2853 */ "sqdmlalb\t\0"
334 /* 2863 */ "bfmlalb\t\0"
335 /* 2872 */ "smlalb\t\0"
336 /* 2880 */ "umlalb\t\0"
337 /* 2888 */ "ldsminalb\t\0"
338 /* 2899 */ "lduminalb\t\0"
339 /* 2910 */ "swpalb\t\0"
340 /* 2918 */ "ldclralb\t\0"
341 /* 2928 */ "ldeoralb\t\0"
342 /* 2938 */ "casalb\t\0"
343 /* 2946 */ "ldsetalb\t\0"
344 /* 2956 */ "ldsmaxalb\t\0"
345 /* 2967 */ "ldumaxalb\t\0"
346 /* 2978 */ "ssublb\t\0"
347 /* 2986 */ "usublb\t\0"
348 /* 2994 */ "sbclb\t\0"
349 /* 3001 */ "adclb\t\0"
350 /* 3008 */ "sabdlb\t\0"
351 /* 3016 */ "uabdlb\t\0"
352 /* 3024 */ "ldaddlb\t\0"
353 /* 3033 */ "saddlb\t\0"
354 /* 3041 */ "uaddlb\t\0"
355 /* 3049 */ "sshllb\t\0"
356 /* 3057 */ "ushllb\t\0"
357 /* 3065 */ "sqdmullb\t\0"
358 /* 3075 */ "pmullb\t\0"
359 /* 3083 */ "smullb\t\0"
360 /* 3091 */ "umullb\t\0"
361 /* 3099 */ "ldsminlb\t\0"
362 /* 3109 */ "lduminlb\t\0"
363 /* 3119 */ "swplb\t\0"
364 /* 3126 */ "ldclrlb\t\0"
365 /* 3135 */ "ldeorlb\t\0"
366 /* 3144 */ "caslb\t\0"
367 /* 3151 */ "sqdmlslb\t\0"
368 /* 3161 */ "fmlslb\t\0"
369 /* 3169 */ "smlslb\t\0"
370 /* 3177 */ "umlslb\t\0"
371 /* 3185 */ "ldsetlb\t\0"
372 /* 3194 */ "ldsmaxlb\t\0"
373 /* 3204 */ "ldumaxlb\t\0"
374 /* 3214 */ "dmb\t\0"
375 /* 3219 */ "rsubhnb\t\0"
376 /* 3228 */ "raddhnb\t\0"
377 /* 3237 */ "ldsminb\t\0"
378 /* 3246 */ "lduminb\t\0"
379 /* 3255 */ "sqshrnb\t\0"
380 /* 3264 */ "uqshrnb\t\0"
381 /* 3273 */ "sqrshrnb\t\0"
382 /* 3283 */ "uqrshrnb\t\0"
383 /* 3293 */ "sqxtnb\t\0"
384 /* 3301 */ "uqxtnb\t\0"
385 /* 3309 */ "sqshrunb\t\0"
386 /* 3319 */ "sqrshrunb\t\0"
387 /* 3330 */ "sqxtunb\t\0"
388 /* 3339 */ "ld1rob\t\0"
389 /* 3347 */ "brkpb\t\0"
390 /* 3354 */ "swpb\t\0"
391 /* 3360 */ "ld1rqb\t\0"
392 /* 3368 */ "ld1rb\t\0"
393 /* 3375 */ "ldarb\t\0"
394 /* 3382 */ "ldlarb\t\0"
395 /* 3390 */ "ldrb\t\0"
396 /* 3396 */ "ldclrb\t\0"
397 /* 3404 */ "stllrb\t\0"
398 /* 3412 */ "stlrb\t\0"
399 /* 3419 */ "ldeorb\t\0"
400 /* 3427 */ "ldaprb\t\0"
401 /* 3435 */ "ldtrb\t\0"
402 /* 3442 */ "strb\t\0"
403 /* 3448 */ "sttrb\t\0"
404 /* 3455 */ "ldurb\t\0"
405 /* 3462 */ "stlurb\t\0"
406 /* 3470 */ "ldapurb\t\0"
407 /* 3479 */ "sturb\t\0"
408 /* 3486 */ "ldaxrb\t\0"
409 /* 3494 */ "ldxrb\t\0"
410 /* 3501 */ "stlxrb\t\0"
411 /* 3509 */ "stxrb\t\0"
412 /* 3516 */ "ld1sb\t\0"
413 /* 3523 */ "ldff1sb\t\0"
414 /* 3532 */ "ldnf1sb\t\0"
415 /* 3541 */ "ldnt1sb\t\0"
416 /* 3550 */ "casb\t\0"
417 /* 3556 */ "dsb\t\0"
418 /* 3561 */ "isb\t\0"
419 /* 3566 */ "fmsb\t\0"
420 /* 3572 */ "fnmsb\t\0"
421 /* 3579 */ "ld1rsb\t\0"
422 /* 3587 */ "ldrsb\t\0"
423 /* 3594 */ "ldtrsb\t\0"
424 /* 3602 */ "ldursb\t\0"
425 /* 3610 */ "ldapursb\t\0"
426 /* 3620 */ "tsb\t\0"
427 /* 3625 */ "ldsetb\t\0"
428 /* 3633 */ "ssubltb\t\0"
429 /* 3642 */ "cntb\t\0"
430 /* 3648 */ "eortb\t\0"
431 /* 3655 */ "clastb\t\0"
432 /* 3663 */ "sxtb\t\0"
433 /* 3669 */ "uxtb\t\0"
434 /* 3675 */ "fsub\t\0"
435 /* 3681 */ "shsub\t\0"
436 /* 3688 */ "uhsub\t\0"
437 /* 3695 */ "fmsub\t\0"
438 /* 3702 */ "fnmsub\t\0"
439 /* 3710 */ "sqsub\t\0"
440 /* 3717 */ "uqsub\t\0"
441 /* 3724 */ "revb\t\0"
442 /* 3730 */ "ssubwb\t\0"
443 /* 3738 */ "usubwb\t\0"
444 /* 3746 */ "saddwb\t\0"
445 /* 3754 */ "uaddwb\t\0"
446 /* 3762 */ "ldsmaxb\t\0"
447 /* 3771 */ "ldumaxb\t\0"
448 /* 3780 */ "pacdzb\t\0"
449 /* 3788 */ "autdzb\t\0"
450 /* 3796 */ "pacizb\t\0"
451 /* 3804 */ "autizb\t\0"
452 /* 3812 */ "sbc\t\0"
453 /* 3817 */ "adc\t\0"
454 /* 3822 */ "bic\t\0"
455 /* 3827 */ "aesimc\t\0"
456 /* 3835 */ "aesmc\t\0"
457 /* 3842 */ "csinc\t\0"
458 /* 3849 */ "hvc\t\0"
459 /* 3854 */ "svc\t\0"
460 /* 3859 */ "fmla.d\t\0"
461 /* 3867 */ "fmul.d\t\0"
462 /* 3875 */ "fmls.d\t\0"
463 /* 3883 */ "ins.d\t\0"
464 /* 3890 */ "fmov.d\t\0"
465 /* 3898 */ "umov.d\t\0"
466 /* 3906 */ "fmulx.d\t\0"
467 /* 3915 */ "sadalp.1d\t\0"
468 /* 3926 */ "uadalp.1d\t\0"
469 /* 3937 */ "saddlp.1d\t\0"
470 /* 3948 */ "uaddlp.1d\t\0"
471 /* 3959 */ "ld1d\t\0"
472 /* 3965 */ "ldff1d\t\0"
473 /* 3973 */ "ldnf1d\t\0"
474 /* 3981 */ "ldnt1d\t\0"
475 /* 3989 */ "stnt1d\t\0"
476 /* 3997 */ "st1d\t\0"
477 /* 4003 */ "sha512su0.2d\t\0"
478 /* 4017 */ "trn1.2d\t\0"
479 /* 4026 */ "zip1.2d\t\0"
480 /* 4035 */ "uzp1.2d\t\0"
481 /* 4044 */ "sha512su1.2d\t\0"
482 /* 4058 */ "rax1.2d\t\0"
483 /* 4067 */ "sha512h2.2d\t\0"
484 /* 4080 */ "sabal2.2d\t\0"
485 /* 4091 */ "uabal2.2d\t\0"
486 /* 4102 */ "sqdmlal2.2d\t\0"
487 /* 4115 */ "smlal2.2d\t\0"
488 /* 4126 */ "umlal2.2d\t\0"
489 /* 4137 */ "ssubl2.2d\t\0"
490 /* 4148 */ "usubl2.2d\t\0"
491 /* 4159 */ "sabdl2.2d\t\0"
492 /* 4170 */ "uabdl2.2d\t\0"
493 /* 4181 */ "saddl2.2d\t\0"
494 /* 4192 */ "uaddl2.2d\t\0"
495 /* 4203 */ "sshll2.2d\t\0"
496 /* 4214 */ "ushll2.2d\t\0"
497 /* 4225 */ "sqdmull2.2d\t\0"
498 /* 4238 */ "smull2.2d\t\0"
499 /* 4249 */ "umull2.2d\t\0"
500 /* 4260 */ "sqdmlsl2.2d\t\0"
501 /* 4273 */ "smlsl2.2d\t\0"
502 /* 4284 */ "umlsl2.2d\t\0"
503 /* 4295 */ "trn2.2d\t\0"
504 /* 4304 */ "zip2.2d\t\0"
505 /* 4313 */ "uzp2.2d\t\0"
506 /* 4322 */ "ssubw2.2d\t\0"
507 /* 4333 */ "usubw2.2d\t\0"
508 /* 4344 */ "saddw2.2d\t\0"
509 /* 4355 */ "uaddw2.2d\t\0"
510 /* 4366 */ "fcmla.2d\t\0"
511 /* 4376 */ "fmla.2d\t\0"
512 /* 4385 */ "srsra.2d\t\0"
513 /* 4395 */ "ursra.2d\t\0"
514 /* 4405 */ "ssra.2d\t\0"
515 /* 4414 */ "usra.2d\t\0"
516 /* 4423 */ "frinta.2d\t\0"
517 /* 4434 */ "fsub.2d\t\0"
518 /* 4443 */ "sqsub.2d\t\0"
519 /* 4453 */ "uqsub.2d\t\0"
520 /* 4463 */ "fabd.2d\t\0"
521 /* 4472 */ "fcadd.2d\t\0"
522 /* 4482 */ "fadd.2d\t\0"
523 /* 4491 */ "usqadd.2d\t\0"
524 /* 4502 */ "suqadd.2d\t\0"
525 /* 4513 */ "facge.2d\t\0"
526 /* 4523 */ "fcmge.2d\t\0"
527 /* 4533 */ "fcmle.2d\t\0"
528 /* 4543 */ "frecpe.2d\t\0"
529 /* 4554 */ "frsqrte.2d\t\0"
530 /* 4566 */ "scvtf.2d\t\0"
531 /* 4576 */ "ucvtf.2d\t\0"
532 /* 4586 */ "fneg.2d\t\0"
533 /* 4595 */ "sqneg.2d\t\0"
534 /* 4605 */ "sha512h.2d\t\0"
535 /* 4617 */ "cmhi.2d\t\0"
536 /* 4626 */ "sli.2d\t\0"
537 /* 4634 */ "sri.2d\t\0"
538 /* 4642 */ "frinti.2d\t\0"
539 /* 4653 */ "movi.2d\t\0"
540 /* 4662 */ "sabal.2d\t\0"
541 /* 4672 */ "uabal.2d\t\0"
542 /* 4682 */ "sqdmlal.2d\t\0"
543 /* 4694 */ "smlal.2d\t\0"
544 /* 4704 */ "umlal.2d\t\0"
545 /* 4714 */ "ssubl.2d\t\0"
546 /* 4724 */ "usubl.2d\t\0"
547 /* 4734 */ "sabdl.2d\t\0"
548 /* 4744 */ "uabdl.2d\t\0"
549 /* 4754 */ "saddl.2d\t\0"
550 /* 4764 */ "uaddl.2d\t\0"
551 /* 4774 */ "sqshl.2d\t\0"
552 /* 4784 */ "uqshl.2d\t\0"
553 /* 4794 */ "sqrshl.2d\t\0"
554 /* 4805 */ "uqrshl.2d\t\0"
555 /* 4816 */ "srshl.2d\t\0"
556 /* 4826 */ "urshl.2d\t\0"
557 /* 4836 */ "sshl.2d\t\0"
558 /* 4845 */ "ushl.2d\t\0"
559 /* 4854 */ "sshll.2d\t\0"
560 /* 4864 */ "ushll.2d\t\0"
561 /* 4874 */ "sqdmull.2d\t\0"
562 /* 4886 */ "smull.2d\t\0"
563 /* 4896 */ "umull.2d\t\0"
564 /* 4906 */ "sqdmlsl.2d\t\0"
565 /* 4918 */ "smlsl.2d\t\0"
566 /* 4928 */ "umlsl.2d\t\0"
567 /* 4938 */ "fmul.2d\t\0"
568 /* 4947 */ "fminnm.2d\t\0"
569 /* 4958 */ "fmaxnm.2d\t\0"
570 /* 4969 */ "frintm.2d\t\0"
571 /* 4980 */ "fmin.2d\t\0"
572 /* 4989 */ "frintn.2d\t\0"
573 /* 5000 */ "faddp.2d\t\0"
574 /* 5010 */ "sadalp.2d\t\0"
575 /* 5021 */ "uadalp.2d\t\0"
576 /* 5032 */ "saddlp.2d\t\0"
577 /* 5043 */ "uaddlp.2d\t\0"
578 /* 5054 */ "fminnmp.2d\t\0"
579 /* 5066 */ "fmaxnmp.2d\t\0"
580 /* 5078 */ "fminp.2d\t\0"
581 /* 5088 */ "frintp.2d\t\0"
582 /* 5099 */ "dup.2d\t\0"
583 /* 5107 */ "fmaxp.2d\t\0"
584 /* 5117 */ "fcmeq.2d\t\0"
585 /* 5127 */ "xar.2d\t\0"
586 /* 5135 */ "srshr.2d\t\0"
587 /* 5145 */ "urshr.2d\t\0"
588 /* 5155 */ "sshr.2d\t\0"
589 /* 5164 */ "ushr.2d\t\0"
590 /* 5173 */ "fcvtas.2d\t\0"
591 /* 5184 */ "fabs.2d\t\0"
592 /* 5193 */ "sqabs.2d\t\0"
593 /* 5203 */ "cmhs.2d\t\0"
594 /* 5212 */ "fmls.2d\t\0"
595 /* 5221 */ "fcvtms.2d\t\0"
596 /* 5232 */ "fcvtns.2d\t\0"
597 /* 5243 */ "frecps.2d\t\0"
598 /* 5254 */ "fcvtps.2d\t\0"
599 /* 5265 */ "frsqrts.2d\t\0"
600 /* 5277 */ "fcvtzs.2d\t\0"
601 /* 5288 */ "facgt.2d\t\0"
602 /* 5298 */ "fcmgt.2d\t\0"
603 /* 5308 */ "fcmlt.2d\t\0"
604 /* 5318 */ "fsqrt.2d\t\0"
605 /* 5328 */ "cmtst.2d\t\0"
606 /* 5338 */ "fcvtau.2d\t\0"
607 /* 5349 */ "sqshlu.2d\t\0"
608 /* 5360 */ "fcvtmu.2d\t\0"
609 /* 5371 */ "fcvtnu.2d\t\0"
610 /* 5382 */ "fcvtpu.2d\t\0"
611 /* 5393 */ "fcvtzu.2d\t\0"
612 /* 5404 */ "fdiv.2d\t\0"
613 /* 5413 */ "fmov.2d\t\0"
614 /* 5422 */ "ssubw.2d\t\0"
615 /* 5432 */ "usubw.2d\t\0"
616 /* 5442 */ "saddw.2d\t\0"
617 /* 5452 */ "uaddw.2d\t\0"
618 /* 5462 */ "frint32x.2d\t\0"
619 /* 5475 */ "frint64x.2d\t\0"
620 /* 5488 */ "fmax.2d\t\0"
621 /* 5497 */ "fmulx.2d\t\0"
622 /* 5507 */ "frintx.2d\t\0"
623 /* 5518 */ "frint32z.2d\t\0"
624 /* 5531 */ "frint64z.2d\t\0"
625 /* 5544 */ "frintz.2d\t\0"
626 /* 5555 */ "ld2d\t\0"
627 /* 5561 */ "st2d\t\0"
628 /* 5567 */ "ld3d\t\0"
629 /* 5573 */ "st3d\t\0"
630 /* 5579 */ "ld4d\t\0"
631 /* 5585 */ "st4d\t\0"
632 /* 5591 */ "fmad\t\0"
633 /* 5597 */ "fnmad\t\0"
634 /* 5604 */ "ftmad\t\0"
635 /* 5611 */ "fabd\t\0"
636 /* 5617 */ "sabd\t\0"
637 /* 5623 */ "uabd\t\0"
638 /* 5629 */ "xpacd\t\0"
639 /* 5636 */ "sqdecd\t\0"
640 /* 5644 */ "uqdecd\t\0"
641 /* 5652 */ "sqincd\t\0"
642 /* 5660 */ "uqincd\t\0"
643 /* 5668 */ "fcadd\t\0"
644 /* 5675 */ "sqcadd\t\0"
645 /* 5683 */ "ldadd\t\0"
646 /* 5690 */ "fadd\t\0"
647 /* 5696 */ "srhadd\t\0"
648 /* 5704 */ "urhadd\t\0"
649 /* 5712 */ "shadd\t\0"
650 /* 5719 */ "uhadd\t\0"
651 /* 5726 */ "fmadd\t\0"
652 /* 5733 */ "fnmadd\t\0"
653 /* 5741 */ "usqadd\t\0"
654 /* 5749 */ "suqadd\t\0"
655 /* 5757 */ "prfd\t\0"
656 /* 5763 */ "nand\t\0"
657 /* 5769 */ "ld1rod\t\0"
658 /* 5777 */ "ld1rqd\t\0"
659 /* 5785 */ "ld1rd\t\0"
660 /* 5792 */ "asrd\t\0"
661 /* 5798 */ "aesd\t\0"
662 /* 5804 */ "cntd\t\0"
663 /* 5810 */ "sm4e\t\0"
664 /* 5816 */ "splice\t\0"
665 /* 5824 */ "facge\t\0"
666 /* 5831 */ "whilege\t\0"
667 /* 5840 */ "fcmge\t\0"
668 /* 5847 */ "cmpge\t\0"
669 /* 5854 */ "fscale\t\0"
670 /* 5862 */ "whilele\t\0"
671 /* 5871 */ "fcmle\t\0"
672 /* 5878 */ "cmple\t\0"
673 /* 5885 */ "fcmne\t\0"
674 /* 5892 */ "ctermne\t\0"
675 /* 5901 */ "cmpne\t\0"
676 /* 5908 */ "frecpe\t\0"
677 /* 5916 */ "urecpe\t\0"
678 /* 5924 */ "fccmpe\t\0"
679 /* 5932 */ "fcmpe\t\0"
680 /* 5939 */ "aese\t\0"
681 /* 5945 */ "pfalse\t\0"
682 /* 5953 */ "frsqrte\t\0"
683 /* 5962 */ "ursqrte\t\0"
684 /* 5971 */ "ptrue\t\0"
685 /* 5978 */ "udf\t\0"
686 /* 5983 */ "scvtf\t\0"
687 /* 5990 */ "ucvtf\t\0"
688 /* 5997 */ "st2g\t\0"
689 /* 6003 */ "stz2g\t\0"
690 /* 6010 */ "subg\t\0"
691 /* 6016 */ "addg\t\0"
692 /* 6022 */ "ldg\t\0"
693 /* 6027 */ "fneg\t\0"
694 /* 6033 */ "sqneg\t\0"
695 /* 6040 */ "csneg\t\0"
696 /* 6047 */ "histseg\t\0"
697 /* 6056 */ "irg\t\0"
698 /* 6061 */ "stg\t\0"
699 /* 6066 */ "stzg\t\0"
700 /* 6072 */ "fmla.h\t\0"
701 /* 6080 */ "sqrdmlah.h\t\0"
702 /* 6092 */ "sqdmulh.h\t\0"
703 /* 6103 */ "sqrdmulh.h\t\0"
704 /* 6115 */ "sqrdmlsh.h\t\0"
705 /* 6127 */ "sqdmlal.h\t\0"
706 /* 6138 */ "sqdmull.h\t\0"
707 /* 6149 */ "sqdmlsl.h\t\0"
708 /* 6160 */ "fmul.h\t\0"
709 /* 6168 */ "fmls.h\t\0"
710 /* 6176 */ "ins.h\t\0"
711 /* 6183 */ "smov.h\t\0"
712 /* 6191 */ "umov.h\t\0"
713 /* 6199 */ "fmulx.h\t\0"
714 /* 6208 */ "sha1h\t\0"
715 /* 6215 */ "ld1h\t\0"
716 /* 6221 */ "ldff1h\t\0"
717 /* 6229 */ "ldnf1h\t\0"
718 /* 6237 */ "ldnt1h\t\0"
719 /* 6245 */ "stnt1h\t\0"
720 /* 6253 */ "st1h\t\0"
721 /* 6259 */ "faddp.2h\t\0"
722 /* 6269 */ "fminnmp.2h\t\0"
723 /* 6281 */ "fmaxnmp.2h\t\0"
724 /* 6293 */ "fminp.2h\t\0"
725 /* 6303 */ "fmaxp.2h\t\0"
726 /* 6313 */ "crc32h\t\0"
727 /* 6321 */ "ld2h\t\0"
728 /* 6327 */ "st2h\t\0"
729 /* 6333 */ "ld3h\t\0"
730 /* 6339 */ "st3h\t\0"
731 /* 6345 */ "trn1.4h\t\0"
732 /* 6354 */ "zip1.4h\t\0"
733 /* 6363 */ "uzp1.4h\t\0"
734 /* 6372 */ "rev32.4h\t\0"
735 /* 6382 */ "trn2.4h\t\0"
736 /* 6391 */ "zip2.4h\t\0"
737 /* 6400 */ "uzp2.4h\t\0"
738 /* 6409 */ "rev64.4h\t\0"
739 /* 6419 */ "saba.4h\t\0"
740 /* 6428 */ "uaba.4h\t\0"
741 /* 6437 */ "fcmla.4h\t\0"
742 /* 6447 */ "fmla.4h\t\0"
743 /* 6456 */ "srsra.4h\t\0"
744 /* 6466 */ "ursra.4h\t\0"
745 /* 6476 */ "ssra.4h\t\0"
746 /* 6485 */ "usra.4h\t\0"
747 /* 6494 */ "frinta.4h\t\0"
748 /* 6505 */ "fsub.4h\t\0"
749 /* 6514 */ "shsub.4h\t\0"
750 /* 6524 */ "uhsub.4h\t\0"
751 /* 6534 */ "sqsub.4h\t\0"
752 /* 6544 */ "uqsub.4h\t\0"
753 /* 6554 */ "bic.4h\t\0"
754 /* 6562 */ "fabd.4h\t\0"
755 /* 6571 */ "sabd.4h\t\0"
756 /* 6580 */ "uabd.4h\t\0"
757 /* 6589 */ "fcadd.4h\t\0"
758 /* 6599 */ "fadd.4h\t\0"
759 /* 6608 */ "srhadd.4h\t\0"
760 /* 6619 */ "urhadd.4h\t\0"
761 /* 6630 */ "shadd.4h\t\0"
762 /* 6640 */ "uhadd.4h\t\0"
763 /* 6650 */ "usqadd.4h\t\0"
764 /* 6661 */ "suqadd.4h\t\0"
765 /* 6672 */ "facge.4h\t\0"
766 /* 6682 */ "fcmge.4h\t\0"
767 /* 6692 */ "fcmle.4h\t\0"
768 /* 6702 */ "frecpe.4h\t\0"
769 /* 6713 */ "frsqrte.4h\t\0"
770 /* 6725 */ "scvtf.4h\t\0"
771 /* 6735 */ "ucvtf.4h\t\0"
772 /* 6745 */ "fneg.4h\t\0"
773 /* 6754 */ "sqneg.4h\t\0"
774 /* 6764 */ "sqrdmlah.4h\t\0"
775 /* 6777 */ "sqdmulh.4h\t\0"
776 /* 6789 */ "sqrdmulh.4h\t\0"
777 /* 6802 */ "sqrdmlsh.4h\t\0"
778 /* 6815 */ "cmhi.4h\t\0"
779 /* 6824 */ "sli.4h\t\0"
780 /* 6832 */ "mvni.4h\t\0"
781 /* 6841 */ "sri.4h\t\0"
782 /* 6849 */ "frinti.4h\t\0"
783 /* 6860 */ "movi.4h\t\0"
784 /* 6869 */ "sqshl.4h\t\0"
785 /* 6879 */ "uqshl.4h\t\0"
786 /* 6889 */ "sqrshl.4h\t\0"
787 /* 6900 */ "uqrshl.4h\t\0"
788 /* 6911 */ "srshl.4h\t\0"
789 /* 6921 */ "urshl.4h\t\0"
790 /* 6931 */ "sshl.4h\t\0"
791 /* 6940 */ "ushl.4h\t\0"
792 /* 6949 */ "fmul.4h\t\0"
793 /* 6958 */ "fminnm.4h\t\0"
794 /* 6969 */ "fmaxnm.4h\t\0"
795 /* 6980 */ "frintm.4h\t\0"
796 /* 6991 */ "rsubhn.4h\t\0"
797 /* 7002 */ "raddhn.4h\t\0"
798 /* 7013 */ "fmin.4h\t\0"
799 /* 7022 */ "smin.4h\t\0"
800 /* 7031 */ "umin.4h\t\0"
801 /* 7040 */ "sqshrn.4h\t\0"
802 /* 7051 */ "uqshrn.4h\t\0"
803 /* 7062 */ "sqrshrn.4h\t\0"
804 /* 7074 */ "uqrshrn.4h\t\0"
805 /* 7086 */ "frintn.4h\t\0"
806 /* 7097 */ "bfcvtn.4h\t\0"
807 /* 7108 */ "sqxtn.4h\t\0"
808 /* 7118 */ "uqxtn.4h\t\0"
809 /* 7128 */ "sqshrun.4h\t\0"
810 /* 7140 */ "sqrshrun.4h\t\0"
811 /* 7153 */ "sqxtun.4h\t\0"
812 /* 7164 */ "faddp.4h\t\0"
813 /* 7174 */ "sadalp.4h\t\0"
814 /* 7185 */ "uadalp.4h\t\0"
815 /* 7196 */ "saddlp.4h\t\0"
816 /* 7207 */ "uaddlp.4h\t\0"
817 /* 7218 */ "fminnmp.4h\t\0"
818 /* 7230 */ "fmaxnmp.4h\t\0"
819 /* 7242 */ "fminp.4h\t\0"
820 /* 7252 */ "sminp.4h\t\0"
821 /* 7262 */ "uminp.4h\t\0"
822 /* 7272 */ "frintp.4h\t\0"
823 /* 7283 */ "dup.4h\t\0"
824 /* 7291 */ "fmaxp.4h\t\0"
825 /* 7301 */ "smaxp.4h\t\0"
826 /* 7311 */ "umaxp.4h\t\0"
827 /* 7321 */ "fcmeq.4h\t\0"
828 /* 7331 */ "srshr.4h\t\0"
829 /* 7341 */ "urshr.4h\t\0"
830 /* 7351 */ "sshr.4h\t\0"
831 /* 7360 */ "ushr.4h\t\0"
832 /* 7369 */ "orr.4h\t\0"
833 /* 7377 */ "fcvtas.4h\t\0"
834 /* 7388 */ "fabs.4h\t\0"
835 /* 7397 */ "sqabs.4h\t\0"
836 /* 7407 */ "cmhs.4h\t\0"
837 /* 7416 */ "cls.4h\t\0"
838 /* 7424 */ "fmls.4h\t\0"
839 /* 7433 */ "fcvtms.4h\t\0"
840 /* 7444 */ "fcvtns.4h\t\0"
841 /* 7455 */ "frecps.4h\t\0"
842 /* 7466 */ "fcvtps.4h\t\0"
843 /* 7477 */ "frsqrts.4h\t\0"
844 /* 7489 */ "fcvtzs.4h\t\0"
845 /* 7500 */ "facgt.4h\t\0"
846 /* 7510 */ "fcmgt.4h\t\0"
847 /* 7520 */ "fcmlt.4h\t\0"
848 /* 7530 */ "fsqrt.4h\t\0"
849 /* 7540 */ "cmtst.4h\t\0"
850 /* 7550 */ "fcvtau.4h\t\0"
851 /* 7561 */ "sqshlu.4h\t\0"
852 /* 7572 */ "fcvtmu.4h\t\0"
853 /* 7583 */ "fcvtnu.4h\t\0"
854 /* 7594 */ "fcvtpu.4h\t\0"
855 /* 7605 */ "fcvtzu.4h\t\0"
856 /* 7616 */ "addv.4h\t\0"
857 /* 7625 */ "fdiv.4h\t\0"
858 /* 7634 */ "saddlv.4h\t\0"
859 /* 7645 */ "uaddlv.4h\t\0"
860 /* 7656 */ "fminnmv.4h\t\0"
861 /* 7668 */ "fmaxnmv.4h\t\0"
862 /* 7680 */ "fminv.4h\t\0"
863 /* 7690 */ "sminv.4h\t\0"
864 /* 7700 */ "uminv.4h\t\0"
865 /* 7710 */ "fmov.4h\t\0"
866 /* 7719 */ "fmaxv.4h\t\0"
867 /* 7729 */ "smaxv.4h\t\0"
868 /* 7739 */ "umaxv.4h\t\0"
869 /* 7749 */ "fmax.4h\t\0"
870 /* 7758 */ "smax.4h\t\0"
871 /* 7767 */ "umax.4h\t\0"
872 /* 7776 */ "fmulx.4h\t\0"
873 /* 7786 */ "frintx.4h\t\0"
874 /* 7797 */ "clz.4h\t\0"
875 /* 7805 */ "frintz.4h\t\0"
876 /* 7816 */ "ld4h\t\0"
877 /* 7822 */ "st4h\t\0"
878 /* 7828 */ "trn1.8h\t\0"
879 /* 7837 */ "zip1.8h\t\0"
880 /* 7846 */ "uzp1.8h\t\0"
881 /* 7855 */ "rev32.8h\t\0"
882 /* 7865 */ "sabal2.8h\t\0"
883 /* 7876 */ "uabal2.8h\t\0"
884 /* 7887 */ "smlal2.8h\t\0"
885 /* 7898 */ "umlal2.8h\t\0"
886 /* 7909 */ "ssubl2.8h\t\0"
887 /* 7920 */ "usubl2.8h\t\0"
888 /* 7931 */ "sabdl2.8h\t\0"
889 /* 7942 */ "uabdl2.8h\t\0"
890 /* 7953 */ "saddl2.8h\t\0"
891 /* 7964 */ "uaddl2.8h\t\0"
892 /* 7975 */ "sshll2.8h\t\0"
893 /* 7986 */ "ushll2.8h\t\0"
894 /* 7997 */ "pmull2.8h\t\0"
895 /* 8008 */ "smull2.8h\t\0"
896 /* 8019 */ "umull2.8h\t\0"
897 /* 8030 */ "smlsl2.8h\t\0"
898 /* 8041 */ "umlsl2.8h\t\0"
899 /* 8052 */ "rsubhn2.8h\t\0"
900 /* 8064 */ "raddhn2.8h\t\0"
901 /* 8076 */ "sqshrn2.8h\t\0"
902 /* 8088 */ "uqshrn2.8h\t\0"
903 /* 8100 */ "sqrshrn2.8h\t\0"
904 /* 8113 */ "uqrshrn2.8h\t\0"
905 /* 8126 */ "trn2.8h\t\0"
906 /* 8135 */ "bfcvtn2.8h\t\0"
907 /* 8147 */ "sqxtn2.8h\t\0"
908 /* 8158 */ "uqxtn2.8h\t\0"
909 /* 8169 */ "sqshrun2.8h\t\0"
910 /* 8182 */ "sqrshrun2.8h\t\0"
911 /* 8196 */ "sqxtun2.8h\t\0"
912 /* 8208 */ "zip2.8h\t\0"
913 /* 8217 */ "uzp2.8h\t\0"
914 /* 8226 */ "ssubw2.8h\t\0"
915 /* 8237 */ "usubw2.8h\t\0"
916 /* 8248 */ "saddw2.8h\t\0"
917 /* 8259 */ "uaddw2.8h\t\0"
918 /* 8270 */ "rev64.8h\t\0"
919 /* 8280 */ "saba.8h\t\0"
920 /* 8289 */ "uaba.8h\t\0"
921 /* 8298 */ "fcmla.8h\t\0"
922 /* 8308 */ "fmla.8h\t\0"
923 /* 8317 */ "srsra.8h\t\0"
924 /* 8327 */ "ursra.8h\t\0"
925 /* 8337 */ "ssra.8h\t\0"
926 /* 8346 */ "usra.8h\t\0"
927 /* 8355 */ "frinta.8h\t\0"
928 /* 8366 */ "fsub.8h\t\0"
929 /* 8375 */ "shsub.8h\t\0"
930 /* 8385 */ "uhsub.8h\t\0"
931 /* 8395 */ "sqsub.8h\t\0"
932 /* 8405 */ "uqsub.8h\t\0"
933 /* 8415 */ "bic.8h\t\0"
934 /* 8423 */ "fabd.8h\t\0"
935 /* 8432 */ "sabd.8h\t\0"
936 /* 8441 */ "uabd.8h\t\0"
937 /* 8450 */ "fcadd.8h\t\0"
938 /* 8460 */ "fadd.8h\t\0"
939 /* 8469 */ "srhadd.8h\t\0"
940 /* 8480 */ "urhadd.8h\t\0"
941 /* 8491 */ "shadd.8h\t\0"
942 /* 8501 */ "uhadd.8h\t\0"
943 /* 8511 */ "usqadd.8h\t\0"
944 /* 8522 */ "suqadd.8h\t\0"
945 /* 8533 */ "facge.8h\t\0"
946 /* 8543 */ "fcmge.8h\t\0"
947 /* 8553 */ "fcmle.8h\t\0"
948 /* 8563 */ "frecpe.8h\t\0"
949 /* 8574 */ "frsqrte.8h\t\0"
950 /* 8586 */ "scvtf.8h\t\0"
951 /* 8596 */ "ucvtf.8h\t\0"
952 /* 8606 */ "fneg.8h\t\0"
953 /* 8615 */ "sqneg.8h\t\0"
954 /* 8625 */ "sqrdmlah.8h\t\0"
955 /* 8638 */ "sqdmulh.8h\t\0"
956 /* 8650 */ "sqrdmulh.8h\t\0"
957 /* 8663 */ "sqrdmlsh.8h\t\0"
958 /* 8676 */ "cmhi.8h\t\0"
959 /* 8685 */ "sli.8h\t\0"
960 /* 8693 */ "mvni.8h\t\0"
961 /* 8702 */ "sri.8h\t\0"
962 /* 8710 */ "frinti.8h\t\0"
963 /* 8721 */ "movi.8h\t\0"
964 /* 8730 */ "sabal.8h\t\0"
965 /* 8740 */ "uabal.8h\t\0"
966 /* 8750 */ "smlal.8h\t\0"
967 /* 8760 */ "umlal.8h\t\0"
968 /* 8770 */ "ssubl.8h\t\0"
969 /* 8780 */ "usubl.8h\t\0"
970 /* 8790 */ "sabdl.8h\t\0"
971 /* 8800 */ "uabdl.8h\t\0"
972 /* 8810 */ "saddl.8h\t\0"
973 /* 8820 */ "uaddl.8h\t\0"
974 /* 8830 */ "sqshl.8h\t\0"
975 /* 8840 */ "uqshl.8h\t\0"
976 /* 8850 */ "sqrshl.8h\t\0"
977 /* 8861 */ "uqrshl.8h\t\0"
978 /* 8872 */ "srshl.8h\t\0"
979 /* 8882 */ "urshl.8h\t\0"
980 /* 8892 */ "sshl.8h\t\0"
981 /* 8901 */ "ushl.8h\t\0"
982 /* 8910 */ "sshll.8h\t\0"
983 /* 8920 */ "ushll.8h\t\0"
984 /* 8930 */ "pmull.8h\t\0"
985 /* 8940 */ "smull.8h\t\0"
986 /* 8950 */ "umull.8h\t\0"
987 /* 8960 */ "smlsl.8h\t\0"
988 /* 8970 */ "umlsl.8h\t\0"
989 /* 8980 */ "fmul.8h\t\0"
990 /* 8989 */ "fminnm.8h\t\0"
991 /* 9000 */ "fmaxnm.8h\t\0"
992 /* 9011 */ "frintm.8h\t\0"
993 /* 9022 */ "fmin.8h\t\0"
994 /* 9031 */ "smin.8h\t\0"
995 /* 9040 */ "umin.8h\t\0"
996 /* 9049 */ "frintn.8h\t\0"
997 /* 9060 */ "faddp.8h\t\0"
998 /* 9070 */ "sadalp.8h\t\0"
999 /* 9081 */ "uadalp.8h\t\0"
1000 /* 9092 */ "saddlp.8h\t\0"
1001 /* 9103 */ "uaddlp.8h\t\0"
1002 /* 9114 */ "fminnmp.8h\t\0"
1003 /* 9126 */ "fmaxnmp.8h\t\0"
1004 /* 9138 */ "fminp.8h\t\0"
1005 /* 9148 */ "sminp.8h\t\0"
1006 /* 9158 */ "uminp.8h\t\0"
1007 /* 9168 */ "frintp.8h\t\0"
1008 /* 9179 */ "dup.8h\t\0"
1009 /* 9187 */ "fmaxp.8h\t\0"
1010 /* 9197 */ "smaxp.8h\t\0"
1011 /* 9207 */ "umaxp.8h\t\0"
1012 /* 9217 */ "fcmeq.8h\t\0"
1013 /* 9227 */ "srshr.8h\t\0"
1014 /* 9237 */ "urshr.8h\t\0"
1015 /* 9247 */ "sshr.8h\t\0"
1016 /* 9256 */ "ushr.8h\t\0"
1017 /* 9265 */ "orr.8h\t\0"
1018 /* 9273 */ "fcvtas.8h\t\0"
1019 /* 9284 */ "fabs.8h\t\0"
1020 /* 9293 */ "sqabs.8h\t\0"
1021 /* 9303 */ "cmhs.8h\t\0"
1022 /* 9312 */ "cls.8h\t\0"
1023 /* 9320 */ "fmls.8h\t\0"
1024 /* 9329 */ "fcvtms.8h\t\0"
1025 /* 9340 */ "fcvtns.8h\t\0"
1026 /* 9351 */ "frecps.8h\t\0"
1027 /* 9362 */ "fcvtps.8h\t\0"
1028 /* 9373 */ "frsqrts.8h\t\0"
1029 /* 9385 */ "fcvtzs.8h\t\0"
1030 /* 9396 */ "facgt.8h\t\0"
1031 /* 9406 */ "fcmgt.8h\t\0"
1032 /* 9416 */ "fcmlt.8h\t\0"
1033 /* 9426 */ "fsqrt.8h\t\0"
1034 /* 9436 */ "cmtst.8h\t\0"
1035 /* 9446 */ "fcvtau.8h\t\0"
1036 /* 9457 */ "sqshlu.8h\t\0"
1037 /* 9468 */ "fcvtmu.8h\t\0"
1038 /* 9479 */ "fcvtnu.8h\t\0"
1039 /* 9490 */ "fcvtpu.8h\t\0"
1040 /* 9501 */ "fcvtzu.8h\t\0"
1041 /* 9512 */ "addv.8h\t\0"
1042 /* 9521 */ "fdiv.8h\t\0"
1043 /* 9530 */ "saddlv.8h\t\0"
1044 /* 9541 */ "uaddlv.8h\t\0"
1045 /* 9552 */ "fminnmv.8h\t\0"
1046 /* 9564 */ "fmaxnmv.8h\t\0"
1047 /* 9576 */ "fminv.8h\t\0"
1048 /* 9586 */ "sminv.8h\t\0"
1049 /* 9596 */ "uminv.8h\t\0"
1050 /* 9606 */ "fmov.8h\t\0"
1051 /* 9615 */ "fmaxv.8h\t\0"
1052 /* 9625 */ "smaxv.8h\t\0"
1053 /* 9635 */ "umaxv.8h\t\0"
1054 /* 9645 */ "ssubw.8h\t\0"
1055 /* 9655 */ "usubw.8h\t\0"
1056 /* 9665 */ "saddw.8h\t\0"
1057 /* 9675 */ "uaddw.8h\t\0"
1058 /* 9685 */ "fmax.8h\t\0"
1059 /* 9694 */ "smax.8h\t\0"
1060 /* 9703 */ "umax.8h\t\0"
1061 /* 9712 */ "fmulx.8h\t\0"
1062 /* 9722 */ "frintx.8h\t\0"
1063 /* 9733 */ "clz.8h\t\0"
1064 /* 9741 */ "frintz.8h\t\0"
1065 /* 9752 */ "ldaddah\t\0"
1066 /* 9761 */ "sqrdcmlah\t\0"
1067 /* 9772 */ "sqrdmlah\t\0"
1068 /* 9782 */ "ldsminah\t\0"
1069 /* 9792 */ "lduminah\t\0"
1070 /* 9802 */ "swpah\t\0"
1071 /* 9809 */ "ldclrah\t\0"
1072 /* 9818 */ "ldeorah\t\0"
1073 /* 9827 */ "casah\t\0"
1074 /* 9834 */ "ldsetah\t\0"
1075 /* 9843 */ "ldsmaxah\t\0"
1076 /* 9853 */ "ldumaxah\t\0"
1077 /* 9863 */ "crc32ch\t\0"
1078 /* 9872 */ "sqdech\t\0"
1079 /* 9880 */ "uqdech\t\0"
1080 /* 9888 */ "sqinch\t\0"
1081 /* 9896 */ "uqinch\t\0"
1082 /* 9904 */ "nmatch\t\0"
1083 /* 9912 */ "ldaddh\t\0"
1084 /* 9920 */ "prfh\t\0"
1085 /* 9926 */ "ldaddalh\t\0"
1086 /* 9936 */ "ldsminalh\t\0"
1087 /* 9947 */ "lduminalh\t\0"
1088 /* 9958 */ "swpalh\t\0"
1089 /* 9966 */ "ldclralh\t\0"
1090 /* 9976 */ "ldeoralh\t\0"
1091 /* 9986 */ "casalh\t\0"
1092 /* 9994 */ "ldsetalh\t\0"
1093 /* 10004 */ "ldsmaxalh\t\0"
1094 /* 10015 */ "ldumaxalh\t\0"
1095 /* 10026 */ "ldaddlh\t\0"
1096 /* 10035 */ "ldsminlh\t\0"
1097 /* 10045 */ "lduminlh\t\0"
1098 /* 10055 */ "swplh\t\0"
1099 /* 10062 */ "ldclrlh\t\0"
1100 /* 10071 */ "ldeorlh\t\0"
1101 /* 10080 */ "caslh\t\0"
1102 /* 10087 */ "ldsetlh\t\0"
1103 /* 10096 */ "sqdmulh\t\0"
1104 /* 10105 */ "sqrdmulh\t\0"
1105 /* 10115 */ "smulh\t\0"
1106 /* 10122 */ "umulh\t\0"
1107 /* 10129 */ "ldsmaxlh\t\0"
1108 /* 10139 */ "ldumaxlh\t\0"
1109 /* 10149 */ "ldsminh\t\0"
1110 /* 10158 */ "lduminh\t\0"
1111 /* 10167 */ "ld1roh\t\0"
1112 /* 10175 */ "swph\t\0"
1113 /* 10181 */ "ld1rqh\t\0"
1114 /* 10189 */ "ld1rh\t\0"
1115 /* 10196 */ "ldarh\t\0"
1116 /* 10203 */ "ldlarh\t\0"
1117 /* 10211 */ "ldrh\t\0"
1118 /* 10217 */ "ldclrh\t\0"
1119 /* 10225 */ "stllrh\t\0"
1120 /* 10233 */ "stlrh\t\0"
1121 /* 10240 */ "ldeorh\t\0"
1122 /* 10248 */ "ldaprh\t\0"
1123 /* 10256 */ "ldtrh\t\0"
1124 /* 10263 */ "strh\t\0"
1125 /* 10269 */ "sttrh\t\0"
1126 /* 10276 */ "ldurh\t\0"
1127 /* 10283 */ "stlurh\t\0"
1128 /* 10291 */ "ldapurh\t\0"
1129 /* 10300 */ "sturh\t\0"
1130 /* 10307 */ "ldaxrh\t\0"
1131 /* 10315 */ "ldxrh\t\0"
1132 /* 10322 */ "stlxrh\t\0"
1133 /* 10330 */ "stxrh\t\0"
1134 /* 10337 */ "ld1sh\t\0"
1135 /* 10344 */ "ldff1sh\t\0"
1136 /* 10353 */ "ldnf1sh\t\0"
1137 /* 10362 */ "ldnt1sh\t\0"
1138 /* 10371 */ "cash\t\0"
1139 /* 10377 */ "sqrdmlsh\t\0"
1140 /* 10387 */ "ld1rsh\t\0"
1141 /* 10395 */ "ldrsh\t\0"
1142 /* 10402 */ "ldtrsh\t\0"
1143 /* 10410 */ "ldursh\t\0"
1144 /* 10418 */ "ldapursh\t\0"
1145 /* 10428 */ "ldseth\t\0"
1146 /* 10436 */ "cnth\t\0"
1147 /* 10442 */ "sxth\t\0"
1148 /* 10448 */ "uxth\t\0"
1149 /* 10454 */ "revh\t\0"
1150 /* 10460 */ "ldsmaxh\t\0"
1151 /* 10469 */ "ldumaxh\t\0"
1152 /* 10478 */ "xpaci\t\0"
1153 /* 10485 */ "whilehi\t\0"
1154 /* 10494 */ "punpkhi\t\0"
1155 /* 10503 */ "sunpkhi\t\0"
1156 /* 10512 */ "uunpkhi\t\0"
1157 /* 10521 */ "cmhi\t\0"
1158 /* 10527 */ "cmphi\t\0"
1159 /* 10534 */ "sli\t\0"
1160 /* 10539 */ "gmi\t\0"
1161 /* 10544 */ "sri\t\0"
1162 /* 10549 */ "frinti\t\0"
1163 /* 10557 */ "movi\t\0"
1164 /* 10563 */ "brk\t\0"
1165 /* 10568 */ "movk\t\0"
1166 /* 10574 */ "ldaddal\t\0"
1167 /* 10583 */ "sqdmlal\t\0"
1168 /* 10592 */ "fmlal\t\0"
1169 /* 10599 */ "ldsminal\t\0"
1170 /* 10609 */ "lduminal\t\0"
1171 /* 10619 */ "caspal\t\0"
1172 /* 10627 */ "swpal\t\0"
1173 /* 10634 */ "ldclral\t\0"
1174 /* 10643 */ "ldeoral\t\0"
1175 /* 10652 */ "casal\t\0"
1176 /* 10659 */ "ldsetal\t\0"
1177 /* 10668 */ "ldsmaxal\t\0"
1178 /* 10678 */ "ldumaxal\t\0"
1179 /* 10688 */ "tbl\t\0"
1180 /* 10693 */ "smsubl\t\0"
1181 /* 10701 */ "umsubl\t\0"
1182 /* 10709 */ "ldaddl\t\0"
1183 /* 10717 */ "smaddl\t\0"
1184 /* 10725 */ "umaddl\t\0"
1185 /* 10733 */ "tcancel\t\0"
1186 /* 10742 */ "fcsel\t\0"
1187 /* 10749 */ "ftssel\t\0"
1188 /* 10757 */ "sqshl\t\0"
1189 /* 10764 */ "uqshl\t\0"
1190 /* 10771 */ "sqrshl\t\0"
1191 /* 10779 */ "uqrshl\t\0"
1192 /* 10787 */ "srshl\t\0"
1193 /* 10794 */ "urshl\t\0"
1194 /* 10801 */ "sshl\t\0"
1195 /* 10807 */ "ushl\t\0"
1196 /* 10813 */ "sqdmull\t\0"
1197 /* 10822 */ "ldsminl\t\0"
1198 /* 10831 */ "lduminl\t\0"
1199 /* 10840 */ "addpl\t\0"
1200 /* 10847 */ "caspl\t\0"
1201 /* 10854 */ "swpl\t\0"
1202 /* 10860 */ "ldclrl\t\0"
1203 /* 10868 */ "ldeorl\t\0"
1204 /* 10876 */ "casl\t\0"
1205 /* 10882 */ "nbsl\t\0"
1206 /* 10888 */ "sqdmlsl\t\0"
1207 /* 10897 */ "fmlsl\t\0"
1208 /* 10904 */ "sysl\t\0"
1209 /* 10910 */ "ldsetl\t\0"
1210 /* 10918 */ "fcvtl\t\0"
1211 /* 10925 */ "fmul\t\0"
1212 /* 10931 */ "fnmul\t\0"
1213 /* 10938 */ "pmul\t\0"
1214 /* 10944 */ "ftsmul\t\0"
1215 /* 10952 */ "addvl\t\0"
1216 /* 10959 */ "rdvl\t\0"
1217 /* 10965 */ "ldsmaxl\t\0"
1218 /* 10974 */ "ldumaxl\t\0"
1219 /* 10983 */ "sbfm\t\0"
1220 /* 10989 */ "ubfm\t\0"
1221 /* 10995 */ "prfm\t\0"
1222 /* 11001 */ "ldgm\t\0"
1223 /* 11007 */ "stgm\t\0"
1224 /* 11013 */ "stzgm\t\0"
1225 /* 11020 */ "fminnm\t\0"
1226 /* 11028 */ "fmaxnm\t\0"
1227 /* 11036 */ "dupm\t\0"
1228 /* 11042 */ "frintm\t\0"
1229 /* 11050 */ "prfum\t\0"
1230 /* 11057 */ "bsl1n\t\0"
1231 /* 11064 */ "bsl2n\t\0"
1232 /* 11071 */ "fmin\t\0"
1233 /* 11077 */ "ldsmin\t\0"
1234 /* 11085 */ "ldumin\t\0"
1235 /* 11093 */ "brkn\t\0"
1236 /* 11099 */ "ccmn\t\0"
1237 /* 11105 */ "eon\t\0"
1238 /* 11110 */ "sqshrn\t\0"
1239 /* 11118 */ "uqshrn\t\0"
1240 /* 11126 */ "sqrshrn\t\0"
1241 /* 11135 */ "uqrshrn\t\0"
1242 /* 11144 */ "orn\t\0"
1243 /* 11149 */ "frintn\t\0"
1244 /* 11157 */ "fcvtn\t\0"
1245 /* 11164 */ "sqxtn\t\0"
1246 /* 11171 */ "uqxtn\t\0"
1247 /* 11178 */ "sqshrun\t\0"
1248 /* 11187 */ "sqrshrun\t\0"
1249 /* 11197 */ "sqxtun\t\0"
1250 /* 11205 */ "movn\t\0"
1251 /* 11211 */ "fcvtxn\t\0"
1252 /* 11219 */ "whilelo\t\0"
1253 /* 11228 */ "punpklo\t\0"
1254 /* 11237 */ "sunpklo\t\0"
1255 /* 11246 */ "uunpklo\t\0"
1256 /* 11255 */ "cmplo\t\0"
1257 /* 11262 */ "fcmuo\t\0"
1258 /* 11269 */ "subp\t\0"
1259 /* 11275 */ "sqdecp\t\0"
1260 /* 11283 */ "uqdecp\t\0"
1261 /* 11291 */ "sqincp\t\0"
1262 /* 11299 */ "uqincp\t\0"
1263 /* 11307 */ "faddp\t\0"
1264 /* 11314 */ "ldp\t\0"
1265 /* 11319 */ "bdep\t\0"
1266 /* 11325 */ "stgp\t\0"
1267 /* 11331 */ "sadalp\t\0"
1268 /* 11339 */ "uadalp\t\0"
1269 /* 11347 */ "fccmp\t\0"
1270 /* 11354 */ "fcmp\t\0"
1271 /* 11360 */ "fminnmp\t\0"
1272 /* 11369 */ "fmaxnmp\t\0"
1273 /* 11378 */ "ldnp\t\0"
1274 /* 11384 */ "fminp\t\0"
1275 /* 11391 */ "sminp\t\0"
1276 /* 11398 */ "uminp\t\0"
1277 /* 11405 */ "stnp\t\0"
1278 /* 11411 */ "adrp\t\0"
1279 /* 11417 */ "bgrp\t\0"
1280 /* 11423 */ "casp\t\0"
1281 /* 11429 */ "cntp\t\0"
1282 /* 11435 */ "frintp\t\0"
1283 /* 11443 */ "stp\t\0"
1284 /* 11448 */ "fdup\t\0"
1285 /* 11454 */ "swp\t\0"
1286 /* 11459 */ "ldaxp\t\0"
1287 /* 11466 */ "fmaxp\t\0"
1288 /* 11473 */ "smaxp\t\0"
1289 /* 11480 */ "umaxp\t\0"
1290 /* 11487 */ "ldxp\t\0"
1291 /* 11493 */ "stlxp\t\0"
1292 /* 11500 */ "stxp\t\0"
1293 /* 11506 */ "pmull2.1q\t\0"
1294 /* 11517 */ "pmull.1q\t\0"
1295 /* 11527 */ "fcmeq\t\0"
1296 /* 11534 */ "ctermeq\t\0"
1297 /* 11543 */ "cmpeq\t\0"
1298 /* 11550 */ "ld1r\t\0"
1299 /* 11556 */ "ld2r\t\0"
1300 /* 11562 */ "ld3r\t\0"
1301 /* 11568 */ "ld4r\t\0"
1302 /* 11574 */ "ldar\t\0"
1303 /* 11580 */ "ldlar\t\0"
1304 /* 11587 */ "xar\t\0"
1305 /* 11592 */ "fsubr\t\0"
1306 /* 11599 */ "shsubr\t\0"
1307 /* 11607 */ "uhsubr\t\0"
1308 /* 11615 */ "sqsubr\t\0"
1309 /* 11623 */ "uqsubr\t\0"
1310 /* 11631 */ "adr\t\0"
1311 /* 11636 */ "ldr\t\0"
1312 /* 11641 */ "rdffr\t\0"
1313 /* 11648 */ "wrffr\t\0"
1314 /* 11655 */ "srshr\t\0"
1315 /* 11662 */ "urshr\t\0"
1316 /* 11669 */ "sshr\t\0"
1317 /* 11675 */ "ushr\t\0"
1318 /* 11681 */ "blr\t\0"
1319 /* 11686 */ "ldclr\t\0"
1320 /* 11693 */ "sqshlr\t\0"
1321 /* 11701 */ "uqshlr\t\0"
1322 /* 11709 */ "sqrshlr\t\0"
1323 /* 11718 */ "uqrshlr\t\0"
1324 /* 11727 */ "srshlr\t\0"
1325 /* 11735 */ "urshlr\t\0"
1326 /* 11743 */ "stllr\t\0"
1327 /* 11750 */ "lslr\t\0"
1328 /* 11756 */ "stlr\t\0"
1329 /* 11762 */ "ldeor\t\0"
1330 /* 11769 */ "nor\t\0"
1331 /* 11774 */ "ror\t\0"
1332 /* 11779 */ "ldapr\t\0"
1333 /* 11786 */ "orr\t\0"
1334 /* 11791 */ "asrr\t\0"
1335 /* 11797 */ "lsrr\t\0"
1336 /* 11803 */ "asr\t\0"
1337 /* 11808 */ "lsr\t\0"
1338 /* 11813 */ "msr\t\0"
1339 /* 11818 */ "insr\t\0"
1340 /* 11824 */ "ldtr\t\0"
1341 /* 11830 */ "str\t\0"
1342 /* 11835 */ "sttr\t\0"
1343 /* 11841 */ "extr\t\0"
1344 /* 11847 */ "ldur\t\0"
1345 /* 11853 */ "stlur\t\0"
1346 /* 11860 */ "ldapur\t\0"
1347 /* 11868 */ "stur\t\0"
1348 /* 11874 */ "fdivr\t\0"
1349 /* 11881 */ "sdivr\t\0"
1350 /* 11888 */ "udivr\t\0"
1351 /* 11895 */ "whilewr\t\0"
1352 /* 11904 */ "ldaxr\t\0"
1353 /* 11911 */ "ldxr\t\0"
1354 /* 11917 */ "stlxr\t\0"
1355 /* 11924 */ "stxr\t\0"
1356 /* 11930 */ "fmla.s\t\0"
1357 /* 11938 */ "sqrdmlah.s\t\0"
1358 /* 11950 */ "sqdmulh.s\t\0"
1359 /* 11961 */ "sqrdmulh.s\t\0"
1360 /* 11973 */ "sqrdmlsh.s\t\0"
1361 /* 11985 */ "sqdmlal.s\t\0"
1362 /* 11996 */ "sqdmull.s\t\0"
1363 /* 12007 */ "sqdmlsl.s\t\0"
1364 /* 12018 */ "fmul.s\t\0"
1365 /* 12026 */ "fmls.s\t\0"
1366 /* 12034 */ "ins.s\t\0"
1367 /* 12041 */ "smov.s\t\0"
1368 /* 12049 */ "umov.s\t\0"
1369 /* 12057 */ "fmulx.s\t\0"
1370 /* 12066 */ "trn1.2s\t\0"
1371 /* 12075 */ "zip1.2s\t\0"
1372 /* 12084 */ "uzp1.2s\t\0"
1373 /* 12093 */ "trn2.2s\t\0"
1374 /* 12102 */ "zip2.2s\t\0"
1375 /* 12111 */ "uzp2.2s\t\0"
1376 /* 12120 */ "rev64.2s\t\0"
1377 /* 12130 */ "saba.2s\t\0"
1378 /* 12139 */ "uaba.2s\t\0"
1379 /* 12148 */ "fcmla.2s\t\0"
1380 /* 12158 */ "fmla.2s\t\0"
1381 /* 12167 */ "srsra.2s\t\0"
1382 /* 12177 */ "ursra.2s\t\0"
1383 /* 12187 */ "ssra.2s\t\0"
1384 /* 12196 */ "usra.2s\t\0"
1385 /* 12205 */ "frinta.2s\t\0"
1386 /* 12216 */ "fsub.2s\t\0"
1387 /* 12225 */ "shsub.2s\t\0"
1388 /* 12235 */ "uhsub.2s\t\0"
1389 /* 12245 */ "sqsub.2s\t\0"
1390 /* 12255 */ "uqsub.2s\t\0"
1391 /* 12265 */ "bic.2s\t\0"
1392 /* 12273 */ "fabd.2s\t\0"
1393 /* 12282 */ "sabd.2s\t\0"
1394 /* 12291 */ "uabd.2s\t\0"
1395 /* 12300 */ "fcadd.2s\t\0"
1396 /* 12310 */ "fadd.2s\t\0"
1397 /* 12319 */ "srhadd.2s\t\0"
1398 /* 12330 */ "urhadd.2s\t\0"
1399 /* 12341 */ "shadd.2s\t\0"
1400 /* 12351 */ "uhadd.2s\t\0"
1401 /* 12361 */ "usqadd.2s\t\0"
1402 /* 12372 */ "suqadd.2s\t\0"
1403 /* 12383 */ "facge.2s\t\0"
1404 /* 12393 */ "fcmge.2s\t\0"
1405 /* 12403 */ "fcmle.2s\t\0"
1406 /* 12413 */ "frecpe.2s\t\0"
1407 /* 12424 */ "urecpe.2s\t\0"
1408 /* 12435 */ "frsqrte.2s\t\0"
1409 /* 12447 */ "ursqrte.2s\t\0"
1410 /* 12459 */ "scvtf.2s\t\0"
1411 /* 12469 */ "ucvtf.2s\t\0"
1412 /* 12479 */ "fneg.2s\t\0"
1413 /* 12488 */ "sqneg.2s\t\0"
1414 /* 12498 */ "sqrdmlah.2s\t\0"
1415 /* 12511 */ "sqdmulh.2s\t\0"
1416 /* 12523 */ "sqrdmulh.2s\t\0"
1417 /* 12536 */ "sqrdmlsh.2s\t\0"
1418 /* 12549 */ "cmhi.2s\t\0"
1419 /* 12558 */ "sli.2s\t\0"
1420 /* 12566 */ "mvni.2s\t\0"
1421 /* 12575 */ "sri.2s\t\0"
1422 /* 12583 */ "frinti.2s\t\0"
1423 /* 12594 */ "movi.2s\t\0"
1424 /* 12603 */ "sqshl.2s\t\0"
1425 /* 12613 */ "uqshl.2s\t\0"
1426 /* 12623 */ "sqrshl.2s\t\0"
1427 /* 12634 */ "uqrshl.2s\t\0"
1428 /* 12645 */ "srshl.2s\t\0"
1429 /* 12655 */ "urshl.2s\t\0"
1430 /* 12665 */ "sshl.2s\t\0"
1431 /* 12674 */ "ushl.2s\t\0"
1432 /* 12683 */ "fmul.2s\t\0"
1433 /* 12692 */ "fminnm.2s\t\0"
1434 /* 12703 */ "fmaxnm.2s\t\0"
1435 /* 12714 */ "frintm.2s\t\0"
1436 /* 12725 */ "rsubhn.2s\t\0"
1437 /* 12736 */ "raddhn.2s\t\0"
1438 /* 12747 */ "fmin.2s\t\0"
1439 /* 12756 */ "smin.2s\t\0"
1440 /* 12765 */ "umin.2s\t\0"
1441 /* 12774 */ "sqshrn.2s\t\0"
1442 /* 12785 */ "uqshrn.2s\t\0"
1443 /* 12796 */ "sqrshrn.2s\t\0"
1444 /* 12808 */ "uqrshrn.2s\t\0"
1445 /* 12820 */ "frintn.2s\t\0"
1446 /* 12831 */ "sqxtn.2s\t\0"
1447 /* 12841 */ "uqxtn.2s\t\0"
1448 /* 12851 */ "sqshrun.2s\t\0"
1449 /* 12863 */ "sqrshrun.2s\t\0"
1450 /* 12876 */ "sqxtun.2s\t\0"
1451 /* 12887 */ "faddp.2s\t\0"
1452 /* 12897 */ "sadalp.2s\t\0"
1453 /* 12908 */ "uadalp.2s\t\0"
1454 /* 12919 */ "saddlp.2s\t\0"
1455 /* 12930 */ "uaddlp.2s\t\0"
1456 /* 12941 */ "fminnmp.2s\t\0"
1457 /* 12953 */ "fmaxnmp.2s\t\0"
1458 /* 12965 */ "fminp.2s\t\0"
1459 /* 12975 */ "sminp.2s\t\0"
1460 /* 12985 */ "uminp.2s\t\0"
1461 /* 12995 */ "frintp.2s\t\0"
1462 /* 13006 */ "dup.2s\t\0"
1463 /* 13014 */ "fmaxp.2s\t\0"
1464 /* 13024 */ "smaxp.2s\t\0"
1465 /* 13034 */ "umaxp.2s\t\0"
1466 /* 13044 */ "fcmeq.2s\t\0"
1467 /* 13054 */ "srshr.2s\t\0"
1468 /* 13064 */ "urshr.2s\t\0"
1469 /* 13074 */ "sshr.2s\t\0"
1470 /* 13083 */ "ushr.2s\t\0"
1471 /* 13092 */ "orr.2s\t\0"
1472 /* 13100 */ "fcvtas.2s\t\0"
1473 /* 13111 */ "fabs.2s\t\0"
1474 /* 13120 */ "sqabs.2s\t\0"
1475 /* 13130 */ "cmhs.2s\t\0"
1476 /* 13139 */ "cls.2s\t\0"
1477 /* 13147 */ "fmls.2s\t\0"
1478 /* 13156 */ "fcvtms.2s\t\0"
1479 /* 13167 */ "fcvtns.2s\t\0"
1480 /* 13178 */ "frecps.2s\t\0"
1481 /* 13189 */ "fcvtps.2s\t\0"
1482 /* 13200 */ "frsqrts.2s\t\0"
1483 /* 13212 */ "fcvtzs.2s\t\0"
1484 /* 13223 */ "facgt.2s\t\0"
1485 /* 13233 */ "fcmgt.2s\t\0"
1486 /* 13243 */ "fcmlt.2s\t\0"
1487 /* 13253 */ "fsqrt.2s\t\0"
1488 /* 13263 */ "cmtst.2s\t\0"
1489 /* 13273 */ "fcvtau.2s\t\0"
1490 /* 13284 */ "sqshlu.2s\t\0"
1491 /* 13295 */ "fcvtmu.2s\t\0"
1492 /* 13306 */ "fcvtnu.2s\t\0"
1493 /* 13317 */ "fcvtpu.2s\t\0"
1494 /* 13328 */ "fcvtzu.2s\t\0"
1495 /* 13339 */ "fdiv.2s\t\0"
1496 /* 13348 */ "fmov.2s\t\0"
1497 /* 13357 */ "frint32x.2s\t\0"
1498 /* 13370 */ "frint64x.2s\t\0"
1499 /* 13383 */ "fmax.2s\t\0"
1500 /* 13392 */ "smax.2s\t\0"
1501 /* 13401 */ "umax.2s\t\0"
1502 /* 13410 */ "fmulx.2s\t\0"
1503 /* 13420 */ "frintx.2s\t\0"
1504 /* 13431 */ "frint32z.2s\t\0"
1505 /* 13444 */ "frint64z.2s\t\0"
1506 /* 13457 */ "clz.2s\t\0"
1507 /* 13465 */ "frintz.2s\t\0"
1508 /* 13476 */ "sha1su0.4s\t\0"
1509 /* 13488 */ "sha256su0.4s\t\0"
1510 /* 13502 */ "trn1.4s\t\0"
1511 /* 13511 */ "zip1.4s\t\0"
1512 /* 13520 */ "uzp1.4s\t\0"
1513 /* 13529 */ "sm3ss1.4s\t\0"
1514 /* 13540 */ "sha1su1.4s\t\0"
1515 /* 13552 */ "sha256su1.4s\t\0"
1516 /* 13566 */ "sm3partw1.4s\t\0"
1517 /* 13580 */ "sha256h2.4s\t\0"
1518 /* 13593 */ "sabal2.4s\t\0"
1519 /* 13604 */ "uabal2.4s\t\0"
1520 /* 13615 */ "sqdmlal2.4s\t\0"
1521 /* 13628 */ "smlal2.4s\t\0"
1522 /* 13639 */ "umlal2.4s\t\0"
1523 /* 13650 */ "ssubl2.4s\t\0"
1524 /* 13661 */ "usubl2.4s\t\0"
1525 /* 13672 */ "sabdl2.4s\t\0"
1526 /* 13683 */ "uabdl2.4s\t\0"
1527 /* 13694 */ "saddl2.4s\t\0"
1528 /* 13705 */ "uaddl2.4s\t\0"
1529 /* 13716 */ "sshll2.4s\t\0"
1530 /* 13727 */ "ushll2.4s\t\0"
1531 /* 13738 */ "sqdmull2.4s\t\0"
1532 /* 13751 */ "smull2.4s\t\0"
1533 /* 13762 */ "umull2.4s\t\0"
1534 /* 13773 */ "sqdmlsl2.4s\t\0"
1535 /* 13786 */ "smlsl2.4s\t\0"
1536 /* 13797 */ "umlsl2.4s\t\0"
1537 /* 13808 */ "rsubhn2.4s\t\0"
1538 /* 13820 */ "raddhn2.4s\t\0"
1539 /* 13832 */ "sqshrn2.4s\t\0"
1540 /* 13844 */ "uqshrn2.4s\t\0"
1541 /* 13856 */ "sqrshrn2.4s\t\0"
1542 /* 13869 */ "uqrshrn2.4s\t\0"
1543 /* 13882 */ "trn2.4s\t\0"
1544 /* 13891 */ "sqxtn2.4s\t\0"
1545 /* 13902 */ "uqxtn2.4s\t\0"
1546 /* 13913 */ "sqshrun2.4s\t\0"
1547 /* 13926 */ "sqrshrun2.4s\t\0"
1548 /* 13940 */ "sqxtun2.4s\t\0"
1549 /* 13952 */ "zip2.4s\t\0"
1550 /* 13961 */ "uzp2.4s\t\0"
1551 /* 13970 */ "ssubw2.4s\t\0"
1552 /* 13981 */ "usubw2.4s\t\0"
1553 /* 13992 */ "saddw2.4s\t\0"
1554 /* 14003 */ "uaddw2.4s\t\0"
1555 /* 14014 */ "sm3partw2.4s\t\0"
1556 /* 14028 */ "rev64.4s\t\0"
1557 /* 14038 */ "sm3tt1a.4s\t\0"
1558 /* 14050 */ "sm3tt2a.4s\t\0"
1559 /* 14062 */ "saba.4s\t\0"
1560 /* 14071 */ "uaba.4s\t\0"
1561 /* 14080 */ "fcmla.4s\t\0"
1562 /* 14090 */ "fmla.4s\t\0"
1563 /* 14099 */ "srsra.4s\t\0"
1564 /* 14109 */ "ursra.4s\t\0"
1565 /* 14119 */ "ssra.4s\t\0"
1566 /* 14128 */ "usra.4s\t\0"
1567 /* 14137 */ "frinta.4s\t\0"
1568 /* 14148 */ "sm3tt1b.4s\t\0"
1569 /* 14160 */ "sm3tt2b.4s\t\0"
1570 /* 14172 */ "fsub.4s\t\0"
1571 /* 14181 */ "shsub.4s\t\0"
1572 /* 14191 */ "uhsub.4s\t\0"
1573 /* 14201 */ "sqsub.4s\t\0"
1574 /* 14211 */ "uqsub.4s\t\0"
1575 /* 14221 */ "sha1c.4s\t\0"
1576 /* 14231 */ "bic.4s\t\0"
1577 /* 14239 */ "fabd.4s\t\0"
1578 /* 14248 */ "sabd.4s\t\0"
1579 /* 14257 */ "uabd.4s\t\0"
1580 /* 14266 */ "fcadd.4s\t\0"
1581 /* 14276 */ "fadd.4s\t\0"
1582 /* 14285 */ "srhadd.4s\t\0"
1583 /* 14296 */ "urhadd.4s\t\0"
1584 /* 14307 */ "shadd.4s\t\0"
1585 /* 14317 */ "uhadd.4s\t\0"
1586 /* 14327 */ "usqadd.4s\t\0"
1587 /* 14338 */ "suqadd.4s\t\0"
1588 /* 14349 */ "sm4e.4s\t\0"
1589 /* 14358 */ "facge.4s\t\0"
1590 /* 14368 */ "fcmge.4s\t\0"
1591 /* 14378 */ "fcmle.4s\t\0"
1592 /* 14388 */ "frecpe.4s\t\0"
1593 /* 14399 */ "urecpe.4s\t\0"
1594 /* 14410 */ "frsqrte.4s\t\0"
1595 /* 14422 */ "ursqrte.4s\t\0"
1596 /* 14434 */ "scvtf.4s\t\0"
1597 /* 14444 */ "ucvtf.4s\t\0"
1598 /* 14454 */ "fneg.4s\t\0"
1599 /* 14463 */ "sqneg.4s\t\0"
1600 /* 14473 */ "sha256h.4s\t\0"
1601 /* 14485 */ "sqrdmlah.4s\t\0"
1602 /* 14498 */ "sqdmulh.4s\t\0"
1603 /* 14510 */ "sqrdmulh.4s\t\0"
1604 /* 14523 */ "sqrdmlsh.4s\t\0"
1605 /* 14536 */ "cmhi.4s\t\0"
1606 /* 14545 */ "sli.4s\t\0"
1607 /* 14553 */ "mvni.4s\t\0"
1608 /* 14562 */ "sri.4s\t\0"
1609 /* 14570 */ "frinti.4s\t\0"
1610 /* 14581 */ "movi.4s\t\0"
1611 /* 14590 */ "sabal.4s\t\0"
1612 /* 14600 */ "uabal.4s\t\0"
1613 /* 14610 */ "sqdmlal.4s\t\0"
1614 /* 14622 */ "smlal.4s\t\0"
1615 /* 14632 */ "umlal.4s\t\0"
1616 /* 14642 */ "ssubl.4s\t\0"
1617 /* 14652 */ "usubl.4s\t\0"
1618 /* 14662 */ "sabdl.4s\t\0"
1619 /* 14672 */ "uabdl.4s\t\0"
1620 /* 14682 */ "saddl.4s\t\0"
1621 /* 14692 */ "uaddl.4s\t\0"
1622 /* 14702 */ "sqshl.4s\t\0"
1623 /* 14712 */ "uqshl.4s\t\0"
1624 /* 14722 */ "sqrshl.4s\t\0"
1625 /* 14733 */ "uqrshl.4s\t\0"
1626 /* 14744 */ "srshl.4s\t\0"
1627 /* 14754 */ "urshl.4s\t\0"
1628 /* 14764 */ "sshl.4s\t\0"
1629 /* 14773 */ "ushl.4s\t\0"
1630 /* 14782 */ "sshll.4s\t\0"
1631 /* 14792 */ "ushll.4s\t\0"
1632 /* 14802 */ "sqdmull.4s\t\0"
1633 /* 14814 */ "smull.4s\t\0"
1634 /* 14824 */ "umull.4s\t\0"
1635 /* 14834 */ "sqdmlsl.4s\t\0"
1636 /* 14846 */ "smlsl.4s\t\0"
1637 /* 14856 */ "umlsl.4s\t\0"
1638 /* 14866 */ "fmul.4s\t\0"
1639 /* 14875 */ "sha1m.4s\t\0"
1640 /* 14885 */ "fminnm.4s\t\0"
1641 /* 14896 */ "fmaxnm.4s\t\0"
1642 /* 14907 */ "frintm.4s\t\0"
1643 /* 14918 */ "fmin.4s\t\0"
1644 /* 14927 */ "smin.4s\t\0"
1645 /* 14936 */ "umin.4s\t\0"
1646 /* 14945 */ "frintn.4s\t\0"
1647 /* 14956 */ "sha1p.4s\t\0"
1648 /* 14966 */ "faddp.4s\t\0"
1649 /* 14976 */ "sadalp.4s\t\0"
1650 /* 14987 */ "uadalp.4s\t\0"
1651 /* 14998 */ "saddlp.4s\t\0"
1652 /* 15009 */ "uaddlp.4s\t\0"
1653 /* 15020 */ "fminnmp.4s\t\0"
1654 /* 15032 */ "fmaxnmp.4s\t\0"
1655 /* 15044 */ "fminp.4s\t\0"
1656 /* 15054 */ "sminp.4s\t\0"
1657 /* 15064 */ "uminp.4s\t\0"
1658 /* 15074 */ "frintp.4s\t\0"
1659 /* 15085 */ "dup.4s\t\0"
1660 /* 15093 */ "fmaxp.4s\t\0"
1661 /* 15103 */ "smaxp.4s\t\0"
1662 /* 15113 */ "umaxp.4s\t\0"
1663 /* 15123 */ "fcmeq.4s\t\0"
1664 /* 15133 */ "srshr.4s\t\0"
1665 /* 15143 */ "urshr.4s\t\0"
1666 /* 15153 */ "sshr.4s\t\0"
1667 /* 15162 */ "ushr.4s\t\0"
1668 /* 15171 */ "orr.4s\t\0"
1669 /* 15179 */ "fcvtas.4s\t\0"
1670 /* 15190 */ "fabs.4s\t\0"
1671 /* 15199 */ "sqabs.4s\t\0"
1672 /* 15209 */ "cmhs.4s\t\0"
1673 /* 15218 */ "cls.4s\t\0"
1674 /* 15226 */ "fmls.4s\t\0"
1675 /* 15235 */ "fcvtms.4s\t\0"
1676 /* 15246 */ "fcvtns.4s\t\0"
1677 /* 15257 */ "frecps.4s\t\0"
1678 /* 15268 */ "fcvtps.4s\t\0"
1679 /* 15279 */ "frsqrts.4s\t\0"
1680 /* 15291 */ "fcvtzs.4s\t\0"
1681 /* 15302 */ "facgt.4s\t\0"
1682 /* 15312 */ "fcmgt.4s\t\0"
1683 /* 15322 */ "fcmlt.4s\t\0"
1684 /* 15332 */ "fsqrt.4s\t\0"
1685 /* 15342 */ "cmtst.4s\t\0"
1686 /* 15352 */ "fcvtau.4s\t\0"
1687 /* 15363 */ "sqshlu.4s\t\0"
1688 /* 15374 */ "fcvtmu.4s\t\0"
1689 /* 15385 */ "fcvtnu.4s\t\0"
1690 /* 15396 */ "fcvtpu.4s\t\0"
1691 /* 15407 */ "fcvtzu.4s\t\0"
1692 /* 15418 */ "addv.4s\t\0"
1693 /* 15427 */ "fdiv.4s\t\0"
1694 /* 15436 */ "saddlv.4s\t\0"
1695 /* 15447 */ "uaddlv.4s\t\0"
1696 /* 15458 */ "fminnmv.4s\t\0"
1697 /* 15470 */ "fmaxnmv.4s\t\0"
1698 /* 15482 */ "fminv.4s\t\0"
1699 /* 15492 */ "sminv.4s\t\0"
1700 /* 15502 */ "uminv.4s\t\0"
1701 /* 15512 */ "fmov.4s\t\0"
1702 /* 15521 */ "fmaxv.4s\t\0"
1703 /* 15531 */ "smaxv.4s\t\0"
1704 /* 15541 */ "umaxv.4s\t\0"
1705 /* 15551 */ "ssubw.4s\t\0"
1706 /* 15561 */ "usubw.4s\t\0"
1707 /* 15571 */ "saddw.4s\t\0"
1708 /* 15581 */ "uaddw.4s\t\0"
1709 /* 15591 */ "frint32x.4s\t\0"
1710 /* 15604 */ "frint64x.4s\t\0"
1711 /* 15617 */ "fmax.4s\t\0"
1712 /* 15626 */ "smax.4s\t\0"
1713 /* 15635 */ "umax.4s\t\0"
1714 /* 15644 */ "fmulx.4s\t\0"
1715 /* 15654 */ "frintx.4s\t\0"
1716 /* 15665 */ "sm4ekey.4s\t\0"
1717 /* 15677 */ "frint32z.4s\t\0"
1718 /* 15690 */ "frint64z.4s\t\0"
1719 /* 15703 */ "clz.4s\t\0"
1720 /* 15711 */ "frintz.4s\t\0"
1721 /* 15722 */ "cas\t\0"
1722 /* 15727 */ "brkas\t\0"
1723 /* 15734 */ "brkpas\t\0"
1724 /* 15742 */ "fcvtas\t\0"
1725 /* 15750 */ "fabs\t\0"
1726 /* 15756 */ "sqabs\t\0"
1727 /* 15763 */ "brkbs\t\0"
1728 /* 15770 */ "brkpbs\t\0"
1729 /* 15778 */ "subs\t\0"
1730 /* 15784 */ "sbcs\t\0"
1731 /* 15790 */ "adcs\t\0"
1732 /* 15796 */ "bics\t\0"
1733 /* 15802 */ "adds\t\0"
1734 /* 15808 */ "nands\t\0"
1735 /* 15815 */ "ptrues\t\0"
1736 /* 15823 */ "whilehs\t\0"
1737 /* 15832 */ "cmhs\t\0"
1738 /* 15838 */ "cmphs\t\0"
1739 /* 15845 */ "cls\t\0"
1740 /* 15850 */ "whilels\t\0"
1741 /* 15859 */ "fmls\t\0"
1742 /* 15865 */ "fnmls\t\0"
1743 /* 15872 */ "cmpls\t\0"
1744 /* 15879 */ "fcvtms\t\0"
1745 /* 15887 */ "brkns\t\0"
1746 /* 15894 */ "orns\t\0"
1747 /* 15900 */ "fcvtns\t\0"
1748 /* 15908 */ "subps\t\0"
1749 /* 15915 */ "frecps\t\0"
1750 /* 15923 */ "fcvtps\t\0"
1751 /* 15931 */ "rdffrs\t\0"
1752 /* 15939 */ "mrs\t\0"
1753 /* 15944 */ "eors\t\0"
1754 /* 15950 */ "nors\t\0"
1755 /* 15956 */ "orrs\t\0"
1756 /* 15962 */ "frsqrts\t\0"
1757 /* 15971 */ "sys\t\0"
1758 /* 15976 */ "fcvtzs\t\0"
1759 /* 15984 */ "fjcvtzs\t\0"
1760 /* 15993 */ "sqdmlalbt\t\0"
1761 /* 16004 */ "ssublbt\t\0"
1762 /* 16013 */ "saddlbt\t\0"
1763 /* 16022 */ "sqdmlslbt\t\0"
1764 /* 16033 */ "eorbt\t\0"
1765 /* 16040 */ "compact\t\0"
1766 /* 16049 */ "wfet\t\0"
1767 /* 16055 */ "ret\t\0"
1768 /* 16060 */ "ldset\t\0"
1769 /* 16067 */ "facgt\t\0"
1770 /* 16074 */ "whilegt\t\0"
1771 /* 16083 */ "fcmgt\t\0"
1772 /* 16090 */ "cmpgt\t\0"
1773 /* 16097 */ "rbit\t\0"
1774 /* 16103 */ "wfit\t\0"
1775 /* 16109 */ "sabalt\t\0"
1776 /* 16117 */ "uabalt\t\0"
1777 /* 16125 */ "sqdmlalt\t\0"
1778 /* 16135 */ "bfmlalt\t\0"
1779 /* 16144 */ "smlalt\t\0"
1780 /* 16152 */ "umlalt\t\0"
1781 /* 16160 */ "ssublt\t\0"
1782 /* 16168 */ "usublt\t\0"
1783 /* 16176 */ "sbclt\t\0"
1784 /* 16183 */ "adclt\t\0"
1785 /* 16190 */ "sabdlt\t\0"
1786 /* 16198 */ "uabdlt\t\0"
1787 /* 16206 */ "saddlt\t\0"
1788 /* 16214 */ "uaddlt\t\0"
1789 /* 16222 */ "whilelt\t\0"
1790 /* 16231 */ "hlt\t\0"
1791 /* 16236 */ "sshllt\t\0"
1792 /* 16244 */ "ushllt\t\0"
1793 /* 16252 */ "sqdmullt\t\0"
1794 /* 16262 */ "pmullt\t\0"
1795 /* 16270 */ "smullt\t\0"
1796 /* 16278 */ "umullt\t\0"
1797 /* 16286 */ "fcmlt\t\0"
1798 /* 16293 */ "cmplt\t\0"
1799 /* 16300 */ "sqdmlslt\t\0"
1800 /* 16310 */ "fmlslt\t\0"
1801 /* 16318 */ "smlslt\t\0"
1802 /* 16326 */ "umlslt\t\0"
1803 /* 16334 */ "fcvtlt\t\0"
1804 /* 16342 */ "histcnt\t\0"
1805 /* 16351 */ "rsubhnt\t\0"
1806 /* 16360 */ "raddhnt\t\0"
1807 /* 16369 */ "hint\t\0"
1808 /* 16375 */ "sqshrnt\t\0"
1809 /* 16384 */ "uqshrnt\t\0"
1810 /* 16393 */ "sqrshrnt\t\0"
1811 /* 16403 */ "uqrshrnt\t\0"
1812 /* 16413 */ "bfcvtnt\t\0"
1813 /* 16422 */ "sqxtnt\t\0"
1814 /* 16430 */ "uqxtnt\t\0"
1815 /* 16438 */ "sqshrunt\t\0"
1816 /* 16448 */ "sqrshrunt\t\0"
1817 /* 16459 */ "sqxtunt\t\0"
1818 /* 16468 */ "fcvtxnt\t\0"
1819 /* 16477 */ "cdot\t\0"
1820 /* 16483 */ "bfdot\t\0"
1821 /* 16490 */ "usdot\t\0"
1822 /* 16497 */ "sudot\t\0"
1823 /* 16504 */ "cnot\t\0"
1824 /* 16510 */ "tstart\t\0"
1825 /* 16518 */ "fsqrt\t\0"
1826 /* 16525 */ "ptest\t\0"
1827 /* 16532 */ "ttest\t\0"
1828 /* 16539 */ "pfirst\t\0"
1829 /* 16547 */ "cmtst\t\0"
1830 /* 16554 */ "bfcvt\t\0"
1831 /* 16561 */ "ssubwt\t\0"
1832 /* 16569 */ "usubwt\t\0"
1833 /* 16577 */ "saddwt\t\0"
1834 /* 16585 */ "uaddwt\t\0"
1835 /* 16593 */ "bext\t\0"
1836 /* 16599 */ "pnext\t\0"
1837 /* 16606 */ "fcvtau\t\0"
1838 /* 16614 */ "sqshlu\t\0"
1839 /* 16622 */ "fcvtmu\t\0"
1840 /* 16630 */ "fcvtnu\t\0"
1841 /* 16638 */ "fcvtpu\t\0"
1842 /* 16646 */ "fcvtzu\t\0"
1843 /* 16654 */ "st64bv\t\0"
1844 /* 16662 */ "faddv\t\0"
1845 /* 16669 */ "saddv\t\0"
1846 /* 16676 */ "uaddv\t\0"
1847 /* 16683 */ "andv\t\0"
1848 /* 16689 */ "rev\t\0"
1849 /* 16694 */ "fdiv\t\0"
1850 /* 16700 */ "sdiv\t\0"
1851 /* 16706 */ "udiv\t\0"
1852 /* 16712 */ "fminnmv\t\0"
1853 /* 16721 */ "fmaxnmv\t\0"
1854 /* 16730 */ "fminv\t\0"
1855 /* 16737 */ "sminv\t\0"
1856 /* 16744 */ "uminv\t\0"
1857 /* 16751 */ "csinv\t\0"
1858 /* 16758 */ "fmov\t\0"
1859 /* 16764 */ "eorv\t\0"
1860 /* 16770 */ "fmaxv\t\0"
1861 /* 16777 */ "smaxv\t\0"
1862 /* 16784 */ "umaxv\t\0"
1863 /* 16791 */ "ld1w\t\0"
1864 /* 16797 */ "ldff1w\t\0"
1865 /* 16805 */ "ldnf1w\t\0"
1866 /* 16813 */ "ldnt1w\t\0"
1867 /* 16821 */ "stnt1w\t\0"
1868 /* 16829 */ "st1w\t\0"
1869 /* 16835 */ "crc32w\t\0"
1870 /* 16843 */ "ld2w\t\0"
1871 /* 16849 */ "st2w\t\0"
1872 /* 16855 */ "ld3w\t\0"
1873 /* 16861 */ "st3w\t\0"
1874 /* 16867 */ "ld4w\t\0"
1875 /* 16873 */ "st4w\t\0"
1876 /* 16879 */ "crc32cw\t\0"
1877 /* 16888 */ "sqdecw\t\0"
1878 /* 16896 */ "uqdecw\t\0"
1879 /* 16904 */ "sqincw\t\0"
1880 /* 16912 */ "uqincw\t\0"
1881 /* 16920 */ "prfw\t\0"
1882 /* 16926 */ "ld1row\t\0"
1883 /* 16934 */ "ld1rqw\t\0"
1884 /* 16942 */ "ld1rw\t\0"
1885 /* 16949 */ "whilerw\t\0"
1886 /* 16958 */ "ld1sw\t\0"
1887 /* 16965 */ "ldff1sw\t\0"
1888 /* 16974 */ "ldnf1sw\t\0"
1889 /* 16983 */ "ldnt1sw\t\0"
1890 /* 16992 */ "ldpsw\t\0"
1891 /* 16999 */ "ld1rsw\t\0"
1892 /* 17007 */ "ldrsw\t\0"
1893 /* 17014 */ "ldtrsw\t\0"
1894 /* 17022 */ "ldursw\t\0"
1895 /* 17030 */ "ldapursw\t\0"
1896 /* 17040 */ "cntw\t\0"
1897 /* 17046 */ "sxtw\t\0"
1898 /* 17052 */ "uxtw\t\0"
1899 /* 17058 */ "revw\t\0"
1900 /* 17064 */ "crc32x\t\0"
1901 /* 17072 */ "frint32x\t\0"
1902 /* 17082 */ "frint64x\t\0"
1903 /* 17092 */ "bcax\t\0"
1904 /* 17098 */ "fmax\t\0"
1905 /* 17104 */ "ldsmax\t\0"
1906 /* 17112 */ "ldumax\t\0"
1907 /* 17120 */ "tbx\t\0"
1908 /* 17125 */ "crc32cx\t\0"
1909 /* 17134 */ "index\t\0"
1910 /* 17141 */ "clrex\t\0"
1911 /* 17148 */ "movprfx\t\0"
1912 /* 17157 */ "fmulx\t\0"
1913 /* 17164 */ "frecpx\t\0"
1914 /* 17172 */ "frintx\t\0"
1915 /* 17180 */ "fcvtx\t\0"
1916 /* 17187 */ "sm4ekey\t\0"
1917 /* 17196 */ "fcpy\t\0"
1918 /* 17202 */ "frint32z\t\0"
1919 /* 17212 */ "frint64z\t\0"
1920 /* 17222 */ "braaz\t\0"
1921 /* 17229 */ "blraaz\t\0"
1922 /* 17237 */ "brabz\t\0"
1923 /* 17244 */ "blrabz\t\0"
1924 /* 17252 */ "cbz\t\0"
1925 /* 17257 */ "tbz\t\0"
1926 /* 17262 */ "clz\t\0"
1927 /* 17267 */ "cbnz\t\0"
1928 /* 17273 */ "tbnz\t\0"
1929 /* 17279 */ "frintz\t\0"
1930 /* 17287 */ "movz\t\0"
1931 /* 17293 */ ".tlsdesccall \0"
1932 /* 17307 */ "# XRay Function Patchable RET.\0"
1933 /* 17338 */ "b.\0"
1934 /* 17341 */ "# XRay Typed Event Log.\0"
1935 /* 17365 */ "# XRay Custom Event Log.\0"
1936 /* 17390 */ "# XRay Function Enter.\0"
1937 /* 17413 */ "# XRay Tail Call Exit.\0"
1938 /* 17436 */ "# XRay Function Exit.\0"
1939 /* 17458 */ "hint\t#10\0"
1940 /* 17467 */ "hint\t#30\0"
1941 /* 17476 */ "hint\t#31\0"
1942 /* 17485 */ "hint\t#12\0"
1943 /* 17494 */ "fmlal2\0"
1944 /* 17501 */ "fmlsl2\0"
1945 /* 17508 */ "hint\t#14\0"
1946 /* 17517 */ "hint\t#24\0"
1947 /* 17526 */ "hint\t#25\0"
1948 /* 17535 */ "setf16\0"
1949 /* 17542 */ "hint\t#26\0"
1950 /* 17551 */ "hint\t#7\0"
1951 /* 17559 */ "hint\t#27\0"
1952 /* 17568 */ "hint\t#8\0"
1953 /* 17576 */ "hint\t#28\0"
1954 /* 17585 */ "setf8\0"
1955 /* 17591 */ "hint\t#29\0"
1956 /* 17600 */ "LIFETIME_END\0"
1957 /* 17613 */ "PSEUDO_PROBE\0"
1958 /* 17626 */ "BUNDLE\0"
1959 /* 17633 */ "DBG_VALUE\0"
1960 /* 17643 */ "DBG_INSTR_REF\0"
1961 /* 17657 */ "DBG_LABEL\0"
1962 /* 17667 */ "LIFETIME_START\0"
1963 /* 17682 */ "eretaa\0"
1964 /* 17689 */ "bfmmla\0"
1965 /* 17696 */ "usmmla\0"
1966 /* 17703 */ "ummla\0"
1967 /* 17709 */ "eretab\0"
1968 /* 17716 */ "bfmlalb\0"
1969 /* 17724 */ "sb\0"
1970 /* 17727 */ "rmif\0"
1971 /* 17732 */ "xaflag\0"
1972 /* 17739 */ "axflag\0"
1973 /* 17746 */ "brb\tinj\0"
1974 /* 17754 */ "fmlal\0"
1975 /* 17760 */ "# FEntry call\0"
1976 /* 17774 */ "brb\tiall\0"
1977 /* 17783 */ "fmlsl\0"
1978 /* 17789 */ "setffr\0"
1979 /* 17796 */ "drps\0"
1980 /* 17801 */ "eret\0"
1981 /* 17806 */ "tcommit\0"
1982 /* 17814 */ "bfmlalt\0"
1983 /* 17822 */ "bfdot\0"
1984 /* 17828 */ "usdot\0"
1985 /* 17834 */ "udot\0"
1986 /* 17839 */ "cfinv\0"
1987};
1988#ifdef __GNUC__
1989#pragma GCC diagnostic pop
1990#endif
1991
1992 static const uint32_t OpInfo0[] = {
1993 0U, // PHI
1994 0U, // INLINEASM
1995 0U, // INLINEASM_BR
1996 0U, // CFI_INSTRUCTION
1997 0U, // EH_LABEL
1998 0U, // GC_LABEL
1999 0U, // ANNOTATION_LABEL
2000 0U, // KILL
2001 0U, // EXTRACT_SUBREG
2002 0U, // INSERT_SUBREG
2003 0U, // IMPLICIT_DEF
2004 0U, // SUBREG_TO_REG
2005 0U, // COPY_TO_REGCLASS
2006 17634U, // DBG_VALUE
2007 17644U, // DBG_INSTR_REF
2008 17658U, // DBG_LABEL
2009 0U, // REG_SEQUENCE
2010 0U, // COPY
2011 17627U, // BUNDLE
2012 17668U, // LIFETIME_START
2013 17601U, // LIFETIME_END
2014 17614U, // PSEUDO_PROBE
2015 0U, // STACKMAP
2016 17761U, // FENTRY_CALL
2017 0U, // PATCHPOINT
2018 0U, // LOAD_STACK_GUARD
2019 0U, // PREALLOCATED_SETUP
2020 0U, // PREALLOCATED_ARG
2021 0U, // STATEPOINT
2022 0U, // LOCAL_ESCAPE
2023 0U, // FAULTING_OP
2024 0U, // PATCHABLE_OP
2025 17391U, // PATCHABLE_FUNCTION_ENTER
2026 17308U, // PATCHABLE_RET
2027 17437U, // PATCHABLE_FUNCTION_EXIT
2028 17414U, // PATCHABLE_TAIL_CALL
2029 17366U, // PATCHABLE_EVENT_CALL
2030 17342U, // PATCHABLE_TYPED_EVENT_CALL
2031 0U, // ICALL_BRANCH_FUNNEL
2032 0U, // G_ADD
2033 0U, // G_SUB
2034 0U, // G_MUL
2035 0U, // G_SDIV
2036 0U, // G_UDIV
2037 0U, // G_SREM
2038 0U, // G_UREM
2039 0U, // G_AND
2040 0U, // G_OR
2041 0U, // G_XOR
2042 0U, // G_IMPLICIT_DEF
2043 0U, // G_PHI
2044 0U, // G_FRAME_INDEX
2045 0U, // G_GLOBAL_VALUE
2046 0U, // G_EXTRACT
2047 0U, // G_UNMERGE_VALUES
2048 0U, // G_INSERT
2049 0U, // G_MERGE_VALUES
2050 0U, // G_BUILD_VECTOR
2051 0U, // G_BUILD_VECTOR_TRUNC
2052 0U, // G_CONCAT_VECTORS
2053 0U, // G_PTRTOINT
2054 0U, // G_INTTOPTR
2055 0U, // G_BITCAST
2056 0U, // G_FREEZE
2057 0U, // G_INTRINSIC_TRUNC
2058 0U, // G_INTRINSIC_ROUND
2059 0U, // G_INTRINSIC_LRINT
2060 0U, // G_INTRINSIC_ROUNDEVEN
2061 0U, // G_READCYCLECOUNTER
2062 0U, // G_LOAD
2063 0U, // G_SEXTLOAD
2064 0U, // G_ZEXTLOAD
2065 0U, // G_INDEXED_LOAD
2066 0U, // G_INDEXED_SEXTLOAD
2067 0U, // G_INDEXED_ZEXTLOAD
2068 0U, // G_STORE
2069 0U, // G_INDEXED_STORE
2070 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2071 0U, // G_ATOMIC_CMPXCHG
2072 0U, // G_ATOMICRMW_XCHG
2073 0U, // G_ATOMICRMW_ADD
2074 0U, // G_ATOMICRMW_SUB
2075 0U, // G_ATOMICRMW_AND
2076 0U, // G_ATOMICRMW_NAND
2077 0U, // G_ATOMICRMW_OR
2078 0U, // G_ATOMICRMW_XOR
2079 0U, // G_ATOMICRMW_MAX
2080 0U, // G_ATOMICRMW_MIN
2081 0U, // G_ATOMICRMW_UMAX
2082 0U, // G_ATOMICRMW_UMIN
2083 0U, // G_ATOMICRMW_FADD
2084 0U, // G_ATOMICRMW_FSUB
2085 0U, // G_FENCE
2086 0U, // G_BRCOND
2087 0U, // G_BRINDIRECT
2088 0U, // G_INTRINSIC
2089 0U, // G_INTRINSIC_W_SIDE_EFFECTS
2090 0U, // G_ANYEXT
2091 0U, // G_TRUNC
2092 0U, // G_CONSTANT
2093 0U, // G_FCONSTANT
2094 0U, // G_VASTART
2095 0U, // G_VAARG
2096 0U, // G_SEXT
2097 0U, // G_SEXT_INREG
2098 0U, // G_ZEXT
2099 0U, // G_SHL
2100 0U, // G_LSHR
2101 0U, // G_ASHR
2102 0U, // G_FSHL
2103 0U, // G_FSHR
2104 0U, // G_ICMP
2105 0U, // G_FCMP
2106 0U, // G_SELECT
2107 0U, // G_UADDO
2108 0U, // G_UADDE
2109 0U, // G_USUBO
2110 0U, // G_USUBE
2111 0U, // G_SADDO
2112 0U, // G_SADDE
2113 0U, // G_SSUBO
2114 0U, // G_SSUBE
2115 0U, // G_UMULO
2116 0U, // G_SMULO
2117 0U, // G_UMULH
2118 0U, // G_SMULH
2119 0U, // G_UADDSAT
2120 0U, // G_SADDSAT
2121 0U, // G_USUBSAT
2122 0U, // G_SSUBSAT
2123 0U, // G_USHLSAT
2124 0U, // G_SSHLSAT
2125 0U, // G_SMULFIX
2126 0U, // G_UMULFIX
2127 0U, // G_SMULFIXSAT
2128 0U, // G_UMULFIXSAT
2129 0U, // G_SDIVFIX
2130 0U, // G_UDIVFIX
2131 0U, // G_SDIVFIXSAT
2132 0U, // G_UDIVFIXSAT
2133 0U, // G_FADD
2134 0U, // G_FSUB
2135 0U, // G_FMUL
2136 0U, // G_FMA
2137 0U, // G_FMAD
2138 0U, // G_FDIV
2139 0U, // G_FREM
2140 0U, // G_FPOW
2141 0U, // G_FPOWI
2142 0U, // G_FEXP
2143 0U, // G_FEXP2
2144 0U, // G_FLOG
2145 0U, // G_FLOG2
2146 0U, // G_FLOG10
2147 0U, // G_FNEG
2148 0U, // G_FPEXT
2149 0U, // G_FPTRUNC
2150 0U, // G_FPTOSI
2151 0U, // G_FPTOUI
2152 0U, // G_SITOFP
2153 0U, // G_UITOFP
2154 0U, // G_FABS
2155 0U, // G_FCOPYSIGN
2156 0U, // G_FCANONICALIZE
2157 0U, // G_FMINNUM
2158 0U, // G_FMAXNUM
2159 0U, // G_FMINNUM_IEEE
2160 0U, // G_FMAXNUM_IEEE
2161 0U, // G_FMINIMUM
2162 0U, // G_FMAXIMUM
2163 0U, // G_PTR_ADD
2164 0U, // G_PTRMASK
2165 0U, // G_SMIN
2166 0U, // G_SMAX
2167 0U, // G_UMIN
2168 0U, // G_UMAX
2169 0U, // G_ABS
2170 0U, // G_BR
2171 0U, // G_BRJT
2172 0U, // G_INSERT_VECTOR_ELT
2173 0U, // G_EXTRACT_VECTOR_ELT
2174 0U, // G_SHUFFLE_VECTOR
2175 0U, // G_CTTZ
2176 0U, // G_CTTZ_ZERO_UNDEF
2177 0U, // G_CTLZ
2178 0U, // G_CTLZ_ZERO_UNDEF
2179 0U, // G_CTPOP
2180 0U, // G_BSWAP
2181 0U, // G_BITREVERSE
2182 0U, // G_FCEIL
2183 0U, // G_FCOS
2184 0U, // G_FSIN
2185 0U, // G_FSQRT
2186 0U, // G_FFLOOR
2187 0U, // G_FRINT
2188 0U, // G_FNEARBYINT
2189 0U, // G_ADDRSPACE_CAST
2190 0U, // G_BLOCK_ADDR
2191 0U, // G_JUMP_TABLE
2192 0U, // G_DYN_STACKALLOC
2193 0U, // G_STRICT_FADD
2194 0U, // G_STRICT_FSUB
2195 0U, // G_STRICT_FMUL
2196 0U, // G_STRICT_FDIV
2197 0U, // G_STRICT_FREM
2198 0U, // G_STRICT_FMA
2199 0U, // G_STRICT_FSQRT
2200 0U, // G_READ_REGISTER
2201 0U, // G_WRITE_REGISTER
2202 0U, // G_MEMCPY
2203 0U, // G_MEMMOVE
2204 0U, // G_MEMSET
2205 0U, // G_VECREDUCE_SEQ_FADD
2206 0U, // G_VECREDUCE_SEQ_FMUL
2207 0U, // G_VECREDUCE_FADD
2208 0U, // G_VECREDUCE_FMUL
2209 0U, // G_VECREDUCE_FMAX
2210 0U, // G_VECREDUCE_FMIN
2211 0U, // G_VECREDUCE_ADD
2212 0U, // G_VECREDUCE_MUL
2213 0U, // G_VECREDUCE_AND
2214 0U, // G_VECREDUCE_OR
2215 0U, // G_VECREDUCE_XOR
2216 0U, // G_VECREDUCE_SMAX
2217 0U, // G_VECREDUCE_SMIN
2218 0U, // G_VECREDUCE_UMAX
2219 0U, // G_VECREDUCE_UMIN
2220 0U, // ADDSWrr
2221 0U, // ADDSXrr
2222 0U, // ADDWrr
2223 0U, // ADDXrr
2224 0U, // ADD_ZPZZ_UNDEF_B
2225 0U, // ADD_ZPZZ_UNDEF_D
2226 0U, // ADD_ZPZZ_UNDEF_H
2227 0U, // ADD_ZPZZ_UNDEF_S
2228 0U, // ADD_ZPZZ_ZERO_B
2229 0U, // ADD_ZPZZ_ZERO_D
2230 0U, // ADD_ZPZZ_ZERO_H
2231 0U, // ADD_ZPZZ_ZERO_S
2232 0U, // ADDlowTLS
2233 0U, // ADJCALLSTACKDOWN
2234 0U, // ADJCALLSTACKUP
2235 0U, // AESIMCrrTied
2236 0U, // AESMCrrTied
2237 0U, // ANDSWrr
2238 0U, // ANDSXrr
2239 0U, // ANDWrr
2240 0U, // ANDXrr
2241 0U, // ASRD_ZPZI_ZERO_B
2242 0U, // ASRD_ZPZI_ZERO_D
2243 0U, // ASRD_ZPZI_ZERO_H
2244 0U, // ASRD_ZPZI_ZERO_S
2245 0U, // ASR_ZPZI_UNDEF_B
2246 0U, // ASR_ZPZI_UNDEF_D
2247 0U, // ASR_ZPZI_UNDEF_H
2248 0U, // ASR_ZPZI_UNDEF_S
2249 0U, // ASR_ZPZZ_UNDEF_B
2250 0U, // ASR_ZPZZ_UNDEF_D
2251 0U, // ASR_ZPZZ_UNDEF_H
2252 0U, // ASR_ZPZZ_UNDEF_S
2253 0U, // ASR_ZPZZ_ZERO_B
2254 0U, // ASR_ZPZZ_ZERO_D
2255 0U, // ASR_ZPZZ_ZERO_H
2256 0U, // ASR_ZPZZ_ZERO_S
2257 0U, // BICSWrr
2258 0U, // BICSXrr
2259 0U, // BICWrr
2260 0U, // BICXrr
2261 0U, // BLRNoIP
2262 0U, // BLR_RVMARKER
2263 0U, // BSPv16i8
2264 0U, // BSPv8i8
2265 0U, // CATCHRET
2266 0U, // CLEANUPRET
2267 0U, // CMP_SWAP_128
2268 0U, // CMP_SWAP_16
2269 0U, // CMP_SWAP_32
2270 0U, // CMP_SWAP_64
2271 0U, // CMP_SWAP_8
2272 0U, // CompilerBarrier
2273 0U, // EMITBKEY
2274 0U, // EONWrr
2275 0U, // EONXrr
2276 0U, // EORWrr
2277 0U, // EORXrr
2278 0U, // F128CSEL
2279 0U, // FABD_ZPZZ_ZERO_D
2280 0U, // FABD_ZPZZ_ZERO_H
2281 0U, // FABD_ZPZZ_ZERO_S
2282 0U, // FADD_ZPZZ_UNDEF_D
2283 0U, // FADD_ZPZZ_UNDEF_H
2284 0U, // FADD_ZPZZ_UNDEF_S
2285 0U, // FADD_ZPZZ_ZERO_D
2286 0U, // FADD_ZPZZ_ZERO_H
2287 0U, // FADD_ZPZZ_ZERO_S
2288 0U, // FDIVR_ZPZZ_ZERO_D
2289 0U, // FDIVR_ZPZZ_ZERO_H
2290 0U, // FDIVR_ZPZZ_ZERO_S
2291 0U, // FDIV_ZPZZ_UNDEF_D
2292 0U, // FDIV_ZPZZ_UNDEF_H
2293 0U, // FDIV_ZPZZ_UNDEF_S
2294 0U, // FDIV_ZPZZ_ZERO_D
2295 0U, // FDIV_ZPZZ_ZERO_H
2296 0U, // FDIV_ZPZZ_ZERO_S
2297 0U, // FMAXNM_ZPZZ_UNDEF_D
2298 0U, // FMAXNM_ZPZZ_UNDEF_H
2299 0U, // FMAXNM_ZPZZ_UNDEF_S
2300 0U, // FMAXNM_ZPZZ_ZERO_D
2301 0U, // FMAXNM_ZPZZ_ZERO_H
2302 0U, // FMAXNM_ZPZZ_ZERO_S
2303 0U, // FMAX_ZPZZ_ZERO_D
2304 0U, // FMAX_ZPZZ_ZERO_H
2305 0U, // FMAX_ZPZZ_ZERO_S
2306 0U, // FMINNM_ZPZZ_UNDEF_D
2307 0U, // FMINNM_ZPZZ_UNDEF_H
2308 0U, // FMINNM_ZPZZ_UNDEF_S
2309 0U, // FMINNM_ZPZZ_ZERO_D
2310 0U, // FMINNM_ZPZZ_ZERO_H
2311 0U, // FMINNM_ZPZZ_ZERO_S
2312 0U, // FMIN_ZPZZ_ZERO_D
2313 0U, // FMIN_ZPZZ_ZERO_H
2314 0U, // FMIN_ZPZZ_ZERO_S
2315 0U, // FMOVD0
2316 0U, // FMOVH0
2317 0U, // FMOVS0
2318 0U, // FMULX_ZPZZ_ZERO_D
2319 0U, // FMULX_ZPZZ_ZERO_H
2320 0U, // FMULX_ZPZZ_ZERO_S
2321 0U, // FMUL_ZPZZ_UNDEF_D
2322 0U, // FMUL_ZPZZ_UNDEF_H
2323 0U, // FMUL_ZPZZ_UNDEF_S
2324 0U, // FMUL_ZPZZ_ZERO_D
2325 0U, // FMUL_ZPZZ_ZERO_H
2326 0U, // FMUL_ZPZZ_ZERO_S
2327 0U, // FSUBR_ZPZZ_ZERO_D
2328 0U, // FSUBR_ZPZZ_ZERO_H
2329 0U, // FSUBR_ZPZZ_ZERO_S
2330 0U, // FSUB_ZPZZ_UNDEF_D
2331 0U, // FSUB_ZPZZ_UNDEF_H
2332 0U, // FSUB_ZPZZ_UNDEF_S
2333 0U, // FSUB_ZPZZ_ZERO_D
2334 0U, // FSUB_ZPZZ_ZERO_H
2335 0U, // FSUB_ZPZZ_ZERO_S
2336 0U, // GLD1B_D
2337 0U, // GLD1B_D_IMM
2338 0U, // GLD1B_D_SXTW
2339 0U, // GLD1B_D_UXTW
2340 0U, // GLD1B_S_IMM
2341 0U, // GLD1B_S_SXTW
2342 0U, // GLD1B_S_UXTW
2343 0U, // GLD1D
2344 0U, // GLD1D_IMM
2345 0U, // GLD1D_SCALED
2346 0U, // GLD1D_SXTW
2347 0U, // GLD1D_SXTW_SCALED
2348 0U, // GLD1D_UXTW
2349 0U, // GLD1D_UXTW_SCALED
2350 0U, // GLD1H_D
2351 0U, // GLD1H_D_IMM
2352 0U, // GLD1H_D_SCALED
2353 0U, // GLD1H_D_SXTW
2354 0U, // GLD1H_D_SXTW_SCALED
2355 0U, // GLD1H_D_UXTW
2356 0U, // GLD1H_D_UXTW_SCALED
2357 0U, // GLD1H_S_IMM
2358 0U, // GLD1H_S_SXTW
2359 0U, // GLD1H_S_SXTW_SCALED
2360 0U, // GLD1H_S_UXTW
2361 0U, // GLD1H_S_UXTW_SCALED
2362 0U, // GLD1SB_D
2363 0U, // GLD1SB_D_IMM
2364 0U, // GLD1SB_D_SXTW
2365 0U, // GLD1SB_D_UXTW
2366 0U, // GLD1SB_S_IMM
2367 0U, // GLD1SB_S_SXTW
2368 0U, // GLD1SB_S_UXTW
2369 0U, // GLD1SH_D
2370 0U, // GLD1SH_D_IMM
2371 0U, // GLD1SH_D_SCALED
2372 0U, // GLD1SH_D_SXTW
2373 0U, // GLD1SH_D_SXTW_SCALED
2374 0U, // GLD1SH_D_UXTW
2375 0U, // GLD1SH_D_UXTW_SCALED
2376 0U, // GLD1SH_S_IMM
2377 0U, // GLD1SH_S_SXTW
2378 0U, // GLD1SH_S_SXTW_SCALED
2379 0U, // GLD1SH_S_UXTW
2380 0U, // GLD1SH_S_UXTW_SCALED
2381 0U, // GLD1SW_D
2382 0U, // GLD1SW_D_IMM
2383 0U, // GLD1SW_D_SCALED
2384 0U, // GLD1SW_D_SXTW
2385 0U, // GLD1SW_D_SXTW_SCALED
2386 0U, // GLD1SW_D_UXTW
2387 0U, // GLD1SW_D_UXTW_SCALED
2388 0U, // GLD1W_D
2389 0U, // GLD1W_D_IMM
2390 0U, // GLD1W_D_SCALED
2391 0U, // GLD1W_D_SXTW
2392 0U, // GLD1W_D_SXTW_SCALED
2393 0U, // GLD1W_D_UXTW
2394 0U, // GLD1W_D_UXTW_SCALED
2395 0U, // GLD1W_IMM
2396 0U, // GLD1W_SXTW
2397 0U, // GLD1W_SXTW_SCALED
2398 0U, // GLD1W_UXTW
2399 0U, // GLD1W_UXTW_SCALED
2400 0U, // GLDFF1B_D
2401 0U, // GLDFF1B_D_IMM
2402 0U, // GLDFF1B_D_SXTW
2403 0U, // GLDFF1B_D_UXTW
2404 0U, // GLDFF1B_S_IMM
2405 0U, // GLDFF1B_S_SXTW
2406 0U, // GLDFF1B_S_UXTW
2407 0U, // GLDFF1D
2408 0U, // GLDFF1D_IMM
2409 0U, // GLDFF1D_SCALED
2410 0U, // GLDFF1D_SXTW
2411 0U, // GLDFF1D_SXTW_SCALED
2412 0U, // GLDFF1D_UXTW
2413 0U, // GLDFF1D_UXTW_SCALED
2414 0U, // GLDFF1H_D
2415 0U, // GLDFF1H_D_IMM
2416 0U, // GLDFF1H_D_SCALED
2417 0U, // GLDFF1H_D_SXTW
2418 0U, // GLDFF1H_D_SXTW_SCALED
2419 0U, // GLDFF1H_D_UXTW
2420 0U, // GLDFF1H_D_UXTW_SCALED
2421 0U, // GLDFF1H_S_IMM
2422 0U, // GLDFF1H_S_SXTW
2423 0U, // GLDFF1H_S_SXTW_SCALED
2424 0U, // GLDFF1H_S_UXTW
2425 0U, // GLDFF1H_S_UXTW_SCALED
2426 0U, // GLDFF1SB_D
2427 0U, // GLDFF1SB_D_IMM
2428 0U, // GLDFF1SB_D_SXTW
2429 0U, // GLDFF1SB_D_UXTW
2430 0U, // GLDFF1SB_S_IMM
2431 0U, // GLDFF1SB_S_SXTW
2432 0U, // GLDFF1SB_S_UXTW
2433 0U, // GLDFF1SH_D
2434 0U, // GLDFF1SH_D_IMM
2435 0U, // GLDFF1SH_D_SCALED
2436 0U, // GLDFF1SH_D_SXTW
2437 0U, // GLDFF1SH_D_SXTW_SCALED
2438 0U, // GLDFF1SH_D_UXTW
2439 0U, // GLDFF1SH_D_UXTW_SCALED
2440 0U, // GLDFF1SH_S_IMM
2441 0U, // GLDFF1SH_S_SXTW
2442 0U, // GLDFF1SH_S_SXTW_SCALED
2443 0U, // GLDFF1SH_S_UXTW
2444 0U, // GLDFF1SH_S_UXTW_SCALED
2445 0U, // GLDFF1SW_D
2446 0U, // GLDFF1SW_D_IMM
2447 0U, // GLDFF1SW_D_SCALED
2448 0U, // GLDFF1SW_D_SXTW
2449 0U, // GLDFF1SW_D_SXTW_SCALED
2450 0U, // GLDFF1SW_D_UXTW
2451 0U, // GLDFF1SW_D_UXTW_SCALED
2452 0U, // GLDFF1W_D
2453 0U, // GLDFF1W_D_IMM
2454 0U, // GLDFF1W_D_SCALED
2455 0U, // GLDFF1W_D_SXTW
2456 0U, // GLDFF1W_D_SXTW_SCALED
2457 0U, // GLDFF1W_D_UXTW
2458 0U, // GLDFF1W_D_UXTW_SCALED
2459 0U, // GLDFF1W_IMM
2460 0U, // GLDFF1W_SXTW
2461 0U, // GLDFF1W_SXTW_SCALED
2462 0U, // GLDFF1W_UXTW
2463 0U, // GLDFF1W_UXTW_SCALED
2464 0U, // G_ADD_LOW
2465 0U, // G_DUP
2466 0U, // G_DUPLANE16
2467 0U, // G_DUPLANE32
2468 0U, // G_DUPLANE64
2469 0U, // G_DUPLANE8
2470 0U, // G_EXT
2471 0U, // G_REV16
2472 0U, // G_REV32
2473 0U, // G_REV64
2474 0U, // G_SITOF
2475 0U, // G_TRN1
2476 0U, // G_TRN2
2477 0U, // G_UITOF
2478 0U, // G_UZP1
2479 0U, // G_UZP2
2480 0U, // G_VASHR
2481 0U, // G_VLSHR
2482 0U, // G_ZIP1
2483 0U, // G_ZIP2
2484 0U, // HWASAN_CHECK_MEMACCESS
2485 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES
2486 0U, // IRGstack
2487 0U, // JumpTableDest16
2488 0U, // JumpTableDest32
2489 0U, // JumpTableDest8
2490 0U, // LD1B_D_IMM
2491 0U, // LD1B_H_IMM
2492 0U, // LD1B_IMM
2493 0U, // LD1B_S_IMM
2494 0U, // LD1D_IMM
2495 0U, // LD1H_D_IMM
2496 0U, // LD1H_IMM
2497 0U, // LD1H_S_IMM
2498 0U, // LD1SB_D_IMM
2499 0U, // LD1SB_H_IMM
2500 0U, // LD1SB_S_IMM
2501 0U, // LD1SH_D_IMM
2502 0U, // LD1SH_S_IMM
2503 0U, // LD1SW_D_IMM
2504 0U, // LD1W_D_IMM
2505 0U, // LD1W_IMM
2506 0U, // LDFF1B
2507 0U, // LDFF1B_D
2508 0U, // LDFF1B_H
2509 0U, // LDFF1B_S
2510 0U, // LDFF1D
2511 0U, // LDFF1H
2512 0U, // LDFF1H_D
2513 0U, // LDFF1H_S
2514 0U, // LDFF1SB_D
2515 0U, // LDFF1SB_H
2516 0U, // LDFF1SB_S
2517 0U, // LDFF1SH_D
2518 0U, // LDFF1SH_S
2519 0U, // LDFF1SW_D
2520 0U, // LDFF1W
2521 0U, // LDFF1W_D
2522 0U, // LDNF1B_D_IMM
2523 0U, // LDNF1B_H_IMM
2524 0U, // LDNF1B_IMM
2525 0U, // LDNF1B_S_IMM
2526 0U, // LDNF1D_IMM
2527 0U, // LDNF1H_D_IMM
2528 0U, // LDNF1H_IMM
2529 0U, // LDNF1H_S_IMM
2530 0U, // LDNF1SB_D_IMM
2531 0U, // LDNF1SB_H_IMM
2532 0U, // LDNF1SB_S_IMM
2533 0U, // LDNF1SH_D_IMM
2534 0U, // LDNF1SH_S_IMM
2535 0U, // LDNF1SW_D_IMM
2536 0U, // LDNF1W_D_IMM
2537 0U, // LDNF1W_IMM
2538 0U, // LDR_ZZXI
2539 0U, // LDR_ZZZXI
2540 0U, // LDR_ZZZZXI
2541 0U, // LOADgot
2542 0U, // LSL_ZPZI_UNDEF_B
2543 0U, // LSL_ZPZI_UNDEF_D
2544 0U, // LSL_ZPZI_UNDEF_H
2545 0U, // LSL_ZPZI_UNDEF_S
2546 0U, // LSL_ZPZZ_UNDEF_B
2547 0U, // LSL_ZPZZ_UNDEF_D
2548 0U, // LSL_ZPZZ_UNDEF_H
2549 0U, // LSL_ZPZZ_UNDEF_S
2550 0U, // LSL_ZPZZ_ZERO_B
2551 0U, // LSL_ZPZZ_ZERO_D
2552 0U, // LSL_ZPZZ_ZERO_H
2553 0U, // LSL_ZPZZ_ZERO_S
2554 0U, // LSR_ZPZI_UNDEF_B
2555 0U, // LSR_ZPZI_UNDEF_D
2556 0U, // LSR_ZPZI_UNDEF_H
2557 0U, // LSR_ZPZI_UNDEF_S
2558 0U, // LSR_ZPZZ_UNDEF_B
2559 0U, // LSR_ZPZZ_UNDEF_D
2560 0U, // LSR_ZPZZ_UNDEF_H
2561 0U, // LSR_ZPZZ_UNDEF_S
2562 0U, // LSR_ZPZZ_ZERO_B
2563 0U, // LSR_ZPZZ_ZERO_D
2564 0U, // LSR_ZPZZ_ZERO_H
2565 0U, // LSR_ZPZZ_ZERO_S
2566 0U, // MOVMCSym
2567 0U, // MOVaddr
2568 0U, // MOVaddrBA
2569 0U, // MOVaddrCP
2570 0U, // MOVaddrEXT
2571 0U, // MOVaddrJT
2572 0U, // MOVaddrTLS
2573 0U, // MOVbaseTLS
2574 0U, // MOVi32imm
2575 0U, // MOVi64imm
2576 0U, // MUL_ZPZZ_UNDEF_B
2577 0U, // MUL_ZPZZ_UNDEF_D
2578 0U, // MUL_ZPZZ_UNDEF_H
2579 0U, // MUL_ZPZZ_UNDEF_S
2580 0U, // ORNWrr
2581 0U, // ORNXrr
2582 0U, // ORRWrr
2583 0U, // ORRXrr
2584 0U, // RDFFR_P
2585 0U, // RDFFR_PPz
2586 0U, // RET_ReallyLR
2587 0U, // SDIV_ZPZZ_UNDEF_D
2588 0U, // SDIV_ZPZZ_UNDEF_S
2589 0U, // SEH_AddFP
2590 0U, // SEH_EpilogEnd
2591 0U, // SEH_EpilogStart
2592 0U, // SEH_Nop
2593 0U, // SEH_PrologEnd
2594 0U, // SEH_SaveFPLR
2595 0U, // SEH_SaveFPLR_X
2596 0U, // SEH_SaveFReg
2597 0U, // SEH_SaveFRegP
2598 0U, // SEH_SaveFRegP_X
2599 0U, // SEH_SaveFReg_X
2600 0U, // SEH_SaveReg
2601 0U, // SEH_SaveRegP
2602 0U, // SEH_SaveRegP_X
2603 0U, // SEH_SaveReg_X
2604 0U, // SEH_SetFP
2605 0U, // SEH_StackAlloc
2606 0U, // SMAX_ZPZZ_UNDEF_B
2607 0U, // SMAX_ZPZZ_UNDEF_D
2608 0U, // SMAX_ZPZZ_UNDEF_H
2609 0U, // SMAX_ZPZZ_UNDEF_S
2610 0U, // SMIN_ZPZZ_UNDEF_B
2611 0U, // SMIN_ZPZZ_UNDEF_D
2612 0U, // SMIN_ZPZZ_UNDEF_H
2613 0U, // SMIN_ZPZZ_UNDEF_S
2614 0U, // SPACE
2615 0U, // SQSHLU_ZPZI_ZERO_B
2616 0U, // SQSHLU_ZPZI_ZERO_D
2617 0U, // SQSHLU_ZPZI_ZERO_H
2618 0U, // SQSHLU_ZPZI_ZERO_S
2619 0U, // SQSHL_ZPZI_ZERO_B
2620 0U, // SQSHL_ZPZI_ZERO_D
2621 0U, // SQSHL_ZPZI_ZERO_H
2622 0U, // SQSHL_ZPZI_ZERO_S
2623 0U, // SRSHR_ZPZI_ZERO_B
2624 0U, // SRSHR_ZPZI_ZERO_D
2625 0U, // SRSHR_ZPZI_ZERO_H
2626 0U, // SRSHR_ZPZI_ZERO_S
2627 0U, // STGloop
2628 0U, // STGloop_wback
2629 0U, // STR_ZZXI
2630 0U, // STR_ZZZXI
2631 0U, // STR_ZZZZXI
2632 0U, // STZGloop
2633 0U, // STZGloop_wback
2634 0U, // SUBR_ZPZZ_ZERO_B
2635 0U, // SUBR_ZPZZ_ZERO_D
2636 0U, // SUBR_ZPZZ_ZERO_H
2637 0U, // SUBR_ZPZZ_ZERO_S
2638 0U, // SUBSWrr
2639 0U, // SUBSXrr
2640 0U, // SUBWrr
2641 0U, // SUBXrr
2642 0U, // SUB_ZPZZ_UNDEF_B
2643 0U, // SUB_ZPZZ_UNDEF_D
2644 0U, // SUB_ZPZZ_UNDEF_H
2645 0U, // SUB_ZPZZ_UNDEF_S
2646 0U, // SUB_ZPZZ_ZERO_B
2647 0U, // SUB_ZPZZ_ZERO_D
2648 0U, // SUB_ZPZZ_ZERO_H
2649 0U, // SUB_ZPZZ_ZERO_S
2650 0U, // SpeculationBarrierISBDSBEndBB
2651 0U, // SpeculationBarrierSBEndBB
2652 0U, // SpeculationSafeValueW
2653 0U, // SpeculationSafeValueX
2654 0U, // TAGPstack
2655 0U, // TCRETURNdi
2656 0U, // TCRETURNri
2657 0U, // TCRETURNriALL
2658 0U, // TCRETURNriBTI
2659 50062U, // TLSDESCCALL
2660 0U, // TLSDESC_CALLSEQ
2661 0U, // UDIV_ZPZZ_UNDEF_D
2662 0U, // UDIV_ZPZZ_UNDEF_S
2663 0U, // UMAX_ZPZZ_UNDEF_B
2664 0U, // UMAX_ZPZZ_UNDEF_D
2665 0U, // UMAX_ZPZZ_UNDEF_H
2666 0U, // UMAX_ZPZZ_UNDEF_S
2667 0U, // UMIN_ZPZZ_UNDEF_B
2668 0U, // UMIN_ZPZZ_UNDEF_D
2669 0U, // UMIN_ZPZZ_UNDEF_H
2670 0U, // UMIN_ZPZZ_UNDEF_S
2671 0U, // UQSHL_ZPZI_ZERO_B
2672 0U, // UQSHL_ZPZI_ZERO_D
2673 0U, // UQSHL_ZPZI_ZERO_H
2674 0U, // UQSHL_ZPZI_ZERO_S
2675 0U, // URSHR_ZPZI_ZERO_B
2676 0U, // URSHR_ZPZI_ZERO_D
2677 0U, // URSHR_ZPZI_ZERO_H
2678 0U, // URSHR_ZPZI_ZERO_S
2679 2178440U, // ABS_ZPmZ_B
2680 2211208U, // ABS_ZPmZ_D
2681 138558856U, // ABS_ZPmZ_H
2682 2276744U, // ABS_ZPmZ_S
2683 270730677U, // ABSv16i8
2684 404798856U, // ABSv1i64
2685 270742329U, // ABSv2i32
2686 270734402U, // ABSv2i64
2687 270736606U, // ABSv4i16
2688 270744408U, // ABSv4i32
2689 270738502U, // ABSv8i16
2690 270731636U, // ABSv8i8
2691 539069370U, // ADCLB_ZZZ_D
2692 673352634U, // ADCLB_ZZZ_S
2693 539082552U, // ADCLT_ZZZ_D
2694 673365816U, // ADCLT_ZZZ_S
2695 404798895U, // ADCSWr
2696 404798895U, // ADCSXr
2697 404786922U, // ADCWr
2698 404786922U, // ADCXr
2699 404789121U, // ADDG
2700 807472286U, // ADDHNB_ZZZ_B
2701 945949854U, // ADDHNB_ZZZ_H
2702 1076006046U, // ADDHNB_ZZZ_S
2703 1210138602U, // ADDHNT_ZZZ_B
2704 948060138U, // ADDHNT_ZZZ_H
2705 539148266U, // ADDHNT_ZZZ_S
2706 270741954U, // ADDHNv2i64_v2i32
2707 1344517630U, // ADDHNv2i64_v4i32
2708 270736220U, // ADDHNv4i32_v4i16
2709 1344511874U, // ADDHNv4i32_v8i16
2710 1344504460U, // ADDHNv8i16_v16i8
2711 270731376U, // ADDHNv8i16_v8i8
2712 404793945U, // ADDPL_XXI
2713 1478569005U, // ADDP_ZPmZ_B
2714 1478601773U, // ADDP_ZPmZ_D
2715 1621240877U, // ADDP_ZPmZ_H
2716 1478667309U, // ADDP_ZPmZ_S
2717 270730542U, // ADDPv16i8
2718 270742105U, // ADDPv2i32
2719 270734218U, // ADDPv2i64
2720 270570378U, // ADDPv2i64p
2721 270736382U, // ADDPv4i16
2722 270744184U, // ADDPv4i32
2723 270738278U, // ADDPv8i16
2724 270731514U, // ADDPv8i8
2725 404798907U, // ADDSWri
2726 404798907U, // ADDSWrs
2727 404798907U, // ADDSWrx
2728 404798907U, // ADDSXri
2729 404798907U, // ADDSXrs
2730 404798907U, // ADDSXrx
2731 404798907U, // ADDSXrx64
2732 404794057U, // ADDVL_XXI
2733 270566954U, // ADDVv16i8v
2734 270572993U, // ADDVv4i16v
2735 270580795U, // ADDVv4i32v
2736 270574889U, // ADDVv8i16v
2737 270567901U, // ADDVv8i8v
2738 404788775U, // ADDWri
2739 404788775U, // ADDWrs
2740 404788775U, // ADDWrx
2741 404788775U, // ADDXri
2742 404788775U, // ADDXrs
2743 404788775U, // ADDXrx
2744 404788775U, // ADDXrx64
2745 1746998823U, // ADD_ZI_B
2746 1075942951U, // ADD_ZI_D
2747 952243751U, // ADD_ZI_H
2748 1881314855U, // ADD_ZI_S
2749 1478563367U, // ADD_ZPmZ_B
2750 1478596135U, // ADD_ZPmZ_D
2751 1621235239U, // ADD_ZPmZ_H
2752 1478661671U, // ADD_ZPmZ_S
2753 1746998823U, // ADD_ZZZ_B
2754 1075942951U, // ADD_ZZZ_D
2755 952243751U, // ADD_ZZZ_H
2756 1881314855U, // ADD_ZZZ_S
2757 270730232U, // ADDv16i8
2758 404788775U, // ADDv1i64
2759 270741519U, // ADDv2i32
2760 270733691U, // ADDv2i64
2761 270735808U, // ADDv4i16
2762 270743485U, // ADDv4i32
2763 270737669U, // ADDv8i16
2764 270731128U, // ADDv8i8
2765 404794736U, // ADR
2766 2015407252U, // ADRP
2767 1088531824U, // ADR_LSL_ZZZ_D_0
2768 1088531824U, // ADR_LSL_ZZZ_D_1
2769 1088531824U, // ADR_LSL_ZZZ_D_2
2770 1088531824U, // ADR_LSL_ZZZ_D_3
2771 1893903728U, // ADR_LSL_ZZZ_S_0
2772 1893903728U, // ADR_LSL_ZZZ_S_1
2773 1893903728U, // ADR_LSL_ZZZ_S_2
2774 1893903728U, // ADR_LSL_ZZZ_S_3
2775 1088531824U, // ADR_SXTW_ZZZ_D_0
2776 1088531824U, // ADR_SXTW_ZZZ_D_1
2777 1088531824U, // ADR_SXTW_ZZZ_D_2
2778 1088531824U, // ADR_SXTW_ZZZ_D_3
2779 1088531824U, // ADR_UXTW_ZZZ_D_0
2780 1088531824U, // ADR_UXTW_ZZZ_D_1
2781 1088531824U, // ADR_UXTW_ZZZ_D_2
2782 1088531824U, // ADR_UXTW_ZZZ_D_3
2783 1746998951U, // AESD_ZZZ_B
2784 1344504900U, // AESDrr
2785 1746999092U, // AESE_ZZZ_B
2786 1344504930U, // AESErr
2787 1746996980U, // AESIMC_ZZ_B
2788 270730186U, // AESIMCrr
2789 1746996988U, // AESMC_ZZ_B
2790 270730198U, // AESMCrr
2791 404798914U, // ANDSWri
2792 404798914U, // ANDSWrs
2793 404798914U, // ANDSXri
2794 404798914U, // ANDSXrs
2795 1478573506U, // ANDS_PPzPP
2796 278828U, // ANDV_VPZ_B
2797 2164572460U, // ANDV_VPZ_D
2798 2166702380U, // ANDV_VPZ_H
2799 2156249388U, // ANDV_VPZ_S
2800 404788869U, // ANDWri
2801 404788869U, // ANDWrs
2802 404788869U, // ANDXri
2803 404788869U, // ANDXrs
2804 1478563461U, // AND_PPzPP
2805 1075943045U, // AND_ZI
2806 1478563461U, // AND_ZPmZ_B
2807 1478596229U, // AND_ZPmZ_D
2808 1621235333U, // AND_ZPmZ_H
2809 1478661765U, // AND_ZPmZ_S
2810 1075943045U, // AND_ZZZ
2811 270730299U, // ANDv16i8
2812 270731189U, // ANDv8i8
2813 1478563489U, // ASRD_ZPmI_B
2814 1478596257U, // ASRD_ZPmI_D
2815 1621235361U, // ASRD_ZPmI_H
2816 1478661793U, // ASRD_ZPmI_S
2817 1478569488U, // ASRR_ZPmZ_B
2818 1478602256U, // ASRR_ZPmZ_D
2819 1621241360U, // ASRR_ZPmZ_H
2820 1478667792U, // ASRR_ZPmZ_S
2821 404794908U, // ASRVWr
2822 404794908U, // ASRVXr
2823 1478569500U, // ASR_WIDE_ZPmZ_B
2824 1621241372U, // ASR_WIDE_ZPmZ_H
2825 1478667804U, // ASR_WIDE_ZPmZ_S
2826 1747004956U, // ASR_WIDE_ZZZ_B
2827 952249884U, // ASR_WIDE_ZZZ_H
2828 1881320988U, // ASR_WIDE_ZZZ_S
2829 1478569500U, // ASR_ZPmI_B
2830 1478602268U, // ASR_ZPmI_D
2831 1621241372U, // ASR_ZPmI_H
2832 1478667804U, // ASR_ZPmI_S
2833 1478569500U, // ASR_ZPmZ_B
2834 1478602268U, // ASR_ZPmZ_D
2835 1621241372U, // ASR_ZPmZ_H
2836 1478667804U, // ASR_ZPmZ_S
2837 1747004956U, // ASR_ZZI_B
2838 1075949084U, // ASR_ZZI_D
2839 952249884U, // ASR_ZZI_H
2840 1881320988U, // ASR_ZZI_S
2841 404783332U, // AUTDA
2842 404785892U, // AUTDB
2843 33216U, // AUTDZA
2844 36557U, // AUTDZB
2845 404783353U, // AUTIA
2846 17486U, // AUTIA1716
2847 17592U, // AUTIASP
2848 17577U, // AUTIAZ
2849 404785919U, // AUTIB
2850 17509U, // AUTIB1716
2851 17477U, // AUTIBSP
2852 17468U, // AUTIBZ
2853 33232U, // AUTIZA
2854 36573U, // AUTIZB
2855 17740U, // AXFLAG
2856 393692U, // B
2857 270730872U, // BCAX
2858 1075954373U, // BCAX_ZZZZ
2859 1747004472U, // BDEP_ZZZ_B
2860 1075948600U, // BDEP_ZZZ_D
2861 952249400U, // BDEP_ZZZ_H
2862 1881320504U, // BDEP_ZZZ_S
2863 1747009746U, // BEXT_ZZZ_B
2864 1075953874U, // BEXT_ZZZ_D
2865 952254674U, // BEXT_ZZZ_H
2866 1881325778U, // BEXT_ZZZ_S
2867 1344520292U, // BF16DOTlanev4bf16
2868 1344520292U, // BF16DOTlanev8bf16
2869 404799659U, // BFCVT
2870 270736314U, // BFCVTN
2871 1344511944U, // BFCVTN2
2872 2286043166U, // BFCVTNT_ZPmZ
2873 2286043307U, // BFCVT_ZPmZ
2874 1210237028U, // BFDOT_ZZI
2875 1210237028U, // BFDOT_ZZZ
2876 17823U, // BFDOTv4bf16
2877 17823U, // BFDOTv8bf16
2878 17717U, // BFMLALB
2879 17717U, // BFMLALBIdx
2880 17815U, // BFMLALT
2881 17815U, // BFMLALTIdx
2882 17690U, // BFMMLA
2883 1210223408U, // BFMMLA_B_ZZI
2884 1210223408U, // BFMMLA_B_ZZZ
2885 1210236680U, // BFMMLA_T_ZZI
2886 1210236680U, // BFMMLA_T_ZZZ
2887 1210220819U, // BFMMLA_ZZZ
2888 2418060009U, // BFMWri
2889 2418060009U, // BFMXri
2890 1747004570U, // BGRP_ZZZ_B
2891 1075948698U, // BGRP_ZZZ_D
2892 952249498U, // BGRP_ZZZ_H
2893 1881320602U, // BGRP_ZZZ_S
2894 404798901U, // BICSWrs
2895 404798901U, // BICSXrs
2896 1478573493U, // BICS_PPzPP
2897 404786927U, // BICWrs
2898 404786927U, // BICXrs
2899 1478561519U, // BIC_PPzPP
2900 1478561519U, // BIC_ZPmZ_B
2901 1478594287U, // BIC_ZPmZ_D
2902 1621233391U, // BIC_ZPmZ_H
2903 1478659823U, // BIC_ZPmZ_S
2904 1075941103U, // BIC_ZZZ
2905 270730177U, // BICv16i8
2906 2552475626U, // BICv2i32
2907 2552469915U, // BICv4i16
2908 2552477592U, // BICv4i32
2909 2552471776U, // BICv8i16
2910 270731099U, // BICv8i8
2911 1344504940U, // BIFv16i8
2912 1344505807U, // BIFv8i8
2913 1344505317U, // BITv16i8
2914 1344506271U, // BITv8i8
2915 403906U, // BL
2916 44450U, // BLR
2917 404783291U, // BLRAA
2918 49998U, // BLRAAZ
2919 404785775U, // BLRAB
2920 50013U, // BLRABZ
2921 44364U, // BR
2922 404783278U, // BRAA
2923 49991U, // BRAAZ
2924 404785762U, // BRAB
2925 50006U, // BRABZ
2926 17775U, // BRB_IALL
2927 17747U, // BRB_INJ
2928 436548U, // BRK
2929 1478573424U, // BRKAS_PPzP
2930 2162944U, // BRKA_PPmP
2931 1478557952U, // BRKA_PPzP
2932 1478573460U, // BRKBS_PPzP
2933 2165510U, // BRKB_PPmP
2934 1478560518U, // BRKB_PPzP
2935 1478573584U, // BRKNS_PPzP
2936 1478568790U, // BRKN_PPzP
2937 1478573431U, // BRKPAS_PPzPP
2938 1478558019U, // BRKPA_PPzPP
2939 1478573467U, // BRKPBS_PPzPP
2940 1478561044U, // BRKPB_PPzPP
2941 1075948338U, // BSL1N_ZZZZ
2942 1075948345U, // BSL2N_ZZZZ
2943 1075948164U, // BSL_ZZZZ
2944 1344505086U, // BSLv16i8
2945 1344505939U, // BSLv8i8
2946 476091U, // Bcc
2947 1746998822U, // CADD_ZZI_B
2948 1075942950U, // CADD_ZZI_D
2949 952243750U, // CADD_ZZI_H
2950 1881314854U, // CADD_ZZI_S
2951 2418510472U, // CASAB
2952 2418517604U, // CASAH
2953 2418510715U, // CASALB
2954 2418517763U, // CASALH
2955 2418518429U, // CASALW
2956 2418518429U, // CASALX
2957 2418508168U, // CASAW
2958 2418508168U, // CASAX
2959 2418511327U, // CASB
2960 2418518148U, // CASH
2961 2418510921U, // CASLB
2962 2418517857U, // CASLH
2963 2418518653U, // CASLW
2964 2418518653U, // CASLX
2965 534908U, // CASPALW
2966 567676U, // CASPALX
2967 524618U, // CASPAW
2968 557386U, // CASPAX
2969 535136U, // CASPLW
2970 567904U, // CASPLX
2971 535712U, // CASPW
2972 568480U, // CASPX
2973 2418523499U, // CASW
2974 2418523499U, // CASX
2975 2686501748U, // CBNZW
2976 2686501748U, // CBNZX
2977 2686501733U, // CBZW
2978 2686501733U, // CBZX
2979 404794204U, // CCMNWi
2980 404794204U, // CCMNWr
2981 404794204U, // CCMNXi
2982 404794204U, // CCMNXr
2983 404794453U, // CCMPWi
2984 404794453U, // CCMPWr
2985 404794453U, // CCMPXi
2986 404794453U, // CCMPXr
2987 1210171486U, // CDOT_ZZZI_D
2988 2820849758U, // CDOT_ZZZI_S
2989 1210171486U, // CDOT_ZZZ_D
2990 2820849758U, // CDOT_ZZZ_S
2991 17840U, // CFINV
2992 1478525342U, // CLASTA_RPZ_B
2993 1478525342U, // CLASTA_RPZ_D
2994 1478525342U, // CLASTA_RPZ_H
2995 1478525342U, // CLASTA_RPZ_S
2996 1478525342U, // CLASTA_VPZ_B
2997 1478525342U, // CLASTA_VPZ_D
2998 1478525342U, // CLASTA_VPZ_H
2999 1478525342U, // CLASTA_VPZ_S
3000 1478558110U, // CLASTA_ZPZ_B
3001 1478590878U, // CLASTA_ZPZ_D
3002 950141342U, // CLASTA_ZPZ_H
3003 1478656414U, // CLASTA_ZPZ_S
3004 1478528584U, // CLASTB_RPZ_B
3005 1478528584U, // CLASTB_RPZ_D
3006 1478528584U, // CLASTB_RPZ_H
3007 1478528584U, // CLASTB_RPZ_S
3008 1478528584U, // CLASTB_VPZ_B
3009 1478528584U, // CLASTB_VPZ_D
3010 1478528584U, // CLASTB_VPZ_H
3011 1478528584U, // CLASTB_VPZ_S
3012 1478561352U, // CLASTB_ZPZ_B
3013 1478594120U, // CLASTB_ZPZ_D
3014 950144584U, // CLASTB_ZPZ_H
3015 1478659656U, // CLASTB_ZPZ_S
3016 49910U, // CLREX
3017 404798950U, // CLSWr
3018 404798950U, // CLSXr
3019 2178534U, // CLS_ZPmZ_B
3020 2211302U, // CLS_ZPmZ_D
3021 138558950U, // CLS_ZPmZ_H
3022 2276838U, // CLS_ZPmZ_S
3023 270730696U, // CLSv16i8
3024 270742356U, // CLSv2i32
3025 270736633U, // CLSv4i16
3026 270744435U, // CLSv4i32
3027 270738529U, // CLSv8i16
3028 270731653U, // CLSv8i8
3029 404800367U, // CLZWr
3030 404800367U, // CLZXr
3031 2179951U, // CLZ_ZPmZ_B
3032 2212719U, // CLZ_ZPmZ_D
3033 138560367U, // CLZ_ZPmZ_H
3034 2278255U, // CLZ_ZPmZ_S
3035 270730902U, // CLZv16i8
3036 270742674U, // CLZv2i32
3037 270737014U, // CLZv4i16
3038 270744920U, // CLZv4i32
3039 270738950U, // CLZv8i16
3040 270731830U, // CLZv8i8
3041 270730605U, // CMEQv16i8
3042 270730605U, // CMEQv16i8rz
3043 404794633U, // CMEQv1i64
3044 404794633U, // CMEQv1i64rz
3045 270742262U, // CMEQv2i32
3046 270742262U, // CMEQv2i32rz
3047 270734335U, // CMEQv2i64
3048 270734335U, // CMEQv2i64rz
3049 270736539U, // CMEQv4i16
3050 270736539U, // CMEQv4i16rz
3051 270744341U, // CMEQv4i32
3052 270744341U, // CMEQv4i32rz
3053 270738435U, // CMEQv8i16
3054 270738435U, // CMEQv8i16rz
3055 270731571U, // CMEQv8i8
3056 270731571U, // CMEQv8i8rz
3057 270730318U, // CMGEv16i8
3058 270730318U, // CMGEv16i8rz
3059 404788946U, // CMGEv1i64
3060 404788946U, // CMGEv1i64rz
3061 270741611U, // CMGEv2i32
3062 270741611U, // CMGEv2i32rz
3063 270733741U, // CMGEv2i64
3064 270733741U, // CMGEv2i64rz
3065 270735900U, // CMGEv4i16
3066 270735900U, // CMGEv4i16rz
3067 270743586U, // CMGEv4i32
3068 270743586U, // CMGEv4i32rz
3069 270737761U, // CMGEv8i16
3070 270737761U, // CMGEv8i16rz
3071 270731197U, // CMGEv8i8
3072 270731197U, // CMGEv8i8rz
3073 270730714U, // CMGTv16i8
3074 270730714U, // CMGTv16i8rz
3075 404799189U, // CMGTv1i64
3076 404799189U, // CMGTv1i64rz
3077 270742451U, // CMGTv2i32
3078 270742451U, // CMGTv2i32rz
3079 270734516U, // CMGTv2i64
3080 270734516U, // CMGTv2i64rz
3081 270736728U, // CMGTv4i16
3082 270736728U, // CMGTv4i16rz
3083 270744530U, // CMGTv4i32
3084 270744530U, // CMGTv4i32rz
3085 270738624U, // CMGTv8i16
3086 270738624U, // CMGTv8i16rz
3087 270731669U, // CMGTv8i8
3088 270731669U, // CMGTv8i8rz
3089 270730368U, // CMHIv16i8
3090 404793626U, // CMHIv1i64
3091 270741766U, // CMHIv2i32
3092 270733834U, // CMHIv2i64
3093 270736032U, // CMHIv4i16
3094 270743753U, // CMHIv4i32
3095 270737893U, // CMHIv8i16
3096 270731233U, // CMHIv8i8
3097 270730686U, // CMHSv16i8
3098 404798937U, // CMHSv1i64
3099 270742347U, // CMHSv2i32
3100 270734420U, // CMHSv2i64
3101 270736624U, // CMHSv4i16
3102 270744426U, // CMHSv4i32
3103 270738520U, // CMHSv8i16
3104 270731644U, // CMHSv8i8
3105 958529799U, // CMLA_ZZZI_H
3106 673349895U, // CMLA_ZZZI_S
3107 2820735239U, // CMLA_ZZZ_B
3108 539066631U, // CMLA_ZZZ_D
3109 958529799U, // CMLA_ZZZ_H
3110 673349895U, // CMLA_ZZZ_S
3111 270730328U, // CMLEv16i8rz
3112 404788977U, // CMLEv1i64rz
3113 270741621U, // CMLEv2i32rz
3114 270733751U, // CMLEv2i64rz
3115 270735910U, // CMLEv4i16rz
3116 270743596U, // CMLEv4i32rz
3117 270737771U, // CMLEv8i16rz
3118 270731206U, // CMLEv8i8rz
3119 270730734U, // CMLTv16i8rz
3120 404799392U, // CMLTv1i64rz
3121 270742461U, // CMLTv2i32rz
3122 270734526U, // CMLTv2i64rz
3123 270736738U, // CMLTv4i16rz
3124 270744540U, // CMLTv4i32rz
3125 270738634U, // CMLTv8i16rz
3126 270731687U, // CMLTv8i8rz
3127 1478569240U, // CMPEQ_PPzZI_B
3128 1478602008U, // CMPEQ_PPzZI_D
3129 2963418392U, // CMPEQ_PPzZI_H
3130 1478667544U, // CMPEQ_PPzZI_S
3131 1478569240U, // CMPEQ_PPzZZ_B
3132 1478602008U, // CMPEQ_PPzZZ_D
3133 2963418392U, // CMPEQ_PPzZZ_H
3134 1478667544U, // CMPEQ_PPzZZ_S
3135 1478569240U, // CMPEQ_WIDE_PPzZZ_B
3136 2963418392U, // CMPEQ_WIDE_PPzZZ_H
3137 1478667544U, // CMPEQ_WIDE_PPzZZ_S
3138 1478563544U, // CMPGE_PPzZI_B
3139 1478596312U, // CMPGE_PPzZI_D
3140 2963412696U, // CMPGE_PPzZI_H
3141 1478661848U, // CMPGE_PPzZI_S
3142 1478563544U, // CMPGE_PPzZZ_B
3143 1478596312U, // CMPGE_PPzZZ_D
3144 2963412696U, // CMPGE_PPzZZ_H
3145 1478661848U, // CMPGE_PPzZZ_S
3146 1478563544U, // CMPGE_WIDE_PPzZZ_B
3147 2963412696U, // CMPGE_WIDE_PPzZZ_H
3148 1478661848U, // CMPGE_WIDE_PPzZZ_S
3149 1478573787U, // CMPGT_PPzZI_B
3150 1478606555U, // CMPGT_PPzZI_D
3151 2963422939U, // CMPGT_PPzZI_H
3152 1478672091U, // CMPGT_PPzZI_S
3153 1478573787U, // CMPGT_PPzZZ_B
3154 1478606555U, // CMPGT_PPzZZ_D
3155 2963422939U, // CMPGT_PPzZZ_H
3156 1478672091U, // CMPGT_PPzZZ_S
3157 1478573787U, // CMPGT_WIDE_PPzZZ_B
3158 2963422939U, // CMPGT_WIDE_PPzZZ_H
3159 1478672091U, // CMPGT_WIDE_PPzZZ_S
3160 1478568224U, // CMPHI_PPzZI_B
3161 1478600992U, // CMPHI_PPzZI_D
3162 2963417376U, // CMPHI_PPzZI_H
3163 1478666528U, // CMPHI_PPzZI_S
3164 1478568224U, // CMPHI_PPzZZ_B
3165 1478600992U, // CMPHI_PPzZZ_D
3166 2963417376U, // CMPHI_PPzZZ_H
3167 1478666528U, // CMPHI_PPzZZ_S
3168 1478568224U, // CMPHI_WIDE_PPzZZ_B
3169 2963417376U, // CMPHI_WIDE_PPzZZ_H
3170 1478666528U, // CMPHI_WIDE_PPzZZ_S
3171 1478573535U, // CMPHS_PPzZI_B
3172 1478606303U, // CMPHS_PPzZI_D
3173 2963422687U, // CMPHS_PPzZI_H
3174 1478671839U, // CMPHS_PPzZI_S
3175 1478573535U, // CMPHS_PPzZZ_B
3176 1478606303U, // CMPHS_PPzZZ_D
3177 2963422687U, // CMPHS_PPzZZ_H
3178 1478671839U, // CMPHS_PPzZZ_S
3179 1478573535U, // CMPHS_WIDE_PPzZZ_B
3180 2963422687U, // CMPHS_WIDE_PPzZZ_H
3181 1478671839U, // CMPHS_WIDE_PPzZZ_S
3182 1478563575U, // CMPLE_PPzZI_B
3183 1478596343U, // CMPLE_PPzZI_D
3184 2963412727U, // CMPLE_PPzZI_H
3185 1478661879U, // CMPLE_PPzZI_S
3186 1478563575U, // CMPLE_WIDE_PPzZZ_B
3187 2963412727U, // CMPLE_WIDE_PPzZZ_H
3188 1478661879U, // CMPLE_WIDE_PPzZZ_S
3189 1478568952U, // CMPLO_PPzZI_B
3190 1478601720U, // CMPLO_PPzZI_D
3191 2963418104U, // CMPLO_PPzZI_H
3192 1478667256U, // CMPLO_PPzZI_S
3193 1478568952U, // CMPLO_WIDE_PPzZZ_B
3194 2963418104U, // CMPLO_WIDE_PPzZZ_H
3195 1478667256U, // CMPLO_WIDE_PPzZZ_S
3196 1478573569U, // CMPLS_PPzZI_B
3197 1478606337U, // CMPLS_PPzZI_D
3198 2963422721U, // CMPLS_PPzZI_H
3199 1478671873U, // CMPLS_PPzZI_S
3200 1478573569U, // CMPLS_WIDE_PPzZZ_B
3201 2963422721U, // CMPLS_WIDE_PPzZZ_H
3202 1478671873U, // CMPLS_WIDE_PPzZZ_S
3203 1478573990U, // CMPLT_PPzZI_B
3204 1478606758U, // CMPLT_PPzZI_D
3205 2963423142U, // CMPLT_PPzZI_H
3206 1478672294U, // CMPLT_PPzZI_S
3207 1478573990U, // CMPLT_WIDE_PPzZZ_B
3208 2963423142U, // CMPLT_WIDE_PPzZZ_H
3209 1478672294U, // CMPLT_WIDE_PPzZZ_S
3210 1478563598U, // CMPNE_PPzZI_B
3211 1478596366U, // CMPNE_PPzZI_D
3212 2963412750U, // CMPNE_PPzZI_H
3213 1478661902U, // CMPNE_PPzZI_S
3214 1478563598U, // CMPNE_PPzZZ_B
3215 1478596366U, // CMPNE_PPzZZ_D
3216 2963412750U, // CMPNE_PPzZZ_H
3217 1478661902U, // CMPNE_PPzZZ_S
3218 1478563598U, // CMPNE_WIDE_PPzZZ_B
3219 2963412750U, // CMPNE_WIDE_PPzZZ_H
3220 1478661902U, // CMPNE_WIDE_PPzZZ_S
3221 270730762U, // CMTSTv16i8
3222 404799652U, // CMTSTv1i64
3223 270742480U, // CMTSTv2i32
3224 270734545U, // CMTSTv2i64
3225 270736757U, // CMTSTv4i16
3226 270744559U, // CMTSTv4i32
3227 270738653U, // CMTSTv8i16
3228 270731712U, // CMTSTv8i8
3229 2179193U, // CNOT_ZPmZ_B
3230 2211961U, // CNOT_ZPmZ_D
3231 138559609U, // CNOT_ZPmZ_H
3232 2277497U, // CNOT_ZPmZ_S
3233 3089141307U, // CNTB_XPiI
3234 3089143469U, // CNTD_XPiI
3235 3089148101U, // CNTH_XPiI
3236 1478536358U, // CNTP_XPP_B
3237 1478536358U, // CNTP_XPP_D
3238 1478536358U, // CNTP_XPP_H
3239 1478536358U, // CNTP_XPP_S
3240 3089154705U, // CNTW_XPiI
3241 2179035U, // CNT_ZPmZ_B
3242 2211803U, // CNT_ZPmZ_D
3243 138559451U, // CNT_ZPmZ_H
3244 2277339U, // CNT_ZPmZ_S
3245 270730744U, // CNTv16i8
3246 270731696U, // CNTv8i8
3247 1478606505U, // COMPACT_ZPZ_D
3248 1478672041U, // COMPACT_ZPZ_S
3249 2179886U, // CPY_ZPmI_B
3250 2212654U, // CPY_ZPmI_D
3251 3225568046U, // CPY_ZPmI_H
3252 2278190U, // CPY_ZPmI_S
3253 2179886U, // CPY_ZPmR_B
3254 2212654U, // CPY_ZPmR_D
3255 3359785774U, // CPY_ZPmR_H
3256 2278190U, // CPY_ZPmR_S
3257 2179886U, // CPY_ZPmV_B
3258 2212654U, // CPY_ZPmV_D
3259 3359785774U, // CPY_ZPmV_H
3260 2278190U, // CPY_ZPmV_S
3261 1478574894U, // CPY_ZPzI_B
3262 1478607662U, // CPY_ZPzI_D
3263 2963424046U, // CPY_ZPzI_H
3264 1478673198U, // CPY_ZPzI_S
3265 270582136U, // CPYi16
3266 270582136U, // CPYi32
3267 270582136U, // CPYi64
3268 270582136U, // CPYi8
3269 404783643U, // CRC32Brr
3270 404785836U, // CRC32CBrr
3271 404792968U, // CRC32CHrr
3272 404799984U, // CRC32CWrr
3273 404800230U, // CRC32CXrr
3274 404789418U, // CRC32Hrr
3275 404799940U, // CRC32Wrr
3276 404800169U, // CRC32Xrr
3277 404793848U, // CSELWr
3278 404793848U, // CSELXr
3279 404786947U, // CSINCWr
3280 404786947U, // CSINCXr
3281 404799856U, // CSINVWr
3282 404799856U, // CSINVXr
3283 404789145U, // CSNEGWr
3284 404789145U, // CSNEGXr
3285 404794639U, // CTERMEQ_WW
3286 404794639U, // CTERMEQ_XX
3287 404788997U, // CTERMNE_WW
3288 404788997U, // CTERMNE_XX
3289 426017U, // DCPS1
3290 426106U, // DCPS2
3291 426129U, // DCPS3
3292 3491793591U, // DECB_XPiI
3293 3491796487U, // DECD_XPiI
3294 3491862023U, // DECD_ZPiI
3295 3491800723U, // DECH_XPiI
3296 21112467U, // DECH_ZPiI
3297 1746971662U, // DECP_XP_B
3298 1075883022U, // DECP_XP_D
3299 807447566U, // DECP_XP_H
3300 1881189390U, // DECP_XP_S
3301 539077646U, // DECP_ZP_D
3302 2166500366U, // DECP_ZP_H
3303 673360910U, // DECP_ZP_S
3304 3491807739U, // DECW_XPiI
3305 3491938811U, // DECW_ZPiI
3306 593039U, // DMB
3307 17797U, // DRPS
3308 593381U, // DSB
3309 626149U, // DSBnXS
3310 3626085149U, // DUPM_ZI
3311 3760270522U, // DUP_ZI_B
3312 3894521018U, // DUP_ZI_D
3313 23211194U, // DUP_ZI_H
3314 4028804282U, // DUP_ZI_S
3315 404827322U, // DUP_ZR_B
3316 404860090U, // DUP_ZR_D
3317 2172791994U, // DUP_ZR_H
3318 404925626U, // DUP_ZR_S
3319 1747004602U, // DUP_ZZI_B
3320 1075948730U, // DUP_ZZI_D
3321 4173475002U, // DUP_ZZI_H
3322 4188679354U, // DUP_ZZI_Q
3323 1881320634U, // DUP_ZZI_S
3324 404948302U, // DUPv16i8gpr
3325 270730574U, // DUPv16i8lane
3326 404959951U, // DUPv2i32gpr
3327 270742223U, // DUPv2i32lane
3328 404952044U, // DUPv2i64gpr
3329 270734316U, // DUPv2i64lane
3330 404954228U, // DUPv4i16gpr
3331 270736500U, // DUPv4i16lane
3332 404962030U, // DUPv4i32gpr
3333 270744302U, // DUPv4i32lane
3334 404956124U, // DUPv8i16gpr
3335 270738396U, // DUPv8i16lane
3336 404949271U, // DUPv8i8gpr
3337 270731543U, // DUPv8i8lane
3338 404794210U, // EONWrs
3339 404794210U, // EONXrs
3340 270730030U, // EOR3
3341 1075937419U, // EOR3_ZZZZ
3342 2820751010U, // EORBT_ZZZ_B
3343 539082402U, // EORBT_ZZZ_D
3344 958545570U, // EORBT_ZZZ_H
3345 673365666U, // EORBT_ZZZ_S
3346 1478573641U, // EORS_PPzPP
3347 2820738625U, // EORTB_ZZZ_B
3348 539070017U, // EORTB_ZZZ_D
3349 958533185U, // EORTB_ZZZ_H
3350 673353281U, // EORTB_ZZZ_S
3351 278909U, // EORV_VPZ_B
3352 2164572541U, // EORV_VPZ_D
3353 2166702461U, // EORV_VPZ_H
3354 2156249469U, // EORV_VPZ_S
3355 404794869U, // EORWri
3356 404794869U, // EORWrs
3357 404794869U, // EORXri
3358 404794869U, // EORXrs
3359 1478569461U, // EOR_PPzPP
3360 1075949045U, // EOR_ZI
3361 1478569461U, // EOR_ZPmZ_B
3362 1478602229U, // EOR_ZPmZ_D
3363 1621241333U, // EOR_ZPmZ_H
3364 1478667765U, // EOR_ZPmZ_S
3365 1075949045U, // EOR_ZZZ
3366 270730657U, // EORv16i8
3367 270731618U, // EORv8i8
3368 17802U, // ERET
3369 17683U, // ERETAA
3370 17710U, // ERETAB
3371 404794946U, // EXTRWrri
3372 404794946U, // EXTRXrri
3373 1747009747U, // EXT_ZZI
3374 2179283U, // EXT_ZZI_B
3375 270730773U, // EXTv16i8
3376 270731722U, // EXTv8i8
3377 404788716U, // FABD16
3378 404788716U, // FABD32
3379 404788716U, // FABD64
3380 1478596076U, // FABD_ZPmZ_D
3381 1621235180U, // FABD_ZPmZ_H
3382 1478661612U, // FABD_ZPmZ_S
3383 270741490U, // FABDv2f32
3384 270733680U, // FABDv2f64
3385 270735779U, // FABDv4f16
3386 270743456U, // FABDv4f32
3387 270737640U, // FABDv8f16
3388 404798855U, // FABSDr
3389 404798855U, // FABSHr
3390 404798855U, // FABSSr
3391 2211207U, // FABS_ZPmZ_D
3392 138558855U, // FABS_ZPmZ_H
3393 2276743U, // FABS_ZPmZ_S
3394 270742328U, // FABSv2f32
3395 270734401U, // FABSv2f64
3396 270736605U, // FABSv4f16
3397 270744407U, // FABSv4f32
3398 270738501U, // FABSv8f16
3399 404788929U, // FACGE16
3400 404788929U, // FACGE32
3401 404788929U, // FACGE64
3402 1478596289U, // FACGE_PPzZZ_D
3403 2963412673U, // FACGE_PPzZZ_H
3404 1478661825U, // FACGE_PPzZZ_S
3405 270741600U, // FACGEv2f32
3406 270733730U, // FACGEv2f64
3407 270735889U, // FACGEv4f16
3408 270743575U, // FACGEv4f32
3409 270737750U, // FACGEv8f16
3410 404799172U, // FACGT16
3411 404799172U, // FACGT32
3412 404799172U, // FACGT64
3413 1478606532U, // FACGT_PPzZZ_D
3414 2963422916U, // FACGT_PPzZZ_H
3415 1478672068U, // FACGT_PPzZZ_S
3416 270742440U, // FACGTv2f32
3417 270734505U, // FACGTv2f64
3418 270736717U, // FACGTv4f16
3419 270744519U, // FACGTv4f32
3420 270738613U, // FACGTv8f16
3421 29655261U, // FADDA_VPZ_D
3422 31785181U, // FADDA_VPZ_H
3423 33915101U, // FADDA_VPZ_S
3424 404788795U, // FADDDrr
3425 404788795U, // FADDHrr
3426 1478601772U, // FADDP_ZPmZZ_D
3427 1621240876U, // FADDP_ZPmZZ_H
3428 1478667308U, // FADDP_ZPmZZ_S
3429 270742104U, // FADDPv2f32
3430 270734217U, // FADDPv2f64
3431 270571636U, // FADDPv2i16p
3432 270578264U, // FADDPv2i32p
3433 270570377U, // FADDPv2i64p
3434 270736381U, // FADDPv4f16
3435 270744183U, // FADDPv4f32
3436 270738277U, // FADDPv8f16
3437 404788795U, // FADDSrr
3438 2164572439U, // FADDV_VPZ_D
3439 2166702359U, // FADDV_VPZ_H
3440 2156249367U, // FADDV_VPZ_S
3441 1478596155U, // FADD_ZPmI_D
3442 1621235259U, // FADD_ZPmI_H
3443 1478661691U, // FADD_ZPmI_S
3444 1478596155U, // FADD_ZPmZ_D
3445 1621235259U, // FADD_ZPmZ_H
3446 1478661691U, // FADD_ZPmZ_S
3447 1075942971U, // FADD_ZZZ_D
3448 952243771U, // FADD_ZZZ_H
3449 1881314875U, // FADD_ZZZ_S
3450 270741527U, // FADDv2f32
3451 270733699U, // FADDv2f64
3452 270735816U, // FADDv4f16
3453 270743493U, // FADDv4f32
3454 270737677U, // FADDv8f16
3455 1478596133U, // FCADD_ZPmZ_D
3456 1621235237U, // FCADD_ZPmZ_H
3457 1478661669U, // FCADD_ZPmZ_S
3458 270741517U, // FCADDv2f32
3459 270733689U, // FCADDv2f64
3460 270735806U, // FCADDv4f16
3461 270743483U, // FCADDv4f32
3462 270737667U, // FCADDv8f16
3463 404794452U, // FCCMPDrr
3464 404789029U, // FCCMPEDrr
3465 404789029U, // FCCMPEHrr
3466 404789029U, // FCCMPESrr
3467 404794452U, // FCCMPHrr
3468 404794452U, // FCCMPSrr
3469 404794632U, // FCMEQ16
3470 404794632U, // FCMEQ32
3471 404794632U, // FCMEQ64
3472 1478601992U, // FCMEQ_PPzZ0_D
3473 2963418376U, // FCMEQ_PPzZ0_H
3474 1478667528U, // FCMEQ_PPzZ0_S
3475 1478601992U, // FCMEQ_PPzZZ_D
3476 2963418376U, // FCMEQ_PPzZZ_H
3477 1478667528U, // FCMEQ_PPzZZ_S
3478 404794632U, // FCMEQv1i16rz
3479 404794632U, // FCMEQv1i32rz
3480 404794632U, // FCMEQv1i64rz
3481 270742261U, // FCMEQv2f32
3482 270734334U, // FCMEQv2f64
3483 270742261U, // FCMEQv2i32rz
3484 270734334U, // FCMEQv2i64rz
3485 270736538U, // FCMEQv4f16
3486 270744340U, // FCMEQv4f32
3487 270736538U, // FCMEQv4i16rz
3488 270744340U, // FCMEQv4i32rz
3489 270738434U, // FCMEQv8f16
3490 270738434U, // FCMEQv8i16rz
3491 404788945U, // FCMGE16
3492 404788945U, // FCMGE32
3493 404788945U, // FCMGE64
3494 1478596305U, // FCMGE_PPzZ0_D
3495 2963412689U, // FCMGE_PPzZ0_H
3496 1478661841U, // FCMGE_PPzZ0_S
3497 1478596305U, // FCMGE_PPzZZ_D
3498 2963412689U, // FCMGE_PPzZZ_H
3499 1478661841U, // FCMGE_PPzZZ_S
3500 404788945U, // FCMGEv1i16rz
3501 404788945U, // FCMGEv1i32rz
3502 404788945U, // FCMGEv1i64rz
3503 270741610U, // FCMGEv2f32
3504 270733740U, // FCMGEv2f64
3505 270741610U, // FCMGEv2i32rz
3506 270733740U, // FCMGEv2i64rz
3507 270735899U, // FCMGEv4f16
3508 270743585U, // FCMGEv4f32
3509 270735899U, // FCMGEv4i16rz
3510 270743585U, // FCMGEv4i32rz
3511 270737760U, // FCMGEv8f16
3512 270737760U, // FCMGEv8i16rz
3513 404799188U, // FCMGT16
3514 404799188U, // FCMGT32
3515 404799188U, // FCMGT64
3516 1478606548U, // FCMGT_PPzZ0_D
3517 2963422932U, // FCMGT_PPzZ0_H
3518 1478672084U, // FCMGT_PPzZ0_S
3519 1478606548U, // FCMGT_PPzZZ_D
3520 2963422932U, // FCMGT_PPzZZ_H
3521 1478672084U, // FCMGT_PPzZZ_S
3522 404799188U, // FCMGTv1i16rz
3523 404799188U, // FCMGTv1i32rz
3524 404799188U, // FCMGTv1i64rz
3525 270742450U, // FCMGTv2f32
3526 270734515U, // FCMGTv2f64
3527 270742450U, // FCMGTv2i32rz
3528 270734515U, // FCMGTv2i64rz
3529 270736727U, // FCMGTv4f16
3530 270744529U, // FCMGTv4f32
3531 270736727U, // FCMGTv4i16rz
3532 270744529U, // FCMGTv4i32rz
3533 270738623U, // FCMGTv8f16
3534 270738623U, // FCMGTv8i16rz
3535 1478590726U, // FCMLA_ZPmZZ_D
3536 1621229830U, // FCMLA_ZPmZZ_H
3537 1478656262U, // FCMLA_ZPmZZ_S
3538 958529798U, // FCMLA_ZZZI_H
3539 673349894U, // FCMLA_ZZZI_S
3540 1344515957U, // FCMLAv2f32
3541 1344508175U, // FCMLAv2f64
3542 1344510246U, // FCMLAv4f16
3543 1344510246U, // FCMLAv4f16_indexed
3544 1344517889U, // FCMLAv4f32
3545 1344517889U, // FCMLAv4f32_indexed
3546 1344512107U, // FCMLAv8f16
3547 1344512107U, // FCMLAv8f16_indexed
3548 1478596336U, // FCMLE_PPzZ0_D
3549 2963412720U, // FCMLE_PPzZ0_H
3550 1478661872U, // FCMLE_PPzZ0_S
3551 404788976U, // FCMLEv1i16rz
3552 404788976U, // FCMLEv1i32rz
3553 404788976U, // FCMLEv1i64rz
3554 270741620U, // FCMLEv2i32rz
3555 270733750U, // FCMLEv2i64rz
3556 270735909U, // FCMLEv4i16rz
3557 270743595U, // FCMLEv4i32rz
3558 270737770U, // FCMLEv8i16rz
3559 1478606751U, // FCMLT_PPzZ0_D
3560 2963423135U, // FCMLT_PPzZ0_H
3561 1478672287U, // FCMLT_PPzZ0_S
3562 404799391U, // FCMLTv1i16rz
3563 404799391U, // FCMLTv1i32rz
3564 404799391U, // FCMLTv1i64rz
3565 270742460U, // FCMLTv2i32rz
3566 270734525U, // FCMLTv2i64rz
3567 270736737U, // FCMLTv4i16rz
3568 270744539U, // FCMLTv4i32rz
3569 270738633U, // FCMLTv8i16rz
3570 1478596350U, // FCMNE_PPzZ0_D
3571 2963412734U, // FCMNE_PPzZ0_H
3572 1478661886U, // FCMNE_PPzZ0_S
3573 1478596350U, // FCMNE_PPzZZ_D
3574 2963412734U, // FCMNE_PPzZZ_H
3575 1478661886U, // FCMNE_PPzZZ_S
3576 35695707U, // FCMPDri
3577 404794459U, // FCMPDrr
3578 35690285U, // FCMPEDri
3579 404789037U, // FCMPEDrr
3580 35690285U, // FCMPEHri
3581 404789037U, // FCMPEHrr
3582 35690285U, // FCMPESri
3583 404789037U, // FCMPESrr
3584 35695707U, // FCMPHri
3585 404794459U, // FCMPHrr
3586 35695707U, // FCMPSri
3587 404794459U, // FCMPSrr
3588 1478601727U, // FCMUO_PPzZZ_D
3589 2963418111U, // FCMUO_PPzZZ_H
3590 1478667263U, // FCMUO_PPzZZ_S
3591 2212653U, // FCPY_ZPmI_D
3592 138560301U, // FCPY_ZPmI_H
3593 2278189U, // FCPY_ZPmI_S
3594 404793847U, // FCSELDrrr
3595 404793847U, // FCSELHrrr
3596 404793847U, // FCSELSrrr
3597 404798847U, // FCVTASUWDr
3598 404798847U, // FCVTASUWHr
3599 404798847U, // FCVTASUWSr
3600 404798847U, // FCVTASUXDr
3601 404798847U, // FCVTASUXHr
3602 404798847U, // FCVTASUXSr
3603 404798847U, // FCVTASv1f16
3604 404798847U, // FCVTASv1i32
3605 404798847U, // FCVTASv1i64
3606 270742317U, // FCVTASv2f32
3607 270734390U, // FCVTASv2f64
3608 270736594U, // FCVTASv4f16
3609 270744396U, // FCVTASv4f32
3610 270738490U, // FCVTASv8f16
3611 404799711U, // FCVTAUUWDr
3612 404799711U, // FCVTAUUWHr
3613 404799711U, // FCVTAUUWSr
3614 404799711U, // FCVTAUUXDr
3615 404799711U, // FCVTAUUXHr
3616 404799711U, // FCVTAUUXSr
3617 404799711U, // FCVTAUv1f16
3618 404799711U, // FCVTAUv1i32
3619 404799711U, // FCVTAUv1i64
3620 270742490U, // FCVTAUv2f32
3621 270734555U, // FCVTAUv2f64
3622 270736767U, // FCVTAUv4f16
3623 270744569U, // FCVTAUv4f32
3624 270738663U, // FCVTAUv8f16
3625 404799660U, // FCVTDHr
3626 404799660U, // FCVTDSr
3627 404799660U, // FCVTHDr
3628 404799660U, // FCVTHSr
3629 2277327U, // FCVTLT_ZPmZ_HtoS
3630 2211791U, // FCVTLT_ZPmZ_StoD
3631 306391719U, // FCVTLv2i32
3632 308488871U, // FCVTLv4i16
3633 440598607U, // FCVTLv4i32
3634 308478031U, // FCVTLv8i16
3635 404798984U, // FCVTMSUWDr
3636 404798984U, // FCVTMSUWHr
3637 404798984U, // FCVTMSUWSr
3638 404798984U, // FCVTMSUXDr
3639 404798984U, // FCVTMSUXHr
3640 404798984U, // FCVTMSUXSr
3641 404798984U, // FCVTMSv1f16
3642 404798984U, // FCVTMSv1i32
3643 404798984U, // FCVTMSv1i64
3644 270742373U, // FCVTMSv2f32
3645 270734438U, // FCVTMSv2f64
3646 270736650U, // FCVTMSv4f16
3647 270744452U, // FCVTMSv4f32
3648 270738546U, // FCVTMSv8f16
3649 404799727U, // FCVTMUUWDr
3650 404799727U, // FCVTMUUWHr
3651 404799727U, // FCVTMUUWSr
3652 404799727U, // FCVTMUUXDr
3653 404799727U, // FCVTMUUXHr
3654 404799727U, // FCVTMUUXSr
3655 404799727U, // FCVTMUv1f16
3656 404799727U, // FCVTMUv1i32
3657 404799727U, // FCVTMUv1i64
3658 270742512U, // FCVTMUv2f32
3659 270734577U, // FCVTMUv2f64
3660 270736789U, // FCVTMUv4f16
3661 270744591U, // FCVTMUv4f32
3662 270738685U, // FCVTMUv8f16
3663 404799005U, // FCVTNSUWDr
3664 404799005U, // FCVTNSUWHr
3665 404799005U, // FCVTNSUWSr
3666 404799005U, // FCVTNSUXDr
3667 404799005U, // FCVTNSUXHr
3668 404799005U, // FCVTNSUXSr
3669 404799005U, // FCVTNSv1f16
3670 404799005U, // FCVTNSv1i32
3671 404799005U, // FCVTNSv1i64
3672 270742384U, // FCVTNSv2f32
3673 270734449U, // FCVTNSv2f64
3674 270736661U, // FCVTNSv4f16
3675 270744463U, // FCVTNSv4f32
3676 270738557U, // FCVTNSv8f16
3677 2277407U, // FCVTNT_ZPmZ_DtoS
3678 2286043167U, // FCVTNT_ZPmZ_StoH
3679 404799735U, // FCVTNUUWDr
3680 404799735U, // FCVTNUUWHr
3681 404799735U, // FCVTNUUWSr
3682 404799735U, // FCVTNUUXDr
3683 404799735U, // FCVTNUUXHr
3684 404799735U, // FCVTNUUXSr
3685 404799735U, // FCVTNUv1f16
3686 404799735U, // FCVTNUv1i32
3687 404799735U, // FCVTNUv1i64
3688 270742523U, // FCVTNUv2f32
3689 270734588U, // FCVTNUv2f64
3690 270736800U, // FCVTNUv4f16
3691 270744602U, // FCVTNUv4f32
3692 270738696U, // FCVTNUv8f16
3693 42150806U, // FCVTNv2i32
3694 44247958U, // FCVTNv4i16
3695 1382252637U, // FCVTNv4i32
3696 46366813U, // FCVTNv8i16
3697 404799028U, // FCVTPSUWDr
3698 404799028U, // FCVTPSUWHr
3699 404799028U, // FCVTPSUWSr
3700 404799028U, // FCVTPSUXDr
3701 404799028U, // FCVTPSUXHr
3702 404799028U, // FCVTPSUXSr
3703 404799028U, // FCVTPSv1f16
3704 404799028U, // FCVTPSv1i32
3705 404799028U, // FCVTPSv1i64
3706 270742406U, // FCVTPSv2f32
3707 270734471U, // FCVTPSv2f64
3708 270736683U, // FCVTPSv4f16
3709 270744485U, // FCVTPSv4f32
3710 270738579U, // FCVTPSv8f16
3711 404799743U, // FCVTPUUWDr
3712 404799743U, // FCVTPUUWHr
3713 404799743U, // FCVTPUUWSr
3714 404799743U, // FCVTPUUXDr
3715 404799743U, // FCVTPUUXHr
3716 404799743U, // FCVTPUUXSr
3717 404799743U, // FCVTPUv1f16
3718 404799743U, // FCVTPUv1i32
3719 404799743U, // FCVTPUv1i64
3720 270742534U, // FCVTPUv2f32
3721 270734599U, // FCVTPUv2f64
3722 270736811U, // FCVTPUv4f16
3723 270744613U, // FCVTPUv4f32
3724 270738707U, // FCVTPUv8f16
3725 404799660U, // FCVTSDr
3726 404799660U, // FCVTSHr
3727 2277461U, // FCVTXNT_ZPmZ_DtoS
3728 404794316U, // FCVTXNv1i64
3729 42150860U, // FCVTXNv2f32
3730 1382252645U, // FCVTXNv4f32
3731 2278173U, // FCVTX_ZPmZ_DtoS
3732 404799081U, // FCVTZSSWDri
3733 404799081U, // FCVTZSSWHri
3734 404799081U, // FCVTZSSWSri
3735 404799081U, // FCVTZSSXDri
3736 404799081U, // FCVTZSSXHri
3737 404799081U, // FCVTZSSXSri
3738 404799081U, // FCVTZSUWDr
3739 404799081U, // FCVTZSUWHr
3740 404799081U, // FCVTZSUWSr
3741 404799081U, // FCVTZSUXDr
3742 404799081U, // FCVTZSUXHr
3743 404799081U, // FCVTZSUXSr
3744 2211433U, // FCVTZS_ZPmZ_DtoD
3745 2276969U, // FCVTZS_ZPmZ_DtoS
3746 2211433U, // FCVTZS_ZPmZ_HtoD
3747 138559081U, // FCVTZS_ZPmZ_HtoH
3748 2276969U, // FCVTZS_ZPmZ_HtoS
3749 2211433U, // FCVTZS_ZPmZ_StoD
3750 2276969U, // FCVTZS_ZPmZ_StoS
3751 404799081U, // FCVTZSd
3752 404799081U, // FCVTZSh
3753 404799081U, // FCVTZSs
3754 404799081U, // FCVTZSv1f16
3755 404799081U, // FCVTZSv1i32
3756 404799081U, // FCVTZSv1i64
3757 270742429U, // FCVTZSv2f32
3758 270734494U, // FCVTZSv2f64
3759 270742429U, // FCVTZSv2i32_shift
3760 270734494U, // FCVTZSv2i64_shift
3761 270736706U, // FCVTZSv4f16
3762 270744508U, // FCVTZSv4f32
3763 270736706U, // FCVTZSv4i16_shift
3764 270744508U, // FCVTZSv4i32_shift
3765 270738602U, // FCVTZSv8f16
3766 270738602U, // FCVTZSv8i16_shift
3767 404799751U, // FCVTZUSWDri
3768 404799751U, // FCVTZUSWHri
3769 404799751U, // FCVTZUSWSri
3770 404799751U, // FCVTZUSXDri
3771 404799751U, // FCVTZUSXHri
3772 404799751U, // FCVTZUSXSri
3773 404799751U, // FCVTZUUWDr
3774 404799751U, // FCVTZUUWHr
3775 404799751U, // FCVTZUUWSr
3776 404799751U, // FCVTZUUXDr
3777 404799751U, // FCVTZUUXHr
3778 404799751U, // FCVTZUUXSr
3779 2212103U, // FCVTZU_ZPmZ_DtoD
3780 2277639U, // FCVTZU_ZPmZ_DtoS
3781 2212103U, // FCVTZU_ZPmZ_HtoD
3782 138559751U, // FCVTZU_ZPmZ_HtoH
3783 2277639U, // FCVTZU_ZPmZ_HtoS
3784 2212103U, // FCVTZU_ZPmZ_StoD
3785 2277639U, // FCVTZU_ZPmZ_StoS
3786 404799751U, // FCVTZUd
3787 404799751U, // FCVTZUh
3788 404799751U, // FCVTZUs
3789 404799751U, // FCVTZUv1f16
3790 404799751U, // FCVTZUv1i32
3791 404799751U, // FCVTZUv1i64
3792 270742545U, // FCVTZUv2f32
3793 270734610U, // FCVTZUv2f64
3794 270742545U, // FCVTZUv2i32_shift
3795 270734610U, // FCVTZUv2i64_shift
3796 270736822U, // FCVTZUv4f16
3797 270744624U, // FCVTZUv4f32
3798 270736822U, // FCVTZUv4i16_shift
3799 270744624U, // FCVTZUv4i32_shift
3800 270738718U, // FCVTZUv8f16
3801 270738718U, // FCVTZUv8i16_shift
3802 541212844U, // FCVT_ZPmZ_DtoH
3803 2277548U, // FCVT_ZPmZ_DtoS
3804 2212012U, // FCVT_ZPmZ_HtoD
3805 2277548U, // FCVT_ZPmZ_HtoS
3806 2212012U, // FCVT_ZPmZ_StoD
3807 2286043308U, // FCVT_ZPmZ_StoH
3808 404799799U, // FDIVDrr
3809 404799799U, // FDIVHrr
3810 1478602339U, // FDIVR_ZPmZ_D
3811 1621241443U, // FDIVR_ZPmZ_H
3812 1478667875U, // FDIVR_ZPmZ_S
3813 404799799U, // FDIVSrr
3814 1478607159U, // FDIV_ZPmZ_D
3815 1621246263U, // FDIV_ZPmZ_H
3816 1478672695U, // FDIV_ZPmZ_S
3817 270742556U, // FDIVv2f32
3818 270734621U, // FDIVv2f64
3819 270736842U, // FDIVv4f16
3820 270744644U, // FDIVv4f32
3821 270738738U, // FDIVv8f16
3822 673295545U, // FDUP_ZI_D
3823 48377017U, // FDUP_ZI_H
3824 673361081U, // FDUP_ZI_S
3825 1075937623U, // FEXPA_ZZ_D
3826 2160197975U, // FEXPA_ZZ_H
3827 1881309527U, // FEXPA_ZZ_S
3828 404799089U, // FJCVTZS
3829 2198257U, // FLOGB_ZPmZ_D
3830 138545905U, // FLOGB_ZPmZ_H
3831 2263793U, // FLOGB_ZPmZ_S
3832 404788831U, // FMADDDrrr
3833 404788831U, // FMADDHrrr
3834 404788831U, // FMADDSrrr
3835 1478596056U, // FMAD_ZPmZZ_D
3836 1621235160U, // FMAD_ZPmZZ_H
3837 1478661592U, // FMAD_ZPmZZ_S
3838 404800203U, // FMAXDrr
3839 404800203U, // FMAXHrr
3840 404794133U, // FMAXNMDrr
3841 404794133U, // FMAXNMHrr
3842 1478601834U, // FMAXNMP_ZPmZZ_D
3843 1621240938U, // FMAXNMP_ZPmZZ_H
3844 1478667370U, // FMAXNMP_ZPmZZ_S
3845 270742170U, // FMAXNMPv2f32
3846 270734283U, // FMAXNMPv2f64
3847 270571658U, // FMAXNMPv2i16p
3848 270578330U, // FMAXNMPv2i32p
3849 270570443U, // FMAXNMPv2i64p
3850 270736447U, // FMAXNMPv4f16
3851 270744249U, // FMAXNMPv4f32
3852 270738343U, // FMAXNMPv8f16
3853 404794133U, // FMAXNMSrr
3854 2164572498U, // FMAXNMV_VPZ_D
3855 2166702418U, // FMAXNMV_VPZ_H
3856 2156249426U, // FMAXNMV_VPZ_S
3857 270573045U, // FMAXNMVv4i16v
3858 270580847U, // FMAXNMVv4i32v
3859 270574941U, // FMAXNMVv8i16v
3860 1478601493U, // FMAXNM_ZPmI_D
3861 1621240597U, // FMAXNM_ZPmI_H
3862 1478667029U, // FMAXNM_ZPmI_S
3863 1478601493U, // FMAXNM_ZPmZ_D
3864 1621240597U, // FMAXNM_ZPmZ_H
3865 1478667029U, // FMAXNM_ZPmZ_S
3866 270741920U, // FMAXNMv2f32
3867 270734175U, // FMAXNMv2f64
3868 270736186U, // FMAXNMv4f16
3869 270744113U, // FMAXNMv4f32
3870 270738217U, // FMAXNMv8f16
3871 1478601931U, // FMAXP_ZPmZZ_D
3872 1621241035U, // FMAXP_ZPmZZ_H
3873 1478667467U, // FMAXP_ZPmZZ_S
3874 270742231U, // FMAXPv2f32
3875 270734324U, // FMAXPv2f64
3876 270571680U, // FMAXPv2i16p
3877 270578391U, // FMAXPv2i32p
3878 270570484U, // FMAXPv2i64p
3879 270736508U, // FMAXPv4f16
3880 270744310U, // FMAXPv4f32
3881 270738404U, // FMAXPv8f16
3882 404800203U, // FMAXSrr
3883 2164572547U, // FMAXV_VPZ_D
3884 2166702467U, // FMAXV_VPZ_H
3885 2156249475U, // FMAXV_VPZ_S
3886 270573096U, // FMAXVv4i16v
3887 270580898U, // FMAXVv4i32v
3888 270574992U, // FMAXVv8i16v
3889 1478607563U, // FMAX_ZPmI_D
3890 1621246667U, // FMAX_ZPmI_H
3891 1478673099U, // FMAX_ZPmI_S
3892 1478607563U, // FMAX_ZPmZ_D
3893 1621246667U, // FMAX_ZPmZ_H
3894 1478673099U, // FMAX_ZPmZ_S
3895 270742600U, // FMAXv2f32
3896 270734705U, // FMAXv2f64
3897 270736966U, // FMAXv4f16
3898 270744834U, // FMAXv4f32
3899 270738902U, // FMAXv8f16
3900 404794176U, // FMINDrr
3901 404794176U, // FMINHrr
3902 404794125U, // FMINNMDrr
3903 404794125U, // FMINNMHrr
3904 1478601825U, // FMINNMP_ZPmZZ_D
3905 1621240929U, // FMINNMP_ZPmZZ_H
3906 1478667361U, // FMINNMP_ZPmZZ_S
3907 270742158U, // FMINNMPv2f32
3908 270734271U, // FMINNMPv2f64
3909 270571646U, // FMINNMPv2i16p
3910 270578318U, // FMINNMPv2i32p
3911 270570431U, // FMINNMPv2i64p
3912 270736435U, // FMINNMPv4f16
3913 270744237U, // FMINNMPv4f32
3914 270738331U, // FMINNMPv8f16
3915 404794125U, // FMINNMSrr
3916 2164572489U, // FMINNMV_VPZ_D
3917 2166702409U, // FMINNMV_VPZ_H
3918 2156249417U, // FMINNMV_VPZ_S
3919 270573033U, // FMINNMVv4i16v
3920 270580835U, // FMINNMVv4i32v
3921 270574929U, // FMINNMVv8i16v
3922 1478601485U, // FMINNM_ZPmI_D
3923 1621240589U, // FMINNM_ZPmI_H
3924 1478667021U, // FMINNM_ZPmI_S
3925 1478601485U, // FMINNM_ZPmZ_D
3926 1621240589U, // FMINNM_ZPmZ_H
3927 1478667021U, // FMINNM_ZPmZ_S
3928 270741909U, // FMINNMv2f32
3929 270734164U, // FMINNMv2f64
3930 270736175U, // FMINNMv4f16
3931 270744102U, // FMINNMv4f32
3932 270738206U, // FMINNMv8f16
3933 1478601849U, // FMINP_ZPmZZ_D
3934 1621240953U, // FMINP_ZPmZZ_H
3935 1478667385U, // FMINP_ZPmZZ_S
3936 270742182U, // FMINPv2f32
3937 270734295U, // FMINPv2f64
3938 270571670U, // FMINPv2i16p
3939 270578342U, // FMINPv2i32p
3940 270570455U, // FMINPv2i64p
3941 270736459U, // FMINPv4f16
3942 270744261U, // FMINPv4f32
3943 270738355U, // FMINPv8f16
3944 404794176U, // FMINSrr
3945 2164572507U, // FMINV_VPZ_D
3946 2166702427U, // FMINV_VPZ_H
3947 2156249435U, // FMINV_VPZ_S
3948 270573057U, // FMINVv4i16v
3949 270580859U, // FMINVv4i32v
3950 270574953U, // FMINVv8i16v
3951 1478601536U, // FMIN_ZPmI_D
3952 1621240640U, // FMIN_ZPmI_H
3953 1478667072U, // FMIN_ZPmI_S
3954 1478601536U, // FMIN_ZPmZ_D
3955 1621240640U, // FMIN_ZPmZ_H
3956 1478667072U, // FMIN_ZPmZ_S
3957 270741964U, // FMINv2f32
3958 270734197U, // FMINv2f64
3959 270736230U, // FMINv4f16
3960 270744135U, // FMINv4f32
3961 270738239U, // FMINv8f16
3962 1344503871U, // FMLAL2lanev4f16
3963 1344503871U, // FMLAL2lanev8f16
3964 17495U, // FMLAL2v4f16
3965 17495U, // FMLAL2v8f16
3966 1210223409U, // FMLALB_ZZZI_SHH
3967 1210223409U, // FMLALB_ZZZ_SHH
3968 1210236681U, // FMLALT_ZZZI_SHH
3969 1210236681U, // FMLALT_ZZZ_SHH
3970 1344514401U, // FMLALlanev4f16
3971 1344514401U, // FMLALlanev8f16
3972 17755U, // FMLALv4f16
3973 17755U, // FMLALv8f16
3974 1478590733U, // FMLA_ZPmZZ_D
3975 1621229837U, // FMLA_ZPmZZ_H
3976 1478656269U, // FMLA_ZPmZZ_S
3977 539066637U, // FMLA_ZZZI_D
3978 958529805U, // FMLA_ZZZI_H
3979 673349901U, // FMLA_ZZZI_S
3980 2418513849U, // FMLAv1i16_indexed
3981 2418519707U, // FMLAv1i32_indexed
3982 2418511636U, // FMLAv1i64_indexed
3983 1344515967U, // FMLAv2f32
3984 1344508185U, // FMLAv2f64
3985 1344515967U, // FMLAv2i32_indexed
3986 1344508185U, // FMLAv2i64_indexed
3987 1344510256U, // FMLAv4f16
3988 1344517899U, // FMLAv4f32
3989 1344510256U, // FMLAv4i16_indexed
3990 1344517899U, // FMLAv4i32_indexed
3991 1344512117U, // FMLAv8f16
3992 1344512117U, // FMLAv8i16_indexed
3993 1344503879U, // FMLSL2lanev4f16
3994 1344503879U, // FMLSL2lanev8f16
3995 17502U, // FMLSL2v4f16
3996 17502U, // FMLSL2v8f16
3997 1210223706U, // FMLSLB_ZZZI_SHH
3998 1210223706U, // FMLSLB_ZZZ_SHH
3999 1210236855U, // FMLSLT_ZZZI_SHH
4000 1210236855U, // FMLSLT_ZZZ_SHH
4001 1344514706U, // FMLSLlanev4f16
4002 1344514706U, // FMLSLlanev8f16
4003 17784U, // FMLSLv4f16
4004 17784U, // FMLSLv8f16
4005 1478606324U, // FMLS_ZPmZZ_D
4006 1621245428U, // FMLS_ZPmZZ_H
4007 1478671860U, // FMLS_ZPmZZ_S
4008 539082228U, // FMLS_ZZZI_D
4009 958545396U, // FMLS_ZZZI_H
4010 673365492U, // FMLS_ZZZI_S
4011 2418513945U, // FMLSv1i16_indexed
4012 2418519803U, // FMLSv1i32_indexed
4013 2418511652U, // FMLSv1i64_indexed
4014 1344516956U, // FMLSv2f32
4015 1344509021U, // FMLSv2f64
4016 1344516956U, // FMLSv2i32_indexed
4017 1344509021U, // FMLSv2i64_indexed
4018 1344511233U, // FMLSv4f16
4019 1344519035U, // FMLSv4f32
4020 1344511233U, // FMLSv4i16_indexed
4021 1344519035U, // FMLSv4i32_indexed
4022 1344513129U, // FMLSv8f16
4023 1344513129U, // FMLSv8i16_indexed
4024 539066644U, // FMMLA_ZZZ_D
4025 673349908U, // FMMLA_ZZZ_S
4026 270569267U, // FMOVDXHighr
4027 404799863U, // FMOVDXr
4028 673235319U, // FMOVDi
4029 404799863U, // FMOVDr
4030 404799863U, // FMOVHWr
4031 404799863U, // FMOVHXr
4032 673235319U, // FMOVHi
4033 404799863U, // FMOVHr
4034 404799863U, // FMOVSWr
4035 673235319U, // FMOVSi
4036 404799863U, // FMOVSr
4037 404799863U, // FMOVWHr
4038 404799863U, // FMOVWSr
4039 453185331U, // FMOVXDHighr
4040 404799863U, // FMOVXDr
4041 404799863U, // FMOVXHr
4042 673395749U, // FMOVv2f32_ns
4043 673387814U, // FMOVv2f64_ns
4044 673390111U, // FMOVv4f16_ns
4045 673397913U, // FMOVv4f32_ns
4046 673392007U, // FMOVv8f16_ns
4047 1478594031U, // FMSB_ZPmZZ_D
4048 1621233135U, // FMSB_ZPmZZ_H
4049 1478659567U, // FMSB_ZPmZZ_S
4050 404786800U, // FMSUBDrrr
4051 404786800U, // FMSUBHrrr
4052 404786800U, // FMSUBSrrr
4053 404794030U, // FMULDrr
4054 404794030U, // FMULHrr
4055 404794030U, // FMULSrr
4056 404800262U, // FMULX16
4057 404800262U, // FMULX32
4058 404800262U, // FMULX64
4059 1478607622U, // FMULX_ZPmZ_D
4060 1621246726U, // FMULX_ZPmZ_H
4061 1478673158U, // FMULX_ZPmZ_S
4062 404789304U, // FMULXv1i16_indexed
4063 404795162U, // FMULXv1i32_indexed
4064 404787011U, // FMULXv1i64_indexed
4065 270742627U, // FMULXv2f32
4066 270734714U, // FMULXv2f64
4067 270742627U, // FMULXv2i32_indexed
4068 270734714U, // FMULXv2i64_indexed
4069 270736993U, // FMULXv4f16
4070 270744861U, // FMULXv4f32
4071 270736993U, // FMULXv4i16_indexed
4072 270744861U, // FMULXv4i32_indexed
4073 270738929U, // FMULXv8f16
4074 270738929U, // FMULXv8i16_indexed
4075 1478601390U, // FMUL_ZPmI_D
4076 1621240494U, // FMUL_ZPmI_H
4077 1478666926U, // FMUL_ZPmI_S
4078 1478601390U, // FMUL_ZPmZ_D
4079 1621240494U, // FMUL_ZPmZ_H
4080 1478666926U, // FMUL_ZPmZ_S
4081 1075948206U, // FMUL_ZZZI_D
4082 952249006U, // FMUL_ZZZI_H
4083 1881320110U, // FMUL_ZZZI_S
4084 1075948206U, // FMUL_ZZZ_D
4085 952249006U, // FMUL_ZZZ_H
4086 1881320110U, // FMUL_ZZZ_S
4087 404789265U, // FMULv1i16_indexed
4088 404795123U, // FMULv1i32_indexed
4089 404786972U, // FMULv1i64_indexed
4090 270741900U, // FMULv2f32
4091 270734155U, // FMULv2f64
4092 270741900U, // FMULv2i32_indexed
4093 270734155U, // FMULv2i64_indexed
4094 270736166U, // FMULv4f16
4095 270744083U, // FMULv4f32
4096 270736166U, // FMULv4i16_indexed
4097 270744083U, // FMULv4i32_indexed
4098 270738197U, // FMULv8f16
4099 270738197U, // FMULv8i16_indexed
4100 404789132U, // FNEGDr
4101 404789132U, // FNEGHr
4102 404789132U, // FNEGSr
4103 2201484U, // FNEG_ZPmZ_D
4104 138549132U, // FNEG_ZPmZ_H
4105 2267020U, // FNEG_ZPmZ_S
4106 270741696U, // FNEGv2f32
4107 270733803U, // FNEGv2f64
4108 270735962U, // FNEGv4f16
4109 270743671U, // FNEGv4f32
4110 270737823U, // FNEGv8f16
4111 404788838U, // FNMADDDrrr
4112 404788838U, // FNMADDHrrr
4113 404788838U, // FNMADDSrrr
4114 1478596062U, // FNMAD_ZPmZZ_D
4115 1621235166U, // FNMAD_ZPmZZ_H
4116 1478661598U, // FNMAD_ZPmZZ_S
4117 1478590762U, // FNMLA_ZPmZZ_D
4118 1621229866U, // FNMLA_ZPmZZ_H
4119 1478656298U, // FNMLA_ZPmZZ_S
4120 1478606330U, // FNMLS_ZPmZZ_D
4121 1621245434U, // FNMLS_ZPmZZ_H
4122 1478671866U, // FNMLS_ZPmZZ_S
4123 1478594037U, // FNMSB_ZPmZZ_D
4124 1621233141U, // FNMSB_ZPmZZ_H
4125 1478659573U, // FNMSB_ZPmZZ_S
4126 404786807U, // FNMSUBDrrr
4127 404786807U, // FNMSUBHrrr
4128 404786807U, // FNMSUBSrrr
4129 404794036U, // FNMULDrr
4130 404794036U, // FNMULHrr
4131 404794036U, // FNMULSrr
4132 1075943189U, // FRECPE_ZZ_D
4133 2160203541U, // FRECPE_ZZ_H
4134 1881315093U, // FRECPE_ZZ_S
4135 404789013U, // FRECPEv1f16
4136 404789013U, // FRECPEv1i32
4137 404789013U, // FRECPEv1i64
4138 270741630U, // FRECPEv2f32
4139 270733760U, // FRECPEv2f64
4140 270735919U, // FRECPEv4f16
4141 270743605U, // FRECPEv4f32
4142 270737780U, // FRECPEv8f16
4143 404799020U, // FRECPS16
4144 404799020U, // FRECPS32
4145 404799020U, // FRECPS64
4146 1075953196U, // FRECPS_ZZZ_D
4147 952253996U, // FRECPS_ZZZ_H
4148 1881325100U, // FRECPS_ZZZ_S
4149 270742395U, // FRECPSv2f32
4150 270734460U, // FRECPSv2f64
4151 270736672U, // FRECPSv4f16
4152 270744474U, // FRECPSv4f32
4153 270738568U, // FRECPSv8f16
4154 2212621U, // FRECPX_ZPmZ_D
4155 138560269U, // FRECPX_ZPmZ_H
4156 2278157U, // FRECPX_ZPmZ_S
4157 404800269U, // FRECPXv1f16
4158 404800269U, // FRECPXv1i32
4159 404800269U, // FRECPXv1i64
4160 404800177U, // FRINT32XDr
4161 404800177U, // FRINT32XSr
4162 270742574U, // FRINT32Xv2f32
4163 270734679U, // FRINT32Xv2f64
4164 270744808U, // FRINT32Xv4f32
4165 404800307U, // FRINT32ZDr
4166 404800307U, // FRINT32ZSr
4167 270742648U, // FRINT32Zv2f32
4168 270734735U, // FRINT32Zv2f64
4169 270744894U, // FRINT32Zv4f32
4170 404800187U, // FRINT64XDr
4171 404800187U, // FRINT64XSr
4172 270742587U, // FRINT64Xv2f32
4173 270734692U, // FRINT64Xv2f64
4174 270744821U, // FRINT64Xv4f32
4175 404800317U, // FRINT64ZDr
4176 404800317U, // FRINT64ZSr
4177 270742661U, // FRINT64Zv2f32
4178 270734748U, // FRINT64Zv2f64
4179 270744907U, // FRINT64Zv4f32
4180 404783510U, // FRINTADr
4181 404783510U, // FRINTAHr
4182 404783510U, // FRINTASr
4183 2195862U, // FRINTA_ZPmZ_D
4184 138543510U, // FRINTA_ZPmZ_H
4185 2261398U, // FRINTA_ZPmZ_S
4186 270741422U, // FRINTAv2f32
4187 270733640U, // FRINTAv2f64
4188 270735711U, // FRINTAv4f16
4189 270743354U, // FRINTAv4f32
4190 270737572U, // FRINTAv8f16
4191 404793654U, // FRINTIDr
4192 404793654U, // FRINTIHr
4193 404793654U, // FRINTISr
4194 2206006U, // FRINTI_ZPmZ_D
4195 138553654U, // FRINTI_ZPmZ_H
4196 2271542U, // FRINTI_ZPmZ_S
4197 270741800U, // FRINTIv2f32
4198 270733859U, // FRINTIv2f64
4199 270736066U, // FRINTIv4f16
4200 270743787U, // FRINTIv4f32
4201 270737927U, // FRINTIv8f16
4202 404794147U, // FRINTMDr
4203 404794147U, // FRINTMHr
4204 404794147U, // FRINTMSr
4205 2206499U, // FRINTM_ZPmZ_D
4206 138554147U, // FRINTM_ZPmZ_H
4207 2272035U, // FRINTM_ZPmZ_S
4208 270741931U, // FRINTMv2f32
4209 270734186U, // FRINTMv2f64
4210 270736197U, // FRINTMv4f16
4211 270744124U, // FRINTMv4f32
4212 270738228U, // FRINTMv8f16
4213 404794254U, // FRINTNDr
4214 404794254U, // FRINTNHr
4215 404794254U, // FRINTNSr
4216 2206606U, // FRINTN_ZPmZ_D
4217 138554254U, // FRINTN_ZPmZ_H
4218 2272142U, // FRINTN_ZPmZ_S
4219 270742037U, // FRINTNv2f32
4220 270734206U, // FRINTNv2f64
4221 270736303U, // FRINTNv4f16
4222 270744162U, // FRINTNv4f32
4223 270738266U, // FRINTNv8f16
4224 404794540U, // FRINTPDr
4225 404794540U, // FRINTPHr
4226 404794540U, // FRINTPSr
4227 2206892U, // FRINTP_ZPmZ_D
4228 138554540U, // FRINTP_ZPmZ_H
4229 2272428U, // FRINTP_ZPmZ_S
4230 270742212U, // FRINTPv2f32
4231 270734305U, // FRINTPv2f64
4232 270736489U, // FRINTPv4f16
4233 270744291U, // FRINTPv4f32
4234 270738385U, // FRINTPv8f16
4235 404800277U, // FRINTXDr
4236 404800277U, // FRINTXHr
4237 404800277U, // FRINTXSr
4238 2212629U, // FRINTX_ZPmZ_D
4239 138560277U, // FRINTX_ZPmZ_H
4240 2278165U, // FRINTX_ZPmZ_S
4241 270742637U, // FRINTXv2f32
4242 270734724U, // FRINTXv2f64
4243 270737003U, // FRINTXv4f16
4244 270744871U, // FRINTXv4f32
4245 270738939U, // FRINTXv8f16
4246 404800384U, // FRINTZDr
4247 404800384U, // FRINTZHr
4248 404800384U, // FRINTZSr
4249 2212736U, // FRINTZ_ZPmZ_D
4250 138560384U, // FRINTZ_ZPmZ_H
4251 2278272U, // FRINTZ_ZPmZ_S
4252 270742682U, // FRINTZv2f32
4253 270734761U, // FRINTZv2f64
4254 270737022U, // FRINTZv4f16
4255 270744928U, // FRINTZv4f32
4256 270738958U, // FRINTZv8f16
4257 1075943234U, // FRSQRTE_ZZ_D
4258 2160203586U, // FRSQRTE_ZZ_H
4259 1881315138U, // FRSQRTE_ZZ_S
4260 404789058U, // FRSQRTEv1f16
4261 404789058U, // FRSQRTEv1i32
4262 404789058U, // FRSQRTEv1i64
4263 270741652U, // FRSQRTEv2f32
4264 270733771U, // FRSQRTEv2f64
4265 270735930U, // FRSQRTEv4f16
4266 270743627U, // FRSQRTEv4f32
4267 270737791U, // FRSQRTEv8f16
4268 404799067U, // FRSQRTS16
4269 404799067U, // FRSQRTS32
4270 404799067U, // FRSQRTS64
4271 1075953243U, // FRSQRTS_ZZZ_D
4272 952254043U, // FRSQRTS_ZZZ_H
4273 1881325147U, // FRSQRTS_ZZZ_S
4274 270742417U, // FRSQRTSv2f32
4275 270734482U, // FRSQRTSv2f64
4276 270736694U, // FRSQRTSv4f16
4277 270744496U, // FRSQRTSv4f32
4278 270738590U, // FRSQRTSv8f16
4279 1478596319U, // FSCALE_ZPmZ_D
4280 1621235423U, // FSCALE_ZPmZ_H
4281 1478661855U, // FSCALE_ZPmZ_S
4282 404799623U, // FSQRTDr
4283 404799623U, // FSQRTHr
4284 404799623U, // FSQRTSr
4285 2211975U, // FSQRT_ZPmZ_D
4286 138559623U, // FSQRT_ZPmZ_H
4287 2277511U, // FSQRT_ZPmZ_S
4288 270742470U, // FSQRTv2f32
4289 270734535U, // FSQRTv2f64
4290 270736747U, // FSQRTv4f16
4291 270744549U, // FSQRTv4f32
4292 270738643U, // FSQRTv8f16
4293 404786780U, // FSUBDrr
4294 404786780U, // FSUBHrr
4295 1478602057U, // FSUBR_ZPmI_D
4296 1621241161U, // FSUBR_ZPmI_H
4297 1478667593U, // FSUBR_ZPmI_S
4298 1478602057U, // FSUBR_ZPmZ_D
4299 1621241161U, // FSUBR_ZPmZ_H
4300 1478667593U, // FSUBR_ZPmZ_S
4301 404786780U, // FSUBSrr
4302 1478594140U, // FSUB_ZPmI_D
4303 1621233244U, // FSUB_ZPmI_H
4304 1478659676U, // FSUB_ZPmI_S
4305 1478594140U, // FSUB_ZPmZ_D
4306 1621233244U, // FSUB_ZPmZ_H
4307 1478659676U, // FSUB_ZPmZ_S
4308 1075940956U, // FSUB_ZZZ_D
4309 952241756U, // FSUB_ZZZ_H
4310 1881312860U, // FSUB_ZZZ_S
4311 270741433U, // FSUBv2f32
4312 270733651U, // FSUBv2f64
4313 270735722U, // FSUBv4f16
4314 270743389U, // FSUBv4f32
4315 270737583U, // FSUBv8f16
4316 1075942885U, // FTMAD_ZZI_D
4317 952243685U, // FTMAD_ZZI_H
4318 1881314789U, // FTMAD_ZZI_S
4319 1075948225U, // FTSMUL_ZZZ_D
4320 952249025U, // FTSMUL_ZZZ_H
4321 1881320129U, // FTSMUL_ZZZ_S
4322 1075948030U, // FTSSEL_ZZZ_D
4323 952248830U, // FTSSEL_ZZZ_H
4324 1881319934U, // FTSSEL_ZZZ_S
4325 589988335U, // GLD1B_D_IMM_REAL
4326 2469036527U, // GLD1B_D_REAL
4327 2469036527U, // GLD1B_D_SXTW_REAL
4328 2469036527U, // GLD1B_D_UXTW_REAL
4329 724238831U, // GLD1B_S_IMM_REAL
4330 2469069295U, // GLD1B_S_SXTW_REAL
4331 2469069295U, // GLD1B_S_UXTW_REAL
4332 589991800U, // GLD1D_IMM_REAL
4333 2469039992U, // GLD1D_REAL
4334 2469039992U, // GLD1D_SCALED_REAL
4335 2469039992U, // GLD1D_SXTW_REAL
4336 2469039992U, // GLD1D_SXTW_SCALED_REAL
4337 2469039992U, // GLD1D_UXTW_REAL
4338 2469039992U, // GLD1D_UXTW_SCALED_REAL
4339 589994056U, // GLD1H_D_IMM_REAL
4340 2469042248U, // GLD1H_D_REAL
4341 2469042248U, // GLD1H_D_SCALED_REAL
4342 2469042248U, // GLD1H_D_SXTW_REAL
4343 2469042248U, // GLD1H_D_SXTW_SCALED_REAL
4344 2469042248U, // GLD1H_D_UXTW_REAL
4345 2469042248U, // GLD1H_D_UXTW_SCALED_REAL
4346 724244552U, // GLD1H_S_IMM_REAL
4347 2469075016U, // GLD1H_S_SXTW_REAL
4348 2469075016U, // GLD1H_S_SXTW_SCALED_REAL
4349 2469075016U, // GLD1H_S_UXTW_REAL
4350 2469075016U, // GLD1H_S_UXTW_SCALED_REAL
4351 589991357U, // GLD1SB_D_IMM_REAL
4352 2469039549U, // GLD1SB_D_REAL
4353 2469039549U, // GLD1SB_D_SXTW_REAL
4354 2469039549U, // GLD1SB_D_UXTW_REAL
4355 724241853U, // GLD1SB_S_IMM_REAL
4356 2469072317U, // GLD1SB_S_SXTW_REAL
4357 2469072317U, // GLD1SB_S_UXTW_REAL
4358 589998178U, // GLD1SH_D_IMM_REAL
4359 2469046370U, // GLD1SH_D_REAL
4360 2469046370U, // GLD1SH_D_SCALED_REAL
4361 2469046370U, // GLD1SH_D_SXTW_REAL
4362 2469046370U, // GLD1SH_D_SXTW_SCALED_REAL
4363 2469046370U, // GLD1SH_D_UXTW_REAL
4364 2469046370U, // GLD1SH_D_UXTW_SCALED_REAL
4365 724248674U, // GLD1SH_S_IMM_REAL
4366 2469079138U, // GLD1SH_S_SXTW_REAL
4367 2469079138U, // GLD1SH_S_SXTW_SCALED_REAL
4368 2469079138U, // GLD1SH_S_UXTW_REAL
4369 2469079138U, // GLD1SH_S_UXTW_SCALED_REAL
4370 590004799U, // GLD1SW_D_IMM_REAL
4371 2469052991U, // GLD1SW_D_REAL
4372 2469052991U, // GLD1SW_D_SCALED_REAL
4373 2469052991U, // GLD1SW_D_SXTW_REAL
4374 2469052991U, // GLD1SW_D_SXTW_SCALED_REAL
4375 2469052991U, // GLD1SW_D_UXTW_REAL
4376 2469052991U, // GLD1SW_D_UXTW_SCALED_REAL
4377 590004632U, // GLD1W_D_IMM_REAL
4378 2469052824U, // GLD1W_D_REAL
4379 2469052824U, // GLD1W_D_SCALED_REAL
4380 2469052824U, // GLD1W_D_SXTW_REAL
4381 2469052824U, // GLD1W_D_SXTW_SCALED_REAL
4382 2469052824U, // GLD1W_D_UXTW_REAL
4383 2469052824U, // GLD1W_D_UXTW_SCALED_REAL
4384 724255128U, // GLD1W_IMM_REAL
4385 2469085592U, // GLD1W_SXTW_REAL
4386 2469085592U, // GLD1W_SXTW_SCALED_REAL
4387 2469085592U, // GLD1W_UXTW_REAL
4388 2469085592U, // GLD1W_UXTW_SCALED_REAL
4389 589988341U, // GLDFF1B_D_IMM_REAL
4390 2469036533U, // GLDFF1B_D_REAL
4391 2469036533U, // GLDFF1B_D_SXTW_REAL
4392 2469036533U, // GLDFF1B_D_UXTW_REAL
4393 724238837U, // GLDFF1B_S_IMM_REAL
4394 2469069301U, // GLDFF1B_S_SXTW_REAL
4395 2469069301U, // GLDFF1B_S_UXTW_REAL
4396 589991806U, // GLDFF1D_IMM_REAL
4397 2469039998U, // GLDFF1D_REAL
4398 2469039998U, // GLDFF1D_SCALED_REAL
4399 2469039998U, // GLDFF1D_SXTW_REAL
4400 2469039998U, // GLDFF1D_SXTW_SCALED_REAL
4401 2469039998U, // GLDFF1D_UXTW_REAL
4402 2469039998U, // GLDFF1D_UXTW_SCALED_REAL
4403 589994062U, // GLDFF1H_D_IMM_REAL
4404 2469042254U, // GLDFF1H_D_REAL
4405 2469042254U, // GLDFF1H_D_SCALED_REAL
4406 2469042254U, // GLDFF1H_D_SXTW_REAL
4407 2469042254U, // GLDFF1H_D_SXTW_SCALED_REAL
4408 2469042254U, // GLDFF1H_D_UXTW_REAL
4409 2469042254U, // GLDFF1H_D_UXTW_SCALED_REAL
4410 724244558U, // GLDFF1H_S_IMM_REAL
4411 2469075022U, // GLDFF1H_S_SXTW_REAL
4412 2469075022U, // GLDFF1H_S_SXTW_SCALED_REAL
4413 2469075022U, // GLDFF1H_S_UXTW_REAL
4414 2469075022U, // GLDFF1H_S_UXTW_SCALED_REAL
4415 589991364U, // GLDFF1SB_D_IMM_REAL
4416 2469039556U, // GLDFF1SB_D_REAL
4417 2469039556U, // GLDFF1SB_D_SXTW_REAL
4418 2469039556U, // GLDFF1SB_D_UXTW_REAL
4419 724241860U, // GLDFF1SB_S_IMM_REAL
4420 2469072324U, // GLDFF1SB_S_SXTW_REAL
4421 2469072324U, // GLDFF1SB_S_UXTW_REAL
4422 589998185U, // GLDFF1SH_D_IMM_REAL
4423 2469046377U, // GLDFF1SH_D_REAL
4424 2469046377U, // GLDFF1SH_D_SCALED_REAL
4425 2469046377U, // GLDFF1SH_D_SXTW_REAL
4426 2469046377U, // GLDFF1SH_D_SXTW_SCALED_REAL
4427 2469046377U, // GLDFF1SH_D_UXTW_REAL
4428 2469046377U, // GLDFF1SH_D_UXTW_SCALED_REAL
4429 724248681U, // GLDFF1SH_S_IMM_REAL
4430 2469079145U, // GLDFF1SH_S_SXTW_REAL
4431 2469079145U, // GLDFF1SH_S_SXTW_SCALED_REAL
4432 2469079145U, // GLDFF1SH_S_UXTW_REAL
4433 2469079145U, // GLDFF1SH_S_UXTW_SCALED_REAL
4434 590004806U, // GLDFF1SW_D_IMM_REAL
4435 2469052998U, // GLDFF1SW_D_REAL
4436 2469052998U, // GLDFF1SW_D_SCALED_REAL
4437 2469052998U, // GLDFF1SW_D_SXTW_REAL
4438 2469052998U, // GLDFF1SW_D_SXTW_SCALED_REAL
4439 2469052998U, // GLDFF1SW_D_UXTW_REAL
4440 2469052998U, // GLDFF1SW_D_UXTW_SCALED_REAL
4441 590004638U, // GLDFF1W_D_IMM_REAL
4442 2469052830U, // GLDFF1W_D_REAL
4443 2469052830U, // GLDFF1W_D_SCALED_REAL
4444 2469052830U, // GLDFF1W_D_SXTW_REAL
4445 2469052830U, // GLDFF1W_D_SXTW_SCALED_REAL
4446 2469052830U, // GLDFF1W_D_UXTW_REAL
4447 2469052830U, // GLDFF1W_D_UXTW_SCALED_REAL
4448 724255134U, // GLDFF1W_IMM_REAL
4449 2469085598U, // GLDFF1W_SXTW_REAL
4450 2469085598U, // GLDFF1W_SXTW_SCALED_REAL
4451 2469085598U, // GLDFF1W_UXTW_REAL
4452 2469085598U, // GLDFF1W_UXTW_SCALED_REAL
4453 404793644U, // GMI
4454 770034U, // HINT
4455 1478606807U, // HISTCNT_ZPzZZ_D
4456 1478672343U, // HISTCNT_ZPzZZ_S
4457 1746999200U, // HISTSEG_ZZZ
4458 442216U, // HLT
4459 429834U, // HVC
4460 3491793607U, // INCB_XPiI
4461 3491796503U, // INCD_XPiI
4462 3491862039U, // INCD_ZPiI
4463 3491800739U, // INCH_XPiI
4464 21112483U, // INCH_ZPiI
4465 1746971678U, // INCP_XP_B
4466 1075883038U, // INCP_XP_D
4467 807447582U, // INCP_XP_H
4468 1881189406U, // INCP_XP_S
4469 539077662U, // INCP_ZP_D
4470 2166500382U, // INCP_ZP_H
4471 673360926U, // INCP_ZP_S
4472 3491807755U, // INCW_XPiI
4473 3491938827U, // INCW_ZPiI
4474 807486191U, // INDEX_II_B
4475 404865775U, // INDEX_II_D
4476 994198255U, // INDEX_II_H
4477 404931311U, // INDEX_II_S
4478 807486191U, // INDEX_IR_B
4479 404865775U, // INDEX_IR_D
4480 2470593263U, // INDEX_IR_H
4481 404931311U, // INDEX_IR_S
4482 404833007U, // INDEX_RI_B
4483 404865775U, // INDEX_RI_D
4484 964838127U, // INDEX_RI_H
4485 404931311U, // INDEX_RI_S
4486 404833007U, // INDEX_RR_B
4487 404865775U, // INDEX_RR_D
4488 964838127U, // INDEX_RR_H
4489 404931311U, // INDEX_RR_S
4490 2418093611U, // INSR_ZR_B
4491 2418126379U, // INSR_ZR_D
4492 2204249643U, // INSR_ZR_H
4493 2418191915U, // INSR_ZR_S
4494 2418093611U, // INSR_ZV_B
4495 2418126379U, // INSR_ZV_D
4496 2204249643U, // INSR_ZV_H
4497 2418191915U, // INSR_ZV_S
4498 3406010401U, // INSvi16gpr
4499 1124309025U, // INSvi16lane
4500 3406016259U, // INSvi32gpr
4501 1124314883U, // INSvi32lane
4502 3406008108U, // INSvi64gpr
4503 1124306732U, // INSvi64lane
4504 3406004696U, // INSvi8gpr
4505 1124303320U, // INSvi8lane
4506 404789161U, // IRG
4507 593386U, // ISB
4508 1478525343U, // LASTA_RPZ_B
4509 1478525343U, // LASTA_RPZ_D
4510 1478525343U, // LASTA_RPZ_H
4511 1478525343U, // LASTA_RPZ_S
4512 1478525343U, // LASTA_VPZ_B
4513 1478525343U, // LASTA_VPZ_D
4514 1478525343U, // LASTA_VPZ_H
4515 1478525343U, // LASTA_VPZ_S
4516 1478528585U, // LASTB_RPZ_B
4517 1478528585U, // LASTB_RPZ_D
4518 1478528585U, // LASTB_RPZ_H
4519 1478528585U, // LASTB_RPZ_S
4520 1478528585U, // LASTB_VPZ_B
4521 1478528585U, // LASTB_VPZ_D
4522 1478528585U, // LASTB_VPZ_H
4523 1478528585U, // LASTB_VPZ_S
4524 2469134831U, // LD1B
4525 2469036527U, // LD1B_D
4526 2469036527U, // LD1B_D_IMM_REAL
4527 2469167599U, // LD1B_H
4528 2469167599U, // LD1B_H_IMM_REAL
4529 2469134831U, // LD1B_IMM_REAL
4530 2469069295U, // LD1B_S
4531 2469069295U, // LD1B_S_IMM_REAL
4532 2469039992U, // LD1D
4533 2469039992U, // LD1D_IMM_REAL
4534 851978U, // LD1Fourv16b
4535 59605002U, // LD1Fourv16b_POST
4536 917514U, // LD1Fourv1d
4537 61767690U, // LD1Fourv1d_POST
4538 983050U, // LD1Fourv2d
4539 59736074U, // LD1Fourv2d_POST
4540 1048586U, // LD1Fourv2s
4541 61898762U, // LD1Fourv2s_POST
4542 1114122U, // LD1Fourv4h
4543 61964298U, // LD1Fourv4h_POST
4544 1179658U, // LD1Fourv4s
4545 59932682U, // LD1Fourv4s_POST
4546 1245194U, // LD1Fourv8b
4547 62095370U, // LD1Fourv8b_POST
4548 1310730U, // LD1Fourv8h
4549 60063754U, // LD1Fourv8h_POST
4550 2469173320U, // LD1H
4551 2469042248U, // LD1H_D
4552 2469042248U, // LD1H_D_IMM_REAL
4553 2469173320U, // LD1H_IMM_REAL
4554 2469075016U, // LD1H_S
4555 2469075016U, // LD1H_S_IMM_REAL
4556 851978U, // LD1Onev16b
4557 63799306U, // LD1Onev16b_POST
4558 917514U, // LD1Onev1d
4559 65961994U, // LD1Onev1d_POST
4560 983050U, // LD1Onev2d
4561 63930378U, // LD1Onev2d_POST
4562 1048586U, // LD1Onev2s
4563 66093066U, // LD1Onev2s_POST
4564 1114122U, // LD1Onev4h
4565 66158602U, // LD1Onev4h_POST
4566 1179658U, // LD1Onev4s
4567 64126986U, // LD1Onev4s_POST
4568 1245194U, // LD1Onev8b
4569 66289674U, // LD1Onev8b_POST
4570 1310730U, // LD1Onev8h
4571 64258058U, // LD1Onev8h_POST
4572 2469039401U, // LD1RB_D_IMM
4573 2469170473U, // LD1RB_H_IMM
4574 2469137705U, // LD1RB_IMM
4575 2469072169U, // LD1RB_S_IMM
4576 2469041818U, // LD1RD_IMM
4577 2469046222U, // LD1RH_D_IMM
4578 2469177294U, // LD1RH_IMM
4579 2469078990U, // LD1RH_S_IMM
4580 2469137676U, // LD1RO_B
4581 2469137676U, // LD1RO_B_IMM
4582 2469041802U, // LD1RO_D
4583 2469041802U, // LD1RO_D_IMM
4584 2469177272U, // LD1RO_H
4585 2469177272U, // LD1RO_H_IMM
4586 2469085727U, // LD1RO_W
4587 2469085727U, // LD1RO_W_IMM
4588 2469137697U, // LD1RQ_B
4589 2469137697U, // LD1RQ_B_IMM
4590 2469041810U, // LD1RQ_D
4591 2469041810U, // LD1RQ_D_IMM
4592 2469177286U, // LD1RQ_H
4593 2469177286U, // LD1RQ_H_IMM
4594 2469085735U, // LD1RQ_W
4595 2469085735U, // LD1RQ_W_IMM
4596 2469039612U, // LD1RSB_D_IMM
4597 2469170684U, // LD1RSB_H_IMM
4598 2469072380U, // LD1RSB_S_IMM
4599 2469046420U, // LD1RSH_D_IMM
4600 2469079188U, // LD1RSH_S_IMM
4601 2469053032U, // LD1RSW_IMM
4602 2469052975U, // LD1RW_D_IMM
4603 2469085743U, // LD1RW_IMM
4604 863519U, // LD1Rv16b
4605 68005151U, // LD1Rv16b_POST
4606 929055U, // LD1Rv1d
4607 65973535U, // LD1Rv1d_POST
4608 994591U, // LD1Rv2d
4609 66039071U, // LD1Rv2d_POST
4610 1060127U, // LD1Rv2s
4611 70298911U, // LD1Rv2s_POST
4612 1125663U, // LD1Rv4h
4613 72461599U, // LD1Rv4h_POST
4614 1191199U, // LD1Rv4s
4615 70429983U, // LD1Rv4s_POST
4616 1256735U, // LD1Rv8b
4617 68398367U, // LD1Rv8b_POST
4618 1322271U, // LD1Rv8h
4619 72658207U, // LD1Rv8h_POST
4620 2469039549U, // LD1SB_D
4621 2469039549U, // LD1SB_D_IMM_REAL
4622 2469170621U, // LD1SB_H
4623 2469170621U, // LD1SB_H_IMM_REAL
4624 2469072317U, // LD1SB_S
4625 2469072317U, // LD1SB_S_IMM_REAL
4626 2469046370U, // LD1SH_D
4627 2469046370U, // LD1SH_D_IMM_REAL
4628 2469079138U, // LD1SH_S
4629 2469079138U, // LD1SH_S_IMM_REAL
4630 2469052991U, // LD1SW_D
4631 2469052991U, // LD1SW_D_IMM_REAL
4632 851978U, // LD1Threev16b
4633 74285066U, // LD1Threev16b_POST
4634 917514U, // LD1Threev1d
4635 76447754U, // LD1Threev1d_POST
4636 983050U, // LD1Threev2d
4637 74416138U, // LD1Threev2d_POST
4638 1048586U, // LD1Threev2s
4639 76578826U, // LD1Threev2s_POST
4640 1114122U, // LD1Threev4h
4641 76644362U, // LD1Threev4h_POST
4642 1179658U, // LD1Threev4s
4643 74612746U, // LD1Threev4s_POST
4644 1245194U, // LD1Threev8b
4645 76775434U, // LD1Threev8b_POST
4646 1310730U, // LD1Threev8h
4647 74743818U, // LD1Threev8h_POST
4648 851978U, // LD1Twov16b
4649 61702154U, // LD1Twov16b_POST
4650 917514U, // LD1Twov1d
4651 63864842U, // LD1Twov1d_POST
4652 983050U, // LD1Twov2d
4653 61833226U, // LD1Twov2d_POST
4654 1048586U, // LD1Twov2s
4655 63995914U, // LD1Twov2s_POST
4656 1114122U, // LD1Twov4h
4657 64061450U, // LD1Twov4h_POST
4658 1179658U, // LD1Twov4s
4659 62029834U, // LD1Twov4s_POST
4660 1245194U, // LD1Twov8b
4661 64192522U, // LD1Twov8b_POST
4662 1310730U, // LD1Twov8h
4663 62160906U, // LD1Twov8h_POST
4664 2469085592U, // LD1W
4665 2469052824U, // LD1W_D
4666 2469052824U, // LD1W_D_IMM_REAL
4667 2469085592U, // LD1W_IMM_REAL
4668 78970890U, // LD1i16
4669 81100810U, // LD1i16_POST
4670 79036426U, // LD1i32
4671 83263498U, // LD1i32_POST
4672 79101962U, // LD1i64
4673 85426186U, // LD1i64_POST
4674 79167498U, // LD1i8
4675 87588874U, // LD1i8_POST
4676 2469134883U, // LD2B
4677 2469134883U, // LD2B_IMM
4678 2469041588U, // LD2D
4679 2469041588U, // LD2D_IMM
4680 2469173426U, // LD2H
4681 2469173426U, // LD2H_IMM
4682 863525U, // LD2Rv16b
4683 72199461U, // LD2Rv16b_POST
4684 929061U, // LD2Rv1d
4685 63876389U, // LD2Rv1d_POST
4686 994597U, // LD2Rv2d
4687 63941925U, // LD2Rv2d_POST
4688 1060133U, // LD2Rv2s
4689 66104613U, // LD2Rv2s_POST
4690 1125669U, // LD2Rv4h
4691 70364453U, // LD2Rv4h_POST
4692 1191205U, // LD2Rv4s
4693 66235685U, // LD2Rv4s_POST
4694 1256741U, // LD2Rv8b
4695 72592677U, // LD2Rv8b_POST
4696 1322277U, // LD2Rv8h
4697 70561061U, // LD2Rv8h_POST
4698 852026U, // LD2Twov16b
4699 61702202U, // LD2Twov16b_POST
4700 983098U, // LD2Twov2d
4701 61833274U, // LD2Twov2d_POST
4702 1048634U, // LD2Twov2s
4703 63995962U, // LD2Twov2s_POST
4704 1114170U, // LD2Twov4h
4705 64061498U, // LD2Twov4h_POST
4706 1179706U, // LD2Twov4s
4707 62029882U, // LD2Twov4s_POST
4708 1245242U, // LD2Twov8b
4709 64192570U, // LD2Twov8b_POST
4710 1310778U, // LD2Twov8h
4711 62160954U, // LD2Twov8h_POST
4712 2469085644U, // LD2W
4713 2469085644U, // LD2W_IMM
4714 78970938U, // LD2i16
4715 83198010U, // LD2i16_POST
4716 79036474U, // LD2i32
4717 85360698U, // LD2i32_POST
4718 79102010U, // LD2i64
4719 89620538U, // LD2i64_POST
4720 79167546U, // LD2i8
4721 81297466U, // LD2i8_POST
4722 2469134895U, // LD3B
4723 2469134895U, // LD3B_IMM
4724 2469041600U, // LD3D
4725 2469041600U, // LD3D_IMM
4726 2469173438U, // LD3H
4727 2469173438U, // LD3H_IMM
4728 863531U, // LD3Rv16b
4729 91073835U, // LD3Rv16b_POST
4730 929067U, // LD3Rv1d
4731 76459307U, // LD3Rv1d_POST
4732 994603U, // LD3Rv2d
4733 76524843U, // LD3Rv2d_POST
4734 1060139U, // LD3Rv2s
4735 93367595U, // LD3Rv2s_POST
4736 1125675U, // LD3Rv4h
4737 95530283U, // LD3Rv4h_POST
4738 1191211U, // LD3Rv4s
4739 93498667U, // LD3Rv4s_POST
4740 1256747U, // LD3Rv8b
4741 91467051U, // LD3Rv8b_POST
4742 1322283U, // LD3Rv8h
4743 95726891U, // LD3Rv8h_POST
4744 852102U, // LD3Threev16b
4745 74285190U, // LD3Threev16b_POST
4746 983174U, // LD3Threev2d
4747 74416262U, // LD3Threev2d_POST
4748 1048710U, // LD3Threev2s
4749 76578950U, // LD3Threev2s_POST
4750 1114246U, // LD3Threev4h
4751 76644486U, // LD3Threev4h_POST
4752 1179782U, // LD3Threev4s
4753 74612870U, // LD3Threev4s_POST
4754 1245318U, // LD3Threev8b
4755 76775558U, // LD3Threev8b_POST
4756 1310854U, // LD3Threev8h
4757 74743942U, // LD3Threev8h_POST
4758 2469085656U, // LD3W
4759 2469085656U, // LD3W_IMM
4760 78971014U, // LD3i16
4761 97878150U, // LD3i16_POST
4762 79036550U, // LD3i32
4763 100040838U, // LD3i32_POST
4764 79102086U, // LD3i64
4765 102203526U, // LD3i64_POST
4766 79167622U, // LD3i8
4767 104366214U, // LD3i8_POST
4768 2469134921U, // LD4B
4769 2469134921U, // LD4B_IMM
4770 2469041612U, // LD4D
4771 2469041612U, // LD4D_IMM
4772 852125U, // LD4Fourv16b
4773 59605149U, // LD4Fourv16b_POST
4774 983197U, // LD4Fourv2d
4775 59736221U, // LD4Fourv2d_POST
4776 1048733U, // LD4Fourv2s
4777 61898909U, // LD4Fourv2s_POST
4778 1114269U, // LD4Fourv4h
4779 61964445U, // LD4Fourv4h_POST
4780 1179805U, // LD4Fourv4s
4781 59932829U, // LD4Fourv4s_POST
4782 1245341U, // LD4Fourv8b
4783 62095517U, // LD4Fourv8b_POST
4784 1310877U, // LD4Fourv8h
4785 60063901U, // LD4Fourv8h_POST
4786 2469174921U, // LD4H
4787 2469174921U, // LD4H_IMM
4788 863537U, // LD4Rv16b
4789 70102321U, // LD4Rv16b_POST
4790 929073U, // LD4Rv1d
4791 61779249U, // LD4Rv1d_POST
4792 994609U, // LD4Rv2d
4793 61844785U, // LD4Rv2d_POST
4794 1060145U, // LD4Rv2s
4795 64007473U, // LD4Rv2s_POST
4796 1125681U, // LD4Rv4h
4797 66170161U, // LD4Rv4h_POST
4798 1191217U, // LD4Rv4s
4799 64138545U, // LD4Rv4s_POST
4800 1256753U, // LD4Rv8b
4801 70495537U, // LD4Rv8b_POST
4802 1322289U, // LD4Rv8h
4803 66366769U, // LD4Rv8h_POST
4804 2469085668U, // LD4W
4805 2469085668U, // LD4W_IMM
4806 78971037U, // LD4i16
4807 85295261U, // LD4i16_POST
4808 79036573U, // LD4i32
4809 89555101U, // LD4i32_POST
4810 79102109U, // LD4i64
4811 106397853U, // LD4i64_POST
4812 79167645U, // LD4i8
4813 83394717U, // LD4i8_POST
4814 1638971U, // LD64B
4815 1210550846U, // LDADDAB
4816 1210557977U, // LDADDAH
4817 1210551068U, // LDADDALB
4818 1210558151U, // LDADDALH
4819 1210558799U, // LDADDALW
4820 1210558799U, // LDADDALX
4821 1210548437U, // LDADDAW
4822 1210548437U, // LDADDAX
4823 1210551004U, // LDADDB
4824 1210558137U, // LDADDH
4825 1210551249U, // LDADDLB
4826 1210558251U, // LDADDLH
4827 1210558934U, // LDADDLW
4828 1210558934U, // LDADDLX
4829 1210553908U, // LDADDW
4830 1210553908U, // LDADDX
4831 417369444U, // LDAPRB
4832 417376265U, // LDAPRH
4833 417377796U, // LDAPRW
4834 417377796U, // LDAPRX
4835 417369487U, // LDAPURBi
4836 417376308U, // LDAPURHi
4837 417369627U, // LDAPURSBWi
4838 417369627U, // LDAPURSBXi
4839 417376435U, // LDAPURSHWi
4840 417376435U, // LDAPURSHXi
4841 417383047U, // LDAPURSWi
4842 417377877U, // LDAPURXi
4843 417377877U, // LDAPURi
4844 417369392U, // LDARB
4845 417376213U, // LDARH
4846 417377591U, // LDARW
4847 417377591U, // LDARX
4848 404794564U, // LDAXPW
4849 404794564U, // LDAXPX
4850 417369503U, // LDAXRB
4851 417376324U, // LDAXRH
4852 417377921U, // LDAXRW
4853 417377921U, // LDAXRX
4854 1210550902U, // LDCLRAB
4855 1210558034U, // LDCLRAH
4856 1210551143U, // LDCLRALB
4857 1210558191U, // LDCLRALH
4858 1210558859U, // LDCLRALW
4859 1210558859U, // LDCLRALX
4860 1210548574U, // LDCLRAW
4861 1210548574U, // LDCLRAX
4862 1210551621U, // LDCLRB
4863 1210558442U, // LDCLRH
4864 1210551351U, // LDCLRLB
4865 1210558287U, // LDCLRLH
4866 1210559085U, // LDCLRLW
4867 1210559085U, // LDCLRLX
4868 1210559911U, // LDCLRW
4869 1210559911U, // LDCLRX
4870 1210550911U, // LDEORAB
4871 1210558043U, // LDEORAH
4872 1210551153U, // LDEORALB
4873 1210558201U, // LDEORALH
4874 1210558868U, // LDEORALW
4875 1210558868U, // LDEORALX
4876 1210548582U, // LDEORAW
4877 1210548582U, // LDEORAX
4878 1210551644U, // LDEORB
4879 1210558465U, // LDEORH
4880 1210551360U, // LDEORLB
4881 1210558296U, // LDEORLH
4882 1210559093U, // LDEORLW
4883 1210559093U, // LDEORLX
4884 1210559987U, // LDEORW
4885 1210559987U, // LDEORX
4886 2469036533U, // LDFF1B_D_REAL
4887 2469167605U, // LDFF1B_H_REAL
4888 2469134837U, // LDFF1B_REAL
4889 2469069301U, // LDFF1B_S_REAL
4890 2469039998U, // LDFF1D_REAL
4891 2469042254U, // LDFF1H_D_REAL
4892 2469173326U, // LDFF1H_REAL
4893 2469075022U, // LDFF1H_S_REAL
4894 2469039556U, // LDFF1SB_D_REAL
4895 2469170628U, // LDFF1SB_H_REAL
4896 2469072324U, // LDFF1SB_S_REAL
4897 2469046377U, // LDFF1SH_D_REAL
4898 2469079145U, // LDFF1SH_S_REAL
4899 2469052998U, // LDFF1SW_D_REAL
4900 2469052830U, // LDFF1W_D_REAL
4901 2469085598U, // LDFF1W_REAL
4902 2431096711U, // LDG
4903 417377018U, // LDGM
4904 417369399U, // LDLARB
4905 417376220U, // LDLARH
4906 417377597U, // LDLARW
4907 417377597U, // LDLARX
4908 2469036541U, // LDNF1B_D_IMM_REAL
4909 2469167613U, // LDNF1B_H_IMM_REAL
4910 2469134845U, // LDNF1B_IMM_REAL
4911 2469069309U, // LDNF1B_S_IMM_REAL
4912 2469040006U, // LDNF1D_IMM_REAL
4913 2469042262U, // LDNF1H_D_IMM_REAL
4914 2469173334U, // LDNF1H_IMM_REAL
4915 2469075030U, // LDNF1H_S_IMM_REAL
4916 2469039565U, // LDNF1SB_D_IMM_REAL
4917 2469170637U, // LDNF1SB_H_IMM_REAL
4918 2469072333U, // LDNF1SB_S_IMM_REAL
4919 2469046386U, // LDNF1SH_D_IMM_REAL
4920 2469079154U, // LDNF1SH_S_IMM_REAL
4921 2469053007U, // LDNF1SW_D_IMM_REAL
4922 2469052838U, // LDNF1W_D_IMM_REAL
4923 2469085606U, // LDNF1W_IMM_REAL
4924 404794483U, // LDNPDi
4925 404794483U, // LDNPQi
4926 404794483U, // LDNPSi
4927 404794483U, // LDNPWi
4928 404794483U, // LDNPXi
4929 2469134853U, // LDNT1B_ZRI
4930 2469134853U, // LDNT1B_ZRR
4931 589988357U, // LDNT1B_ZZR_D_REAL
4932 724238853U, // LDNT1B_ZZR_S_REAL
4933 2469040014U, // LDNT1D_ZRI
4934 2469040014U, // LDNT1D_ZRR
4935 589991822U, // LDNT1D_ZZR_D_REAL
4936 2469173342U, // LDNT1H_ZRI
4937 2469173342U, // LDNT1H_ZRR
4938 589994078U, // LDNT1H_ZZR_D_REAL
4939 724244574U, // LDNT1H_ZZR_S_REAL
4940 589991382U, // LDNT1SB_ZZR_D_REAL
4941 724241878U, // LDNT1SB_ZZR_S_REAL
4942 589998203U, // LDNT1SH_ZZR_D_REAL
4943 724248699U, // LDNT1SH_ZZR_S_REAL
4944 590004824U, // LDNT1SW_ZZR_D_REAL
4945 2469085614U, // LDNT1W_ZRI
4946 2469085614U, // LDNT1W_ZRR
4947 590004654U, // LDNT1W_ZZR_D_REAL
4948 724255150U, // LDNT1W_ZZR_S_REAL
4949 404794419U, // LDPDi
4950 2418519091U, // LDPDpost
4951 2418519091U, // LDPDpre
4952 404794419U, // LDPQi
4953 2418519091U, // LDPQpost
4954 2418519091U, // LDPQpre
4955 404800097U, // LDPSWi
4956 2418524769U, // LDPSWpost
4957 2418524769U, // LDPSWpre
4958 404794419U, // LDPSi
4959 2418519091U, // LDPSpost
4960 2418519091U, // LDPSpre
4961 404794419U, // LDPWi
4962 2418519091U, // LDPWpost
4963 2418519091U, // LDPWpre
4964 404794419U, // LDPXi
4965 2418519091U, // LDPXpost
4966 2418519091U, // LDPXpre
4967 417366196U, // LDRAAindexed
4968 2431090868U, // LDRAAwriteback
4969 417368680U, // LDRABindexed
4970 2431093352U, // LDRABwriteback
4971 2431094079U, // LDRBBpost
4972 2431094079U, // LDRBBpre
4973 417369407U, // LDRBBroW
4974 417369407U, // LDRBBroX
4975 417369407U, // LDRBBui
4976 2431102325U, // LDRBpost
4977 2431102325U, // LDRBpre
4978 417377653U, // LDRBroW
4979 417377653U, // LDRBroX
4980 417377653U, // LDRBui
4981 2686496117U, // LDRDl
4982 2431102325U, // LDRDpost
4983 2431102325U, // LDRDpre
4984 417377653U, // LDRDroW
4985 417377653U, // LDRDroX
4986 417377653U, // LDRDui
4987 2431100900U, // LDRHHpost
4988 2431100900U, // LDRHHpre
4989 417376228U, // LDRHHroW
4990 417376228U, // LDRHHroX
4991 417376228U, // LDRHHui
4992 2431102325U, // LDRHpost
4993 2431102325U, // LDRHpre
4994 417377653U, // LDRHroW
4995 417377653U, // LDRHroX
4996 417377653U, // LDRHui
4997 2686496117U, // LDRQl
4998 2431102325U, // LDRQpost
4999 2431102325U, // LDRQpre
5000 417377653U, // LDRQroW
5001 417377653U, // LDRQroX
5002 417377653U, // LDRQui
5003 2431094276U, // LDRSBWpost
5004 2431094276U, // LDRSBWpre
5005 417369604U, // LDRSBWroW
5006 417369604U, // LDRSBWroX
5007 417369604U, // LDRSBWui
5008 2431094276U, // LDRSBXpost
5009 2431094276U, // LDRSBXpre
5010 417369604U, // LDRSBXroW
5011 417369604U, // LDRSBXroX
5012 417369604U, // LDRSBXui
5013 2431101084U, // LDRSHWpost
5014 2431101084U, // LDRSHWpre
5015 417376412U, // LDRSHWroW
5016 417376412U, // LDRSHWroX
5017 417376412U, // LDRSHWui
5018 2431101084U, // LDRSHXpost
5019 2431101084U, // LDRSHXpre
5020 417376412U, // LDRSHXroW
5021 417376412U, // LDRSHXroX
5022 417376412U, // LDRSHXui
5023 2686501488U, // LDRSWl
5024 2431107696U, // LDRSWpost
5025 2431107696U, // LDRSWpre
5026 417383024U, // LDRSWroW
5027 417383024U, // LDRSWroX
5028 417383024U, // LDRSWui
5029 2686496117U, // LDRSl
5030 2431102325U, // LDRSpost
5031 2431102325U, // LDRSpre
5032 417377653U, // LDRSroW
5033 417377653U, // LDRSroX
5034 417377653U, // LDRSui
5035 2686496117U, // LDRWl
5036 2431102325U, // LDRWpost
5037 2431102325U, // LDRWpre
5038 417377653U, // LDRWroW
5039 417377653U, // LDRWroX
5040 417377653U, // LDRWui
5041 2686496117U, // LDRXl
5042 2431102325U, // LDRXpost
5043 2431102325U, // LDRXpre
5044 417377653U, // LDRXroW
5045 417377653U, // LDRXroX
5046 417377653U, // LDRXui
5047 419016053U, // LDR_PXI
5048 419016053U, // LDR_ZXI
5049 1210550927U, // LDSETAB
5050 1210558059U, // LDSETAH
5051 1210551171U, // LDSETALB
5052 1210558219U, // LDSETALH
5053 1210558884U, // LDSETALW
5054 1210558884U, // LDSETALX
5055 1210548622U, // LDSETAW
5056 1210548622U, // LDSETAX
5057 1210551850U, // LDSETB
5058 1210558653U, // LDSETH
5059 1210551410U, // LDSETLB
5060 1210558312U, // LDSETLH
5061 1210559135U, // LDSETLW
5062 1210559135U, // LDSETLX
5063 1210564285U, // LDSETW
5064 1210564285U, // LDSETX
5065 1210550936U, // LDSMAXAB
5066 1210558068U, // LDSMAXAH
5067 1210551181U, // LDSMAXALB
5068 1210558229U, // LDSMAXALH
5069 1210558893U, // LDSMAXALW
5070 1210558893U, // LDSMAXALX
5071 1210548646U, // LDSMAXAW
5072 1210548646U, // LDSMAXAX
5073 1210551987U, // LDSMAXB
5074 1210558685U, // LDSMAXH
5075 1210551419U, // LDSMAXLB
5076 1210558354U, // LDSMAXLH
5077 1210559190U, // LDSMAXLW
5078 1210559190U, // LDSMAXLX
5079 1210565329U, // LDSMAXW
5080 1210565329U, // LDSMAXX
5081 1210550855U, // LDSMINAB
5082 1210558007U, // LDSMINAH
5083 1210551113U, // LDSMINALB
5084 1210558161U, // LDSMINALH
5085 1210558824U, // LDSMINALW
5086 1210558824U, // LDSMINALX
5087 1210548529U, // LDSMINAW
5088 1210548529U, // LDSMINAX
5089 1210551462U, // LDSMINB
5090 1210558374U, // LDSMINH
5091 1210551324U, // LDSMINLB
5092 1210558260U, // LDSMINLH
5093 1210559047U, // LDSMINLW
5094 1210559047U, // LDSMINLX
5095 1210559302U, // LDSMINW
5096 1210559302U, // LDSMINX
5097 417369452U, // LDTRBi
5098 417376273U, // LDTRHi
5099 417369611U, // LDTRSBWi
5100 417369611U, // LDTRSBXi
5101 417376419U, // LDTRSHWi
5102 417376419U, // LDTRSHXi
5103 417383031U, // LDTRSWi
5104 417377841U, // LDTRWi
5105 417377841U, // LDTRXi
5106 1210550946U, // LDUMAXAB
5107 1210558078U, // LDUMAXAH
5108 1210551192U, // LDUMAXALB
5109 1210558240U, // LDUMAXALH
5110 1210558903U, // LDUMAXALW
5111 1210558903U, // LDUMAXALX
5112 1210548655U, // LDUMAXAW
5113 1210548655U, // LDUMAXAX
5114 1210551996U, // LDUMAXB
5115 1210558694U, // LDUMAXH
5116 1210551429U, // LDUMAXLB
5117 1210558364U, // LDUMAXLH
5118 1210559199U, // LDUMAXLW
5119 1210559199U, // LDUMAXLX
5120 1210565337U, // LDUMAXW
5121 1210565337U, // LDUMAXX
5122 1210550865U, // LDUMINAB
5123 1210558017U, // LDUMINAH
5124 1210551124U, // LDUMINALB
5125 1210558172U, // LDUMINALH
5126 1210558834U, // LDUMINALW
5127 1210558834U, // LDUMINALX
5128 1210548538U, // LDUMINAW
5129 1210548538U, // LDUMINAX
5130 1210551471U, // LDUMINB
5131 1210558383U, // LDUMINH
5132 1210551334U, // LDUMINLB
5133 1210558270U, // LDUMINLH
5134 1210559056U, // LDUMINLW
5135 1210559056U, // LDUMINLX
5136 1210559310U, // LDUMINW
5137 1210559310U, // LDUMINX
5138 417369472U, // LDURBBi
5139 417377864U, // LDURBi
5140 417377864U, // LDURDi
5141 417376293U, // LDURHHi
5142 417377864U, // LDURHi
5143 417377864U, // LDURQi
5144 417369619U, // LDURSBWi
5145 417369619U, // LDURSBXi
5146 417376427U, // LDURSHWi
5147 417376427U, // LDURSHXi
5148 417383039U, // LDURSWi
5149 417377864U, // LDURSi
5150 417377864U, // LDURWi
5151 417377864U, // LDURXi
5152 404794592U, // LDXPW
5153 404794592U, // LDXPX
5154 417369511U, // LDXRB
5155 417376332U, // LDXRH
5156 417377928U, // LDXRW
5157 417377928U, // LDXRX
5158 1478569447U, // LSLR_ZPmZ_B
5159 1478602215U, // LSLR_ZPmZ_D
5160 1621241319U, // LSLR_ZPmZ_H
5161 1478667751U, // LSLR_ZPmZ_S
5162 404793997U, // LSLVWr
5163 404793997U, // LSLVXr
5164 1478568589U, // LSL_WIDE_ZPmZ_B
5165 1621240461U, // LSL_WIDE_ZPmZ_H
5166 1478666893U, // LSL_WIDE_ZPmZ_S
5167 1747004045U, // LSL_WIDE_ZZZ_B
5168 952248973U, // LSL_WIDE_ZZZ_H
5169 1881320077U, // LSL_WIDE_ZZZ_S
5170 1478568589U, // LSL_ZPmI_B
5171 1478601357U, // LSL_ZPmI_D
5172 1621240461U, // LSL_ZPmI_H
5173 1478666893U, // LSL_ZPmI_S
5174 1478568589U, // LSL_ZPmZ_B
5175 1478601357U, // LSL_ZPmZ_D
5176 1621240461U, // LSL_ZPmZ_H
5177 1478666893U, // LSL_ZPmZ_S
5178 1747004045U, // LSL_ZZI_B
5179 1075948173U, // LSL_ZZI_D
5180 952248973U, // LSL_ZZI_H
5181 1881320077U, // LSL_ZZI_S
5182 1478569494U, // LSRR_ZPmZ_B
5183 1478602262U, // LSRR_ZPmZ_D
5184 1621241366U, // LSRR_ZPmZ_H
5185 1478667798U, // LSRR_ZPmZ_S
5186 404794913U, // LSRVWr
5187 404794913U, // LSRVXr
5188 1478569505U, // LSR_WIDE_ZPmZ_B
5189 1621241377U, // LSR_WIDE_ZPmZ_H
5190 1478667809U, // LSR_WIDE_ZPmZ_S
5191 1747004961U, // LSR_WIDE_ZZZ_B
5192 952249889U, // LSR_WIDE_ZZZ_H
5193 1881320993U, // LSR_WIDE_ZZZ_S
5194 1478569505U, // LSR_ZPmI_B
5195 1478602273U, // LSR_ZPmI_D
5196 1621241377U, // LSR_ZPmI_H
5197 1478667809U, // LSR_ZPmI_S
5198 1478569505U, // LSR_ZPmZ_B
5199 1478602273U, // LSR_ZPmZ_D
5200 1621241377U, // LSR_ZPmZ_H
5201 1478667809U, // LSR_ZPmZ_S
5202 1747004961U, // LSR_ZZI_B
5203 1075949089U, // LSR_ZZI_D
5204 952249889U, // LSR_ZZI_H
5205 1881320993U, // LSR_ZZI_S
5206 404788832U, // MADDWrrr
5207 404788832U, // MADDXrrr
5208 1478563289U, // MAD_ZPmZZ_B
5209 1478596057U, // MAD_ZPmZZ_D
5210 1621235161U, // MAD_ZPmZZ_H
5211 1478661593U, // MAD_ZPmZZ_S
5212 1478567602U, // MATCH_PPzZZ_B
5213 2963416754U, // MATCH_PPzZZ_H
5214 1478557960U, // MLA_ZPmZZ_B
5215 1478590728U, // MLA_ZPmZZ_D
5216 1621229832U, // MLA_ZPmZZ_H
5217 1478656264U, // MLA_ZPmZZ_S
5218 539066632U, // MLA_ZZZI_D
5219 958529800U, // MLA_ZZZI_H
5220 673349896U, // MLA_ZZZI_S
5221 1344504674U, // MLAv16i8
5222 1344515959U, // MLAv2i32
5223 1344515959U, // MLAv2i32_indexed
5224 1344510248U, // MLAv4i16
5225 1344510248U, // MLAv4i16_indexed
5226 1344517891U, // MLAv4i32
5227 1344517891U, // MLAv4i32_indexed
5228 1344512109U, // MLAv8i16
5229 1344512109U, // MLAv8i16_indexed
5230 1344505605U, // MLAv8i8
5231 1478573557U, // MLS_ZPmZZ_B
5232 1478606325U, // MLS_ZPmZZ_D
5233 1621245429U, // MLS_ZPmZZ_H
5234 1478671861U, // MLS_ZPmZZ_S
5235 539082229U, // MLS_ZZZI_D
5236 958545397U, // MLS_ZZZI_H
5237 673365493U, // MLS_ZZZI_S
5238 1344505297U, // MLSv16i8
5239 1344516957U, // MLSv2i32
5240 1344516957U, // MLSv2i32_indexed
5241 1344511234U, // MLSv4i16
5242 1344511234U, // MLSv4i16_indexed
5243 1344519036U, // MLSv4i32
5244 1344519036U, // MLSv4i32_indexed
5245 1344513130U, // MLSv8i16
5246 1344513130U, // MLSv8i16_indexed
5247 1344506253U, // MLSv8i8
5248 1344317758U, // MOVID
5249 1478689948U, // MOVIv16b_ns
5250 1344475694U, // MOVIv2d_ns
5251 1478701363U, // MOVIv2i32
5252 1478701363U, // MOVIv2s_msl
5253 1478695629U, // MOVIv4i16
5254 1478703350U, // MOVIv4i32
5255 1478703350U, // MOVIv4s_msl
5256 1478690810U, // MOVIv8b_ns
5257 1478697490U, // MOVIv8i16
5258 2552277321U, // MOVKWi
5259 2552277321U, // MOVKXi
5260 1478536134U, // MOVNWi
5261 1478536134U, // MOVNXi
5262 2179837U, // MOVPRFX_ZPmZ_B
5263 2212605U, // MOVPRFX_ZPmZ_D
5264 138560253U, // MOVPRFX_ZPmZ_H
5265 2278141U, // MOVPRFX_ZPmZ_S
5266 1478574845U, // MOVPRFX_ZPzZ_B
5267 1478607613U, // MOVPRFX_ZPzZ_D
5268 2963423997U, // MOVPRFX_ZPzZ_H
5269 1478673149U, // MOVPRFX_ZPzZ_S
5270 1480180477U, // MOVPRFX_ZZ
5271 1478542216U, // MOVZWi
5272 1478542216U, // MOVZXi
5273 1612758596U, // MRS
5274 1478561264U, // MSB_ZPmZZ_B
5275 1478594032U, // MSB_ZPmZZ_D
5276 1621233136U, // MSB_ZPmZZ_H
5277 1478659568U, // MSB_ZPmZZ_S
5278 1715750U, // MSR
5279 1748518U, // MSRpstateImm1
5280 1748518U, // MSRpstateImm4
5281 404786801U, // MSUBWrrr
5282 404786801U, // MSUBXrrr
5283 1747004079U, // MUL_ZI_B
5284 1075948207U, // MUL_ZI_D
5285 952249007U, // MUL_ZI_H
5286 1881320111U, // MUL_ZI_S
5287 1478568623U, // MUL_ZPmZ_B
5288 1478601391U, // MUL_ZPmZ_D
5289 1621240495U, // MUL_ZPmZ_H
5290 1478666927U, // MUL_ZPmZ_S
5291 1075948207U, // MUL_ZZZI_D
5292 952249007U, // MUL_ZZZI_H
5293 1881320111U, // MUL_ZZZI_S
5294 1747004079U, // MUL_ZZZ_B
5295 1075948207U, // MUL_ZZZ_D
5296 952249007U, // MUL_ZZZ_H
5297 1881320111U, // MUL_ZZZ_S
5298 270730504U, // MULv16i8
5299 270741901U, // MULv2i32
5300 270741901U, // MULv2i32_indexed
5301 270736167U, // MULv4i16
5302 270736167U, // MULv4i16_indexed
5303 270744084U, // MULv4i32
5304 270744084U, // MULv4i32_indexed
5305 270738198U, // MULv8i16
5306 270738198U, // MULv8i16_indexed
5307 270731356U, // MULv8i8
5308 1478701335U, // MVNIv2i32
5309 1478701335U, // MVNIv2s_msl
5310 1478695601U, // MVNIv4i16
5311 1478703322U, // MVNIv4i32
5312 1478703322U, // MVNIv4s_msl
5313 1478697462U, // MVNIv8i16
5314 1478573505U, // NANDS_PPzPP
5315 1478563460U, // NAND_PPzPP
5316 1075948163U, // NBSL_ZZZZ
5317 2168717U, // NEG_ZPmZ_B
5318 2201485U, // NEG_ZPmZ_D
5319 138549133U, // NEG_ZPmZ_H
5320 2267021U, // NEG_ZPmZ_S
5321 270730359U, // NEGv16i8
5322 404789133U, // NEGv1i64
5323 270741697U, // NEGv2i32
5324 270733804U, // NEGv2i64
5325 270735963U, // NEGv4i16
5326 270743672U, // NEGv4i32
5327 270737824U, // NEGv8i16
5328 270731225U, // NEGv8i8
5329 1478567601U, // NMATCH_PPzZZ_B
5330 2963416753U, // NMATCH_PPzZZ_H
5331 1478573647U, // NORS_PPzPP
5332 1478569466U, // NOR_PPzPP
5333 2179194U, // NOT_ZPmZ_B
5334 2211962U, // NOT_ZPmZ_D
5335 138559610U, // NOT_ZPmZ_H
5336 2277498U, // NOT_ZPmZ_S
5337 270730753U, // NOTv16i8
5338 270731704U, // NOTv8i8
5339 1478573591U, // ORNS_PPzPP
5340 404794249U, // ORNWrs
5341 404794249U, // ORNXrs
5342 1478568841U, // ORN_PPzPP
5343 270730533U, // ORNv16i8
5344 270731450U, // ORNv8i8
5345 1478573653U, // ORRS_PPzPP
5346 404794891U, // ORRWri
5347 404794891U, // ORRWrs
5348 404794891U, // ORRXri
5349 404794891U, // ORRXrs
5350 1478569483U, // ORR_PPzPP
5351 1075949067U, // ORR_ZI
5352 1478569483U, // ORR_ZPmZ_B
5353 1478602251U, // ORR_ZPmZ_D
5354 1621241355U, // ORR_ZPmZ_H
5355 1478667787U, // ORR_ZPmZ_S
5356 1075949067U, // ORR_ZZZ
5357 270730666U, // ORRv16i8
5358 2552476453U, // ORRv2i32
5359 2552470730U, // ORRv4i16
5360 2552478532U, // ORRv4i32
5361 2552472626U, // ORRv8i16
5362 270731626U, // ORRv8i8
5363 278910U, // ORV_VPZ_B
5364 2164572542U, // ORV_VPZ_D
5365 2166702462U, // ORV_VPZ_H
5366 2156249470U, // ORV_VPZ_S
5367 404783310U, // PACDA
5368 404785877U, // PACDB
5369 33208U, // PACDZA
5370 36549U, // PACDZB
5371 404783339U, // PACGA
5372 404783346U, // PACIA
5373 17569U, // PACIA1716
5374 17527U, // PACIASP
5375 17518U, // PACIAZ
5376 404785912U, // PACIB
5377 17459U, // PACIB1716
5378 17560U, // PACIBSP
5379 17543U, // PACIBZ
5380 33224U, // PACIZA
5381 36565U, // PACIZB
5382 71482U, // PFALSE
5383 1478574236U, // PFIRST_B
5384 1881246724U, // PMULLB_ZZZ_D
5385 1046612996U, // PMULLB_ZZZ_H
5386 109710340U, // PMULLB_ZZZ_Q
5387 1881259911U, // PMULLT_ZZZ_D
5388 1046626183U, // PMULLT_ZZZ_H
5389 109723527U, // PMULLT_ZZZ_Q
5390 270737214U, // PMULLv16i8
5391 270740734U, // PMULLv1i64
5392 270740723U, // PMULLv2i64
5393 270738147U, // PMULLv8i8
5394 1747004091U, // PMUL_ZZZ_B
5395 270730503U, // PMULv16i8
5396 270731355U, // PMULv8i8
5397 1478574296U, // PNEXT_B
5398 1478607064U, // PNEXT_D
5399 950157528U, // PNEXT_H
5400 1478672600U, // PNEXT_S
5401 958073579U, // PRFB_D_PZI
5402 997919467U, // PRFB_D_SCALED
5403 997919467U, // PRFB_D_SXTW_SCALED
5404 997919467U, // PRFB_D_UXTW_SCALED
5405 997919467U, // PRFB_PRI
5406 997919467U, // PRFB_PRR
5407 949684971U, // PRFB_S_PZI
5408 997919467U, // PRFB_S_SXTW_SCALED
5409 997919467U, // PRFB_S_UXTW_SCALED
5410 958076542U, // PRFD_D_PZI
5411 997922430U, // PRFD_D_SCALED
5412 997922430U, // PRFD_D_SXTW_SCALED
5413 997922430U, // PRFD_D_UXTW_SCALED
5414 997922430U, // PRFD_PRI
5415 997922430U, // PRFD_PRR
5416 949687934U, // PRFD_S_PZI
5417 997922430U, // PRFD_S_SXTW_SCALED
5418 997922430U, // PRFD_S_UXTW_SCALED
5419 958080705U, // PRFH_D_PZI
5420 997926593U, // PRFH_D_SCALED
5421 997926593U, // PRFH_D_SXTW_SCALED
5422 997926593U, // PRFH_D_UXTW_SCALED
5423 997926593U, // PRFH_PRI
5424 997926593U, // PRFH_PRR
5425 949692097U, // PRFH_S_PZI
5426 997926593U, // PRFH_S_SXTW_SCALED
5427 997926593U, // PRFH_S_UXTW_SCALED
5428 2688264948U, // PRFMl
5429 419146484U, // PRFMroW
5430 419146484U, // PRFMroX
5431 419146484U, // PRFMui
5432 997933593U, // PRFS_PRR
5433 419146539U, // PRFUMi
5434 958087705U, // PRFW_D_PZI
5435 997933593U, // PRFW_D_SCALED
5436 997933593U, // PRFW_D_SXTW_SCALED
5437 997933593U, // PRFW_D_UXTW_SCALED
5438 997933593U, // PRFW_PRI
5439 949699097U, // PRFW_S_PZI
5440 997933593U, // PRFW_S_SXTW_SCALED
5441 997933593U, // PRFW_S_UXTW_SCALED
5442 1748615310U, // PTEST_PP
5443 3089186248U, // PTRUES_B
5444 3089219016U, // PTRUES_D
5445 111295944U, // PTRUES_H
5446 3089284552U, // PTRUES_S
5447 3089176404U, // PTRUE_B
5448 3089209172U, // PTRUE_D
5449 111286100U, // PTRUE_H
5450 3089274708U, // PTRUE_S
5451 2254579967U, // PUNPKHI_PP
5452 2254580701U, // PUNPKLO_PP
5453 807472285U, // RADDHNB_ZZZ_B
5454 945949853U, // RADDHNB_ZZZ_H
5455 1076006045U, // RADDHNB_ZZZ_S
5456 1210138601U, // RADDHNT_ZZZ_B
5457 948060137U, // RADDHNT_ZZZ_H
5458 539148265U, // RADDHNT_ZZZ_S
5459 270741953U, // RADDHNv2i64_v2i32
5460 1344517629U, // RADDHNv2i64_v4i32
5461 270736219U, // RADDHNv4i32_v4i16
5462 1344511873U, // RADDHNv4i32_v8i16
5463 1344504459U, // RADDHNv8i16_v16i8
5464 270731375U, // RADDHNv8i16_v8i8
5465 270733275U, // RAX1
5466 1075937325U, // RAX1_ZZZ_D
5467 404799202U, // RBITWr
5468 404799202U, // RBITXr
5469 2178786U, // RBIT_ZPmZ_B
5470 2211554U, // RBIT_ZPmZ_D
5471 138559202U, // RBIT_ZPmZ_H
5472 2277090U, // RBIT_ZPmZ_S
5473 270730724U, // RBITv16i8
5474 270731678U, // RBITv8i8
5475 1478573628U, // RDFFRS_PPz
5476 1478569338U, // RDFFR_PPz_REAL
5477 77178U, // RDFFR_P_REAL
5478 404794064U, // RDVLI_XI
5479 48824U, // RET
5480 17684U, // RETAA
5481 17711U, // RETAB
5482 404783271U, // REV16Wr
5483 404783271U, // REV16Xr
5484 270730051U, // REV16v16i8
5485 270730985U, // REV16v8i8
5486 404783155U, // REV32Xr
5487 270729843U, // REV32v16i8
5488 270735589U, // REV32v4i16
5489 270737072U, // REV32v8i16
5490 270730938U, // REV32v8i8
5491 270730040U, // REV64v16i8
5492 270741337U, // REV64v2i32
5493 270735626U, // REV64v4i16
5494 270743245U, // REV64v4i32
5495 270737487U, // REV64v8i16
5496 270730975U, // REV64v8i8
5497 2199181U, // REVB_ZPmZ_D
5498 138546829U, // REVB_ZPmZ_H
5499 2264717U, // REVB_ZPmZ_S
5500 2205911U, // REVH_ZPmZ_D
5501 2271447U, // REVH_ZPmZ_S
5502 2212515U, // REVW_ZPmZ_D
5503 404799794U, // REVWr
5504 404799794U, // REVXr
5505 1747009842U, // REV_PP_B
5506 1075953970U, // REV_PP_D
5507 2160214322U, // REV_PP_H
5508 1881325874U, // REV_PP_S
5509 1747009842U, // REV_ZZ_B
5510 1075953970U, // REV_ZZ_D
5511 2160214322U, // REV_ZZ_H
5512 1881325874U, // REV_ZZ_S
5513 17728U, // RMIF
5514 404794879U, // RORVWr
5515 404794879U, // RORVXr
5516 807472332U, // RSHRNB_ZZI_B
5517 945949900U, // RSHRNB_ZZI_H
5518 1076006092U, // RSHRNB_ZZI_S
5519 1210138636U, // RSHRNT_ZZI_B
5520 948060172U, // RSHRNT_ZZI_H
5521 539148300U, // RSHRNT_ZZI_S
5522 1344504500U, // RSHRNv16i8_shift
5523 270742015U, // RSHRNv2i32_shift
5524 270736281U, // RSHRNv4i16_shift
5525 1344517667U, // RSHRNv4i32_shift
5526 1344511911U, // RSHRNv8i16_shift
5527 270731428U, // RSHRNv8i8_shift
5528 807472276U, // RSUBHNB_ZZZ_B
5529 945949844U, // RSUBHNB_ZZZ_H
5530 1076006036U, // RSUBHNB_ZZZ_S
5531 1210138592U, // RSUBHNT_ZZZ_B
5532 948060128U, // RSUBHNT_ZZZ_H
5533 539148256U, // RSUBHNT_ZZZ_S
5534 270741942U, // RSUBHNv2i64_v2i32
5535 1344517617U, // RSUBHNv2i64_v4i32
5536 270736208U, // RSUBHNv4i32_v4i16
5537 1344511861U, // RSUBHNv4i32_v8i16
5538 1344504446U, // RSUBHNv8i16_v16i8
5539 270731364U, // RSUBHNv8i16_v8i8
5540 673286924U, // SABALB_ZZZ_D
5541 1052904204U, // SABALB_ZZZ_H
5542 1210223372U, // SABALB_ZZZ_S
5543 673300206U, // SABALT_ZZZ_D
5544 1052917486U, // SABALT_ZZZ_H
5545 1210236654U, // SABALT_ZZZ_S
5546 1344511674U, // SABALv16i8_v8i16
5547 1344508471U, // SABALv2i32_v2i64
5548 1344518399U, // SABALv4i16_v4i32
5549 1344507889U, // SABALv4i32_v2i64
5550 1344517402U, // SABALv8i16_v4i32
5551 1344512539U, // SABALv8i8_v8i16
5552 2820735170U, // SABA_ZZZ_B
5553 539066562U, // SABA_ZZZ_D
5554 958529730U, // SABA_ZZZ_H
5555 673349826U, // SABA_ZZZ_S
5556 1344504654U, // SABAv16i8
5557 1344515939U, // SABAv2i32
5558 1344510228U, // SABAv4i16
5559 1344517871U, // SABAv4i32
5560 1344512089U, // SABAv8i16
5561 1344505587U, // SABAv8i8
5562 1881246657U, // SABDLB_ZZZ_D
5563 1046612929U, // SABDLB_ZZZ_H
5564 807570369U, // SABDLB_ZZZ_S
5565 1881259839U, // SABDLT_ZZZ_D
5566 1046626111U, // SABDLT_ZZZ_H
5567 807583551U, // SABDLT_ZZZ_S
5568 270737148U, // SABDLv16i8_v8i16
5569 270733951U, // SABDLv2i32_v2i64
5570 270743879U, // SABDLv4i16_v4i32
5571 270733376U, // SABDLv4i32_v2i64
5572 270742889U, // SABDLv8i16_v4i32
5573 270738007U, // SABDLv8i8_v8i16
5574 1478563314U, // SABD_ZPmZ_B
5575 1478596082U, // SABD_ZPmZ_D
5576 1621235186U, // SABD_ZPmZ_H
5577 1478661618U, // SABD_ZPmZ_S
5578 270730209U, // SABDv16i8
5579 270741499U, // SABDv2i32
5580 270735788U, // SABDv4i16
5581 270743465U, // SABDv4i32
5582 270737649U, // SABDv8i16
5583 270731107U, // SABDv8i8
5584 1478601796U, // SADALP_ZPmZ_D
5585 1621240900U, // SADALP_ZPmZ_H
5586 1478667332U, // SADALP_ZPmZ_S
5587 1344512879U, // SADALPv16i8_v8i16
5588 1344507724U, // SADALPv2i32_v1i64
5589 1344516706U, // SADALPv4i16_v2i32
5590 1344508819U, // SADALPv4i32_v2i64
5591 1344518785U, // SADALPv8i16_v4i32
5592 1344510983U, // SADALPv8i8_v4i16
5593 1881259662U, // SADDLBT_ZZZ_D
5594 1046625934U, // SADDLBT_ZZZ_H
5595 807583374U, // SADDLBT_ZZZ_S
5596 1881246682U, // SADDLB_ZZZ_D
5597 1046612954U, // SADDLB_ZZZ_H
5598 807570394U, // SADDLB_ZZZ_S
5599 270738309U, // SADDLPv16i8_v8i16
5600 270733154U, // SADDLPv2i32_v1i64
5601 270742136U, // SADDLPv4i16_v2i32
5602 270734249U, // SADDLPv4i32_v2i64
5603 270744215U, // SADDLPv8i16_v4i32
5604 270736413U, // SADDLPv8i8_v4i16
5605 1881259855U, // SADDLT_ZZZ_D
5606 1046626127U, // SADDLT_ZZZ_H
5607 807583567U, // SADDLT_ZZZ_S
5608 270566964U, // SADDLVv16i8v
5609 270573011U, // SADDLVv4i16v
5610 270580813U, // SADDLVv4i32v
5611 270574907U, // SADDLVv8i16v
5612 270567910U, // SADDLVv8i8v
5613 270737170U, // SADDLv16i8_v8i16
5614 270733971U, // SADDLv2i32_v2i64
5615 270743899U, // SADDLv4i16_v4i32
5616 270733398U, // SADDLv4i32_v2i64
5617 270742911U, // SADDLv8i16_v4i32
5618 270738027U, // SADDLv8i8_v8i16
5619 2261041438U, // SADDV_VPZ_B
5620 2166669598U, // SADDV_VPZ_H
5621 2156183838U, // SADDV_VPZ_S
5622 1075941027U, // SADDWB_ZZZ_D
5623 952241827U, // SADDWB_ZZZ_H
5624 1881312931U, // SADDWB_ZZZ_S
5625 1075953858U, // SADDWT_ZZZ_D
5626 952254658U, // SADDWT_ZZZ_H
5627 1881325762U, // SADDWT_ZZZ_S
5628 270737465U, // SADDWv16i8_v8i16
5629 270734659U, // SADDWv2i32_v2i64
5630 270744788U, // SADDWv4i16_v4i32
5631 270733561U, // SADDWv4i32_v2i64
5632 270743209U, // SADDWv8i16_v4i32
5633 270738882U, // SADDWv8i8_v8i16
5634 17725U, // SB
5635 539069363U, // SBCLB_ZZZ_D
5636 673352627U, // SBCLB_ZZZ_S
5637 539082545U, // SBCLT_ZZZ_D
5638 673365809U, // SBCLT_ZZZ_S
5639 404798889U, // SBCSWr
5640 404798889U, // SBCSXr
5641 404786917U, // SBCWr
5642 404786917U, // SBCXr
5643 404794088U, // SBFMWri
5644 404794088U, // SBFMXri
5645 404789088U, // SCVTFSWDri
5646 404789088U, // SCVTFSWHri
5647 404789088U, // SCVTFSWSri
5648 404789088U, // SCVTFSXDri
5649 404789088U, // SCVTFSXHri
5650 404789088U, // SCVTFSXSri
5651 404789088U, // SCVTFUWDri
5652 404789088U, // SCVTFUWHri
5653 404789088U, // SCVTFUWSri
5654 404789088U, // SCVTFUXDri
5655 404789088U, // SCVTFUXHri
5656 404789088U, // SCVTFUXSri
5657 2201440U, // SCVTF_ZPmZ_DtoD
5658 541202272U, // SCVTF_ZPmZ_DtoH
5659 2266976U, // SCVTF_ZPmZ_DtoS
5660 138549088U, // SCVTF_ZPmZ_HtoH
5661 2201440U, // SCVTF_ZPmZ_StoD
5662 2286032736U, // SCVTF_ZPmZ_StoH
5663 2266976U, // SCVTF_ZPmZ_StoS
5664 404789088U, // SCVTFd
5665 404789088U, // SCVTFh
5666 404789088U, // SCVTFs
5667 404789088U, // SCVTFv1i16
5668 404789088U, // SCVTFv1i32
5669 404789088U, // SCVTFv1i64
5670 270741676U, // SCVTFv2f32
5671 270733783U, // SCVTFv2f64
5672 270741676U, // SCVTFv2i32_shift
5673 270733783U, // SCVTFv2i64_shift
5674 270735942U, // SCVTFv4f16
5675 270743651U, // SCVTFv4f32
5676 270735942U, // SCVTFv4i16_shift
5677 270743651U, // SCVTFv4i32_shift
5678 270737803U, // SCVTFv8f16
5679 270737803U, // SCVTFv8i16_shift
5680 1478602346U, // SDIVR_ZPmZ_D
5681 1478667882U, // SDIVR_ZPmZ_S
5682 404799805U, // SDIVWr
5683 404799805U, // SDIVXr
5684 1478607165U, // SDIV_ZPmZ_D
5685 1478672701U, // SDIV_ZPmZ_S
5686 1210171500U, // SDOT_ZZZI_D
5687 2820849772U, // SDOT_ZZZI_S
5688 1210171500U, // SDOT_ZZZ_D
5689 2820849772U, // SDOT_ZZZ_S
5690 1344520300U, // SDOTlanev16i8
5691 1344520300U, // SDOTlanev8i8
5692 17830U, // SDOTv16i8
5693 17830U, // SDOTv8i8
5694 1478568441U, // SEL_PPPP
5695 1478568441U, // SEL_ZPZZ_B
5696 1478601209U, // SEL_ZPZZ_D
5697 950151673U, // SEL_ZPZZ_H
5698 1478666745U, // SEL_ZPZZ_S
5699 17536U, // SETF16
5700 17586U, // SETF8
5701 17790U, // SETFFR
5702 2418521998U, // SHA1Crrr
5703 404789313U, // SHA1Hrr
5704 2418522652U, // SHA1Mrrr
5705 2418522733U, // SHA1Prrr
5706 1344517285U, // SHA1SU0rrr
5707 1344517349U, // SHA1SU1rr
5708 2418521357U, // SHA256H2rrr
5709 2418522250U, // SHA256Hrrr
5710 1344517297U, // SHA256SU0rr
5711 1344517361U, // SHA256SU1rrr
5712 2418512382U, // SHA512H
5713 2418511844U, // SHA512H2
5714 270733220U, // SHA512SU0
5715 1344507853U, // SHA512SU1
5716 1478563409U, // SHADD_ZPmZ_B
5717 1478596177U, // SHADD_ZPmZ_D
5718 1621235281U, // SHADD_ZPmZ_H
5719 1478661713U, // SHADD_ZPmZ_S
5720 270730253U, // SHADDv16i8
5721 270741558U, // SHADDv2i32
5722 270735847U, // SHADDv4i16
5723 270743524U, // SHADDv4i32
5724 270737708U, // SHADDv8i16
5725 270731147U, // SHADDv8i8
5726 270737193U, // SHLLv16i8
5727 270734072U, // SHLLv2i32
5728 270744000U, // SHLLv4i16
5729 270733421U, // SHLLv4i32
5730 270742934U, // SHLLv8i16
5731 270738128U, // SHLLv8i8
5732 404793864U, // SHLd
5733 270730408U, // SHLv16i8_shift
5734 270741822U, // SHLv2i32_shift
5735 270733993U, // SHLv2i64_shift
5736 270736088U, // SHLv4i16_shift
5737 270743921U, // SHLv4i32_shift
5738 270738049U, // SHLv8i16_shift
5739 270731269U, // SHLv8i8_shift
5740 807472314U, // SHRNB_ZZI_B
5741 945949882U, // SHRNB_ZZI_H
5742 1076006074U, // SHRNB_ZZI_S
5743 1210138618U, // SHRNT_ZZI_B
5744 948060154U, // SHRNT_ZZI_H
5745 539148282U, // SHRNT_ZZI_S
5746 1344504474U, // SHRNv16i8_shift
5747 270741993U, // SHRNv2i32_shift
5748 270736259U, // SHRNv4i16_shift
5749 1344517643U, // SHRNv4i32_shift
5750 1344511887U, // SHRNv8i16_shift
5751 270731406U, // SHRNv8i8_shift
5752 1478569296U, // SHSUBR_ZPmZ_B
5753 1478602064U, // SHSUBR_ZPmZ_D
5754 1621241168U, // SHSUBR_ZPmZ_H
5755 1478667600U, // SHSUBR_ZPmZ_S
5756 1478561378U, // SHSUB_ZPmZ_B
5757 1478594146U, // SHSUB_ZPmZ_D
5758 1621233250U, // SHSUB_ZPmZ_H
5759 1478659682U, // SHSUB_ZPmZ_S
5760 270730133U, // SHSUBv16i8
5761 270741442U, // SHSUBv2i32
5762 270735731U, // SHSUBv4i16
5763 270743398U, // SHSUBv4i32
5764 270737592U, // SHSUBv8i16
5765 270731059U, // SHSUBv8i8
5766 2820745511U, // SLI_ZZI_B
5767 539076903U, // SLI_ZZI_D
5768 958540071U, // SLI_ZZI_H
5769 673360167U, // SLI_ZZI_S
5770 2418518311U, // SLId
5771 1344504970U, // SLIv16i8_shift
5772 1344516367U, // SLIv2i32_shift
5773 1344508435U, // SLIv2i64_shift
5774 1344510633U, // SLIv4i16_shift
5775 1344518354U, // SLIv4i32_shift
5776 1344512494U, // SLIv8i16_shift
5777 1344505834U, // SLIv8i8_shift
5778 1344517375U, // SM3PARTW1
5779 1344517823U, // SM3PARTW2
5780 270742746U, // SM3SS1
5781 1344517847U, // SM3TT1A
5782 1344517957U, // SM3TT1B
5783 1344517859U, // SM3TT2A
5784 1344517969U, // SM3TT2B
5785 270743566U, // SM4E
5786 1881326372U, // SM4EKEY_ZZZ_S
5787 270744882U, // SM4ENCKEY
5788 1881314995U, // SM4E_ZZZ_S
5789 404793822U, // SMADDLrrr
5790 1478569170U, // SMAXP_ZPmZ_B
5791 1478601938U, // SMAXP_ZPmZ_D
5792 1621241042U, // SMAXP_ZPmZ_H
5793 1478667474U, // SMAXP_ZPmZ_S
5794 270730583U, // SMAXPv16i8
5795 270742241U, // SMAXPv2i32
5796 270736518U, // SMAXPv4i16
5797 270744320U, // SMAXPv4i32
5798 270738414U, // SMAXPv8i16
5799 270731551U, // SMAXPv8i8
5800 278922U, // SMAXV_VPZ_B
5801 2164572554U, // SMAXV_VPZ_D
5802 2166702474U, // SMAXV_VPZ_H
5803 2156249482U, // SMAXV_VPZ_S
5804 270567010U, // SMAXVv16i8v
5805 270573106U, // SMAXVv4i16v
5806 270580908U, // SMAXVv4i32v
5807 270575002U, // SMAXVv8i16v
5808 270567952U, // SMAXVv8i8v
5809 1747010259U, // SMAX_ZI_B
5810 1075954387U, // SMAX_ZI_D
5811 952255187U, // SMAX_ZI_H
5812 1881326291U, // SMAX_ZI_S
5813 1478574803U, // SMAX_ZPmZ_B
5814 1478607571U, // SMAX_ZPmZ_D
5815 1621246675U, // SMAX_ZPmZ_H
5816 1478673107U, // SMAX_ZPmZ_S
5817 270730882U, // SMAXv16i8
5818 270742609U, // SMAXv2i32
5819 270736975U, // SMAXv4i16
5820 270744843U, // SMAXv4i32
5821 270738911U, // SMAXv8i16
5822 270731812U, // SMAXv8i8
5823 429822U, // SMC
5824 1478569088U, // SMINP_ZPmZ_B
5825 1478601856U, // SMINP_ZPmZ_D
5826 1621240960U, // SMINP_ZPmZ_H
5827 1478667392U, // SMINP_ZPmZ_S
5828 270730552U, // SMINPv16i8
5829 270742192U, // SMINPv2i32
5830 270736469U, // SMINPv4i16
5831 270744271U, // SMINPv4i32
5832 270738365U, // SMINPv8i16
5833 270731523U, // SMINPv8i8
5834 278882U, // SMINV_VPZ_B
5835 2164572514U, // SMINV_VPZ_D
5836 2166702434U, // SMINV_VPZ_H
5837 2156249442U, // SMINV_VPZ_S
5838 270566988U, // SMINVv16i8v
5839 270573067U, // SMINVv4i16v
5840 270580869U, // SMINVv4i32v
5841 270574963U, // SMINVv8i16v
5842 270567932U, // SMINVv8i8v
5843 1747004232U, // SMIN_ZI_B
5844 1075948360U, // SMIN_ZI_D
5845 952249160U, // SMIN_ZI_H
5846 1881320264U, // SMIN_ZI_S
5847 1478568776U, // SMIN_ZPmZ_B
5848 1478601544U, // SMIN_ZPmZ_D
5849 1621240648U, // SMIN_ZPmZ_H
5850 1478667080U, // SMIN_ZPmZ_S
5851 270730513U, // SMINv16i8
5852 270741973U, // SMINv2i32
5853 270736239U, // SMINv4i16
5854 270744144U, // SMINv4i32
5855 270738248U, // SMINv8i16
5856 270731386U, // SMINv8i8
5857 673286969U, // SMLALB_ZZZI_D
5858 1210223417U, // SMLALB_ZZZI_S
5859 673286969U, // SMLALB_ZZZ_D
5860 1052904249U, // SMLALB_ZZZ_H
5861 1210223417U, // SMLALB_ZZZ_S
5862 673300241U, // SMLALT_ZZZI_D
5863 1210236689U, // SMLALT_ZZZI_S
5864 673300241U, // SMLALT_ZZZ_D
5865 1052917521U, // SMLALT_ZZZ_H
5866 1210236689U, // SMLALT_ZZZ_S
5867 1344511696U, // SMLALv16i8_v8i16
5868 1344508503U, // SMLALv2i32_indexed
5869 1344508503U, // SMLALv2i32_v2i64
5870 1344518431U, // SMLALv4i16_indexed
5871 1344518431U, // SMLALv4i16_v4i32
5872 1344507924U, // SMLALv4i32_indexed
5873 1344507924U, // SMLALv4i32_v2i64
5874 1344517437U, // SMLALv8i16_indexed
5875 1344517437U, // SMLALv8i16_v4i32
5876 1344512559U, // SMLALv8i8_v8i16
5877 673287266U, // SMLSLB_ZZZI_D
5878 1210223714U, // SMLSLB_ZZZI_S
5879 673287266U, // SMLSLB_ZZZ_D
5880 1052904546U, // SMLSLB_ZZZ_H
5881 1210223714U, // SMLSLB_ZZZ_S
5882 673300415U, // SMLSLT_ZZZI_D
5883 1210236863U, // SMLSLT_ZZZI_S
5884 673300415U, // SMLSLT_ZZZ_D
5885 1052917695U, // SMLSLT_ZZZ_H
5886 1210236863U, // SMLSLT_ZZZ_S
5887 1344511839U, // SMLSLv16i8_v8i16
5888 1344508727U, // SMLSLv2i32_indexed
5889 1344508727U, // SMLSLv2i32_v2i64
5890 1344518655U, // SMLSLv4i16_indexed
5891 1344518655U, // SMLSLv4i16_v4i32
5892 1344508082U, // SMLSLv4i32_indexed
5893 1344508082U, // SMLSLv4i32_v2i64
5894 1344517595U, // SMLSLv8i16_indexed
5895 1344517595U, // SMLSLv8i16_v4i32
5896 1344512769U, // SMLSLv8i8_v8i16
5897 17698U, // SMMLA
5898 2820833564U, // SMMLA_ZZZ
5899 270571560U, // SMOVvi16to32
5900 270571560U, // SMOVvi16to64
5901 270577418U, // SMOVvi32to64
5902 270565855U, // SMOVvi8to32
5903 270565855U, // SMOVvi8to64
5904 404793798U, // SMSUBLrrr
5905 1478567812U, // SMULH_ZPmZ_B
5906 1478600580U, // SMULH_ZPmZ_D
5907 1621239684U, // SMULH_ZPmZ_H
5908 1478666116U, // SMULH_ZPmZ_S
5909 1747003268U, // SMULH_ZZZ_B
5910 1075947396U, // SMULH_ZZZ_D
5911 952248196U, // SMULH_ZZZ_H
5912 1881319300U, // SMULH_ZZZ_S
5913 404793220U, // SMULHrr
5914 1881246732U, // SMULLB_ZZZI_D
5915 807570444U, // SMULLB_ZZZI_S
5916 1881246732U, // SMULLB_ZZZ_D
5917 1046613004U, // SMULLB_ZZZ_H
5918 807570444U, // SMULLB_ZZZ_S
5919 1881259919U, // SMULLT_ZZZI_D
5920 807583631U, // SMULLT_ZZZI_S
5921 1881259919U, // SMULLT_ZZZ_D
5922 1046626191U, // SMULLT_ZZZ_H
5923 807583631U, // SMULLT_ZZZ_S
5924 270737225U, // SMULLv16i8_v8i16
5925 270734103U, // SMULLv2i32_indexed
5926 270734103U, // SMULLv2i32_v2i64
5927 270744031U, // SMULLv4i16_indexed
5928 270744031U, // SMULLv4i16_v4i32
5929 270733455U, // SMULLv4i32_indexed
5930 270733455U, // SMULLv4i32_v2i64
5931 270742968U, // SMULLv8i16_indexed
5932 270742968U, // SMULLv8i16_v4i32
5933 270738157U, // SMULLv8i8_v8i16
5934 1478563513U, // SPLICE_ZPZZ_B
5935 1478596281U, // SPLICE_ZPZZ_D
5936 950146745U, // SPLICE_ZPZZ_H
5937 1478661817U, // SPLICE_ZPZZ_S
5938 1478563513U, // SPLICE_ZPZ_B
5939 1478596281U, // SPLICE_ZPZ_D
5940 950146745U, // SPLICE_ZPZ_H
5941 1478661817U, // SPLICE_ZPZ_S
5942 2178445U, // SQABS_ZPmZ_B
5943 2211213U, // SQABS_ZPmZ_D
5944 138558861U, // SQABS_ZPmZ_H
5945 2276749U, // SQABS_ZPmZ_S
5946 270730675U, // SQABSv16i8
5947 404798861U, // SQABSv1i16
5948 404798861U, // SQABSv1i32
5949 404798861U, // SQABSv1i64
5950 404798861U, // SQABSv1i8
5951 270742337U, // SQABSv2i32
5952 270734410U, // SQABSv2i64
5953 270736614U, // SQABSv4i16
5954 270744416U, // SQABSv4i32
5955 270738510U, // SQABSv8i16
5956 270731634U, // SQABSv8i8
5957 1746998895U, // SQADD_ZI_B
5958 1075943023U, // SQADD_ZI_D
5959 952243823U, // SQADD_ZI_H
5960 1881314927U, // SQADD_ZI_S
5961 1478563439U, // SQADD_ZPmZ_B
5962 1478596207U, // SQADD_ZPmZ_D
5963 1621235311U, // SQADD_ZPmZ_H
5964 1478661743U, // SQADD_ZPmZ_S
5965 1746998895U, // SQADD_ZZZ_B
5966 1075943023U, // SQADD_ZZZ_D
5967 952243823U, // SQADD_ZZZ_H
5968 1881314927U, // SQADD_ZZZ_S
5969 270730276U, // SQADDv16i8
5970 404788847U, // SQADDv1i16
5971 404788847U, // SQADDv1i32
5972 404788847U, // SQADDv1i64
5973 404788847U, // SQADDv1i8
5974 270741579U, // SQADDv2i32
5975 270733709U, // SQADDv2i64
5976 270735868U, // SQADDv4i16
5977 270743545U, // SQADDv4i32
5978 270737729U, // SQADDv8i16
5979 270731168U, // SQADDv8i8
5980 1746998828U, // SQCADD_ZZI_B
5981 1075942956U, // SQCADD_ZZI_D
5982 952243756U, // SQCADD_ZZI_H
5983 1881314860U, // SQCADD_ZZI_S
5984 3491793589U, // SQDECB_XPiI
5985 1746963125U, // SQDECB_XPiWdI
5986 3491796485U, // SQDECD_XPiI
5987 1746966021U, // SQDECD_XPiWdI
5988 3491862021U, // SQDECD_ZPiI
5989 3491800721U, // SQDECH_XPiI
5990 1746970257U, // SQDECH_XPiWdI
5991 21112465U, // SQDECH_ZPiI
5992 1746971660U, // SQDECP_XPWd_B
5993 1075883020U, // SQDECP_XPWd_D
5994 807447564U, // SQDECP_XPWd_H
5995 1881189388U, // SQDECP_XPWd_S
5996 1746971660U, // SQDECP_XP_B
5997 1075883020U, // SQDECP_XP_D
5998 807447564U, // SQDECP_XP_H
5999 1881189388U, // SQDECP_XP_S
6000 539077644U, // SQDECP_ZP_D
6001 2166500364U, // SQDECP_ZP_H
6002 673360908U, // SQDECP_ZP_S
6003 3491807737U, // SQDECW_XPiI
6004 1746977273U, // SQDECW_XPiWdI
6005 3491938809U, // SQDECW_ZPiI
6006 673300090U, // SQDMLALBT_ZZZ_D
6007 1052917370U, // SQDMLALBT_ZZZ_H
6008 1210236538U, // SQDMLALBT_ZZZ_S
6009 673286950U, // SQDMLALB_ZZZI_D
6010 1210223398U, // SQDMLALB_ZZZI_S
6011 673286950U, // SQDMLALB_ZZZ_D
6012 1052904230U, // SQDMLALB_ZZZ_H
6013 1210223398U, // SQDMLALB_ZZZ_S
6014 673300222U, // SQDMLALT_ZZZI_D
6015 1210236670U, // SQDMLALT_ZZZI_S
6016 673300222U, // SQDMLALT_ZZZ_D
6017 1052917502U, // SQDMLALT_ZZZ_H
6018 1210236670U, // SQDMLALT_ZZZ_S
6019 2418518360U, // SQDMLALi16
6020 2418518360U, // SQDMLALi32
6021 2418513904U, // SQDMLALv1i32_indexed
6022 2418519762U, // SQDMLALv1i64_indexed
6023 1344508491U, // SQDMLALv2i32_indexed
6024 1344508491U, // SQDMLALv2i32_v2i64
6025 1344518419U, // SQDMLALv4i16_indexed
6026 1344518419U, // SQDMLALv4i16_v4i32
6027 1344507911U, // SQDMLALv4i32_indexed
6028 1344507911U, // SQDMLALv4i32_v2i64
6029 1344517424U, // SQDMLALv8i16_indexed
6030 1344517424U, // SQDMLALv8i16_v4i32
6031 673300119U, // SQDMLSLBT_ZZZ_D
6032 1052917399U, // SQDMLSLBT_ZZZ_H
6033 1210236567U, // SQDMLSLBT_ZZZ_S
6034 673287248U, // SQDMLSLB_ZZZI_D
6035 1210223696U, // SQDMLSLB_ZZZI_S
6036 673287248U, // SQDMLSLB_ZZZ_D
6037 1052904528U, // SQDMLSLB_ZZZ_H
6038 1210223696U, // SQDMLSLB_ZZZ_S
6039 673300397U, // SQDMLSLT_ZZZI_D
6040 1210236845U, // SQDMLSLT_ZZZI_S
6041 673300397U, // SQDMLSLT_ZZZ_D
6042 1052917677U, // SQDMLSLT_ZZZ_H
6043 1210236845U, // SQDMLSLT_ZZZ_S
6044 2418518665U, // SQDMLSLi16
6045 2418518665U, // SQDMLSLi32
6046 2418513926U, // SQDMLSLv1i32_indexed
6047 2418519784U, // SQDMLSLv1i64_indexed
6048 1344508715U, // SQDMLSLv2i32_indexed
6049 1344508715U, // SQDMLSLv2i32_v2i64
6050 1344518643U, // SQDMLSLv4i16_indexed
6051 1344518643U, // SQDMLSLv4i16_v4i32
6052 1344508069U, // SQDMLSLv4i32_indexed
6053 1344508069U, // SQDMLSLv4i32_v2i64
6054 1344517582U, // SQDMLSLv8i16_indexed
6055 1344517582U, // SQDMLSLv8i16_v4i32
6056 1075947377U, // SQDMULH_ZZZI_D
6057 952248177U, // SQDMULH_ZZZI_H
6058 1881319281U, // SQDMULH_ZZZI_S
6059 1747003249U, // SQDMULH_ZZZ_B
6060 1075947377U, // SQDMULH_ZZZ_D
6061 952248177U, // SQDMULH_ZZZ_H
6062 1881319281U, // SQDMULH_ZZZ_S
6063 404793201U, // SQDMULHv1i16
6064 404789197U, // SQDMULHv1i16_indexed
6065 404793201U, // SQDMULHv1i32
6066 404795055U, // SQDMULHv1i32_indexed
6067 270741728U, // SQDMULHv2i32
6068 270741728U, // SQDMULHv2i32_indexed
6069 270735994U, // SQDMULHv4i16
6070 270735994U, // SQDMULHv4i16_indexed
6071 270743715U, // SQDMULHv4i32
6072 270743715U, // SQDMULHv4i32_indexed
6073 270737855U, // SQDMULHv8i16
6074 270737855U, // SQDMULHv8i16_indexed
6075 1881246714U, // SQDMULLB_ZZZI_D
6076 807570426U, // SQDMULLB_ZZZI_S
6077 1881246714U, // SQDMULLB_ZZZ_D
6078 1046612986U, // SQDMULLB_ZZZ_H
6079 807570426U, // SQDMULLB_ZZZ_S
6080 1881259901U, // SQDMULLT_ZZZI_D
6081 807583613U, // SQDMULLT_ZZZI_S
6082 1881259901U, // SQDMULLT_ZZZ_D
6083 1046626173U, // SQDMULLT_ZZZ_H
6084 807583613U, // SQDMULLT_ZZZ_S
6085 404793918U, // SQDMULLi16
6086 404793918U, // SQDMULLi32
6087 404789243U, // SQDMULLv1i32_indexed
6088 404795101U, // SQDMULLv1i64_indexed
6089 270734091U, // SQDMULLv2i32_indexed
6090 270734091U, // SQDMULLv2i32_v2i64
6091 270744019U, // SQDMULLv4i16_indexed
6092 270744019U, // SQDMULLv4i16_v4i32
6093 270733442U, // SQDMULLv4i32_indexed
6094 270733442U, // SQDMULLv4i32_v2i64
6095 270742955U, // SQDMULLv8i16_indexed
6096 270742955U, // SQDMULLv8i16_v4i32
6097 3491793605U, // SQINCB_XPiI
6098 1746963141U, // SQINCB_XPiWdI
6099 3491796501U, // SQINCD_XPiI
6100 1746966037U, // SQINCD_XPiWdI
6101 3491862037U, // SQINCD_ZPiI
6102 3491800737U, // SQINCH_XPiI
6103 1746970273U, // SQINCH_XPiWdI
6104 21112481U, // SQINCH_ZPiI
6105 1746971676U, // SQINCP_XPWd_B
6106 1075883036U, // SQINCP_XPWd_D
6107 807447580U, // SQINCP_XPWd_H
6108 1881189404U, // SQINCP_XPWd_S
6109 1746971676U, // SQINCP_XP_B
6110 1075883036U, // SQINCP_XP_D
6111 807447580U, // SQINCP_XP_H
6112 1881189404U, // SQINCP_XP_S
6113 539077660U, // SQINCP_ZP_D
6114 2166500380U, // SQINCP_ZP_H
6115 673360924U, // SQINCP_ZP_S
6116 3491807753U, // SQINCW_XPiI
6117 1746977289U, // SQINCW_XPiWdI
6118 3491938825U, // SQINCW_ZPiI
6119 2168722U, // SQNEG_ZPmZ_B
6120 2201490U, // SQNEG_ZPmZ_D
6121 138549138U, // SQNEG_ZPmZ_H
6122 2267026U, // SQNEG_ZPmZ_S
6123 270730357U, // SQNEGv16i8
6124 404789138U, // SQNEGv1i16
6125 404789138U, // SQNEGv1i32
6126 404789138U, // SQNEGv1i64
6127 404789138U, // SQNEGv1i8
6128 270741705U, // SQNEGv2i32
6129 270733812U, // SQNEGv2i64
6130 270735971U, // SQNEGv4i16
6131 270743680U, // SQNEGv4i32
6132 270737832U, // SQNEGv8i16
6133 270731223U, // SQNEGv8i8
6134 958539298U, // SQRDCMLAH_ZZZI_H
6135 673359394U, // SQRDCMLAH_ZZZI_S
6136 2820744738U, // SQRDCMLAH_ZZZ_B
6137 539076130U, // SQRDCMLAH_ZZZ_D
6138 958539298U, // SQRDCMLAH_ZZZ_H
6139 673359394U, // SQRDCMLAH_ZZZ_S
6140 539076141U, // SQRDMLAH_ZZZI_D
6141 958539309U, // SQRDMLAH_ZZZI_H
6142 673359405U, // SQRDMLAH_ZZZI_S
6143 2820744749U, // SQRDMLAH_ZZZ_B
6144 539076141U, // SQRDMLAH_ZZZ_D
6145 958539309U, // SQRDMLAH_ZZZ_H
6146 673359405U, // SQRDMLAH_ZZZ_S
6147 2418513857U, // SQRDMLAHi16_indexed
6148 2418519715U, // SQRDMLAHi32_indexed
6149 2418517549U, // SQRDMLAHv1i16
6150 2418517549U, // SQRDMLAHv1i32
6151 1344516307U, // SQRDMLAHv2i32
6152 1344516307U, // SQRDMLAHv2i32_indexed
6153 1344510573U, // SQRDMLAHv4i16
6154 1344510573U, // SQRDMLAHv4i16_indexed
6155 1344518294U, // SQRDMLAHv4i32
6156 1344518294U, // SQRDMLAHv4i32_indexed
6157 1344512434U, // SQRDMLAHv8i16
6158 1344512434U, // SQRDMLAHv8i16_indexed
6159 539076746U, // SQRDMLSH_ZZZI_D
6160 958539914U, // SQRDMLSH_ZZZI_H
6161 673360010U, // SQRDMLSH_ZZZI_S
6162 2820745354U, // SQRDMLSH_ZZZ_B
6163 539076746U, // SQRDMLSH_ZZZ_D
6164 958539914U, // SQRDMLSH_ZZZ_H
6165 673360010U, // SQRDMLSH_ZZZ_S
6166 2418513892U, // SQRDMLSHi16_indexed
6167 2418519750U, // SQRDMLSHi32_indexed
6168 2418518154U, // SQRDMLSHv1i16
6169 2418518154U, // SQRDMLSHv1i32
6170 1344516345U, // SQRDMLSHv2i32
6171 1344516345U, // SQRDMLSHv2i32_indexed
6172 1344510611U, // SQRDMLSHv4i16
6173 1344510611U, // SQRDMLSHv4i16_indexed
6174 1344518332U, // SQRDMLSHv4i32
6175 1344518332U, // SQRDMLSHv4i32_indexed
6176 1344512472U, // SQRDMLSHv8i16
6177 1344512472U, // SQRDMLSHv8i16_indexed
6178 1075947386U, // SQRDMULH_ZZZI_D
6179 952248186U, // SQRDMULH_ZZZI_H
6180 1881319290U, // SQRDMULH_ZZZI_S
6181 1747003258U, // SQRDMULH_ZZZ_B
6182 1075947386U, // SQRDMULH_ZZZ_D
6183 952248186U, // SQRDMULH_ZZZ_H
6184 1881319290U, // SQRDMULH_ZZZ_S
6185 404793210U, // SQRDMULHv1i16
6186 404789208U, // SQRDMULHv1i16_indexed
6187 404793210U, // SQRDMULHv1i32
6188 404795066U, // SQRDMULHv1i32_indexed
6189 270741740U, // SQRDMULHv2i32
6190 270741740U, // SQRDMULHv2i32_indexed
6191 270736006U, // SQRDMULHv4i16
6192 270736006U, // SQRDMULHv4i16_indexed
6193 270743727U, // SQRDMULHv4i32
6194 270743727U, // SQRDMULHv4i32_indexed
6195 270737867U, // SQRDMULHv8i16
6196 270737867U, // SQRDMULHv8i16_indexed
6197 1478569406U, // SQRSHLR_ZPmZ_B
6198 1478602174U, // SQRSHLR_ZPmZ_D
6199 1621241278U, // SQRSHLR_ZPmZ_H
6200 1478667710U, // SQRSHLR_ZPmZ_S
6201 1478568468U, // SQRSHL_ZPmZ_B
6202 1478601236U, // SQRSHL_ZPmZ_D
6203 1621240340U, // SQRSHL_ZPmZ_H
6204 1478666772U, // SQRSHL_ZPmZ_S
6205 270730428U, // SQRSHLv16i8
6206 404793876U, // SQRSHLv1i16
6207 404793876U, // SQRSHLv1i32
6208 404793876U, // SQRSHLv1i64
6209 404793876U, // SQRSHLv1i8
6210 270741840U, // SQRSHLv2i32
6211 270734011U, // SQRSHLv2i64
6212 270736106U, // SQRSHLv4i16
6213 270743939U, // SQRSHLv4i32
6214 270738067U, // SQRSHLv8i16
6215 270731287U, // SQRSHLv8i8
6216 807472330U, // SQRSHRNB_ZZI_B
6217 945949898U, // SQRSHRNB_ZZI_H
6218 1076006090U, // SQRSHRNB_ZZI_S
6219 1210138634U, // SQRSHRNT_ZZI_B
6220 948060170U, // SQRSHRNT_ZZI_H
6221 539148298U, // SQRSHRNT_ZZI_S
6222 404794231U, // SQRSHRNb
6223 404794231U, // SQRSHRNh
6224 404794231U, // SQRSHRNs
6225 1344504498U, // SQRSHRNv16i8_shift
6226 270742013U, // SQRSHRNv2i32_shift
6227 270736279U, // SQRSHRNv4i16_shift
6228 1344517665U, // SQRSHRNv4i32_shift
6229 1344511909U, // SQRSHRNv8i16_shift
6230 270731426U, // SQRSHRNv8i8_shift
6231 807472376U, // SQRSHRUNB_ZZI_B
6232 945949944U, // SQRSHRUNB_ZZI_H
6233 1076006136U, // SQRSHRUNB_ZZI_S
6234 1210138689U, // SQRSHRUNT_ZZI_B
6235 948060225U, // SQRSHRUNT_ZZI_H
6236 539148353U, // SQRSHRUNT_ZZI_S
6237 404794292U, // SQRSHRUNb
6238 404794292U, // SQRSHRUNh
6239 404794292U, // SQRSHRUNs
6240 1344504574U, // SQRSHRUNv16i8_shift
6241 270742080U, // SQRSHRUNv2i32_shift
6242 270736357U, // SQRSHRUNv4i16_shift
6243 1344517735U, // SQRSHRUNv4i32_shift
6244 1344511991U, // SQRSHRUNv8i16_shift
6245 270731490U, // SQRSHRUNv8i8_shift
6246 1478569390U, // SQSHLR_ZPmZ_B
6247 1478602158U, // SQSHLR_ZPmZ_D
6248 1621241262U, // SQSHLR_ZPmZ_H
6249 1478667694U, // SQSHLR_ZPmZ_S
6250 1478574311U, // SQSHLU_ZPmI_B
6251 1478607079U, // SQSHLU_ZPmI_D
6252 1621246183U, // SQSHLU_ZPmI_H
6253 1478672615U, // SQSHLU_ZPmI_S
6254 404799719U, // SQSHLUb
6255 404799719U, // SQSHLUd
6256 404799719U, // SQSHLUh
6257 404799719U, // SQSHLUs
6258 270730782U, // SQSHLUv16i8_shift
6259 270742501U, // SQSHLUv2i32_shift
6260 270734566U, // SQSHLUv2i64_shift
6261 270736778U, // SQSHLUv4i16_shift
6262 270744580U, // SQSHLUv4i32_shift
6263 270738674U, // SQSHLUv8i16_shift
6264 270731730U, // SQSHLUv8i8_shift
6265 1478568454U, // SQSHL_ZPmI_B
6266 1478601222U, // SQSHL_ZPmI_D
6267 1621240326U, // SQSHL_ZPmI_H
6268 1478666758U, // SQSHL_ZPmI_S
6269 1478568454U, // SQSHL_ZPmZ_B
6270 1478601222U, // SQSHL_ZPmZ_D
6271 1621240326U, // SQSHL_ZPmZ_H
6272 1478666758U, // SQSHL_ZPmZ_S
6273 404793862U, // SQSHLb
6274 404793862U, // SQSHLd
6275 404793862U, // SQSHLh
6276 404793862U, // SQSHLs
6277 270730406U, // SQSHLv16i8
6278 270730406U, // SQSHLv16i8_shift
6279 404793862U, // SQSHLv1i16
6280 404793862U, // SQSHLv1i32
6281 404793862U, // SQSHLv1i64
6282 404793862U, // SQSHLv1i8
6283 270741820U, // SQSHLv2i32
6284 270741820U, // SQSHLv2i32_shift
6285 270733991U, // SQSHLv2i64
6286 270733991U, // SQSHLv2i64_shift
6287 270736086U, // SQSHLv4i16
6288 270736086U, // SQSHLv4i16_shift
6289 270743919U, // SQSHLv4i32
6290 270743919U, // SQSHLv4i32_shift
6291 270738047U, // SQSHLv8i16
6292 270738047U, // SQSHLv8i16_shift
6293 270731267U, // SQSHLv8i8
6294 270731267U, // SQSHLv8i8_shift
6295 807472312U, // SQSHRNB_ZZI_B
6296 945949880U, // SQSHRNB_ZZI_H
6297 1076006072U, // SQSHRNB_ZZI_S
6298 1210138616U, // SQSHRNT_ZZI_B
6299 948060152U, // SQSHRNT_ZZI_H
6300 539148280U, // SQSHRNT_ZZI_S
6301 404794215U, // SQSHRNb
6302 404794215U, // SQSHRNh
6303 404794215U, // SQSHRNs
6304 1344504472U, // SQSHRNv16i8_shift
6305 270741991U, // SQSHRNv2i32_shift
6306 270736257U, // SQSHRNv4i16_shift
6307 1344517641U, // SQSHRNv4i32_shift
6308 1344511885U, // SQSHRNv8i16_shift
6309 270731404U, // SQSHRNv8i8_shift
6310 807472366U, // SQSHRUNB_ZZI_B
6311 945949934U, // SQSHRUNB_ZZI_H
6312 1076006126U, // SQSHRUNB_ZZI_S
6313 1210138679U, // SQSHRUNT_ZZI_B
6314 948060215U, // SQSHRUNT_ZZI_H
6315 539148343U, // SQSHRUNT_ZZI_S
6316 404794283U, // SQSHRUNb
6317 404794283U, // SQSHRUNh
6318 404794283U, // SQSHRUNs
6319 1344504560U, // SQSHRUNv16i8_shift
6320 270742068U, // SQSHRUNv2i32_shift
6321 270736345U, // SQSHRUNv4i16_shift
6322 1344517722U, // SQSHRUNv4i32_shift
6323 1344511978U, // SQSHRUNv8i16_shift
6324 270731478U, // SQSHRUNv8i8_shift
6325 1478569312U, // SQSUBR_ZPmZ_B
6326 1478602080U, // SQSUBR_ZPmZ_D
6327 1621241184U, // SQSUBR_ZPmZ_H
6328 1478667616U, // SQSUBR_ZPmZ_S
6329 1746996863U, // SQSUB_ZI_B
6330 1075940991U, // SQSUB_ZI_D
6331 952241791U, // SQSUB_ZI_H
6332 1881312895U, // SQSUB_ZI_S
6333 1478561407U, // SQSUB_ZPmZ_B
6334 1478594175U, // SQSUB_ZPmZ_D
6335 1621233279U, // SQSUB_ZPmZ_H
6336 1478659711U, // SQSUB_ZPmZ_S
6337 1746996863U, // SQSUB_ZZZ_B
6338 1075940991U, // SQSUB_ZZZ_D
6339 952241791U, // SQSUB_ZZZ_H
6340 1881312895U, // SQSUB_ZZZ_S
6341 270730155U, // SQSUBv16i8
6342 404786815U, // SQSUBv1i16
6343 404786815U, // SQSUBv1i32
6344 404786815U, // SQSUBv1i64
6345 404786815U, // SQSUBv1i8
6346 270741462U, // SQSUBv2i32
6347 270733660U, // SQSUBv2i64
6348 270735751U, // SQSUBv4i16
6349 270743418U, // SQSUBv4i32
6350 270737612U, // SQSUBv8i16
6351 270731079U, // SQSUBv8i8
6352 807472350U, // SQXTNB_ZZ_B
6353 2153909470U, // SQXTNB_ZZ_H
6354 1076006110U, // SQXTNB_ZZ_S
6355 1210138663U, // SQXTNT_ZZ_B
6356 2156019751U, // SQXTNT_ZZ_H
6357 539148327U, // SQXTNT_ZZ_S
6358 1344504536U, // SQXTNv16i8
6359 404794269U, // SQXTNv1i16
6360 404794269U, // SQXTNv1i32
6361 404794269U, // SQXTNv1i8
6362 270742048U, // SQXTNv2i32
6363 270736325U, // SQXTNv4i16
6364 1344517700U, // SQXTNv4i32
6365 1344511956U, // SQXTNv8i16
6366 270731458U, // SQXTNv8i8
6367 807472387U, // SQXTUNB_ZZ_B
6368 2153909507U, // SQXTUNB_ZZ_H
6369 1076006147U, // SQXTUNB_ZZ_S
6370 1210138700U, // SQXTUNT_ZZ_B
6371 2156019788U, // SQXTUNT_ZZ_H
6372 539148364U, // SQXTUNT_ZZ_S
6373 1344504589U, // SQXTUNv16i8
6374 404794302U, // SQXTUNv1i16
6375 404794302U, // SQXTUNv1i32
6376 404794302U, // SQXTUNv1i8
6377 270742093U, // SQXTUNv2i32
6378 270736370U, // SQXTUNv4i16
6379 1344517749U, // SQXTUNv4i32
6380 1344512005U, // SQXTUNv8i16
6381 270731503U, // SQXTUNv8i8
6382 1478563393U, // SRHADD_ZPmZ_B
6383 1478596161U, // SRHADD_ZPmZ_D
6384 1621235265U, // SRHADD_ZPmZ_H
6385 1478661697U, // SRHADD_ZPmZ_S
6386 270730229U, // SRHADDv16i8
6387 270741536U, // SRHADDv2i32
6388 270735825U, // SRHADDv4i16
6389 270743502U, // SRHADDv4i32
6390 270737686U, // SRHADDv8i16
6391 270731125U, // SRHADDv8i8
6392 2820745521U, // SRI_ZZI_B
6393 539076913U, // SRI_ZZI_D
6394 958540081U, // SRI_ZZI_H
6395 673360177U, // SRI_ZZI_S
6396 2418518321U, // SRId
6397 1344504979U, // SRIv16i8_shift
6398 1344516384U, // SRIv2i32_shift
6399 1344508443U, // SRIv2i64_shift
6400 1344510650U, // SRIv4i16_shift
6401 1344518371U, // SRIv4i32_shift
6402 1344512511U, // SRIv8i16_shift
6403 1344505842U, // SRIv8i8_shift
6404 1478569424U, // SRSHLR_ZPmZ_B
6405 1478602192U, // SRSHLR_ZPmZ_D
6406 1621241296U, // SRSHLR_ZPmZ_H
6407 1478667728U, // SRSHLR_ZPmZ_S
6408 1478568484U, // SRSHL_ZPmZ_B
6409 1478601252U, // SRSHL_ZPmZ_D
6410 1621240356U, // SRSHL_ZPmZ_H
6411 1478666788U, // SRSHL_ZPmZ_S
6412 270730452U, // SRSHLv16i8
6413 404793892U, // SRSHLv1i64
6414 270741862U, // SRSHLv2i32
6415 270734033U, // SRSHLv2i64
6416 270736128U, // SRSHLv4i16
6417 270743961U, // SRSHLv4i32
6418 270738089U, // SRSHLv8i16
6419 270731309U, // SRSHLv8i8
6420 1478569352U, // SRSHR_ZPmI_B
6421 1478602120U, // SRSHR_ZPmI_D
6422 1621241224U, // SRSHR_ZPmI_H
6423 1478667656U, // SRSHR_ZPmI_S
6424 404794760U, // SRSHRd
6425 270730615U, // SRSHRv16i8_shift
6426 270742271U, // SRSHRv2i32_shift
6427 270734352U, // SRSHRv2i64_shift
6428 270736548U, // SRSHRv4i16_shift
6429 270744350U, // SRSHRv4i32_shift
6430 270738444U, // SRSHRv8i16_shift
6431 270731580U, // SRSHRv8i8_shift
6432 2820735342U, // SRSRA_ZZI_B
6433 539066734U, // SRSRA_ZZI_D
6434 958529902U, // SRSRA_ZZI_H
6435 673349998U, // SRSRA_ZZI_S
6436 2418508142U, // SRSRAd
6437 1344504683U, // SRSRAv16i8_shift
6438 1344515976U, // SRSRAv2i32_shift
6439 1344508194U, // SRSRAv2i64_shift
6440 1344510265U, // SRSRAv4i16_shift
6441 1344517908U, // SRSRAv4i32_shift
6442 1344512126U, // SRSRAv8i16_shift
6443 1344505613U, // SRSRAv8i8_shift
6444 1881246698U, // SSHLLB_ZZI_D
6445 1046612970U, // SSHLLB_ZZI_H
6446 807570410U, // SSHLLB_ZZI_S
6447 1881259885U, // SSHLLT_ZZI_D
6448 1046626157U, // SSHLLT_ZZI_H
6449 807583597U, // SSHLLT_ZZI_S
6450 270737192U, // SSHLLv16i8_shift
6451 270734071U, // SSHLLv2i32_shift
6452 270743999U, // SSHLLv4i16_shift
6453 270733420U, // SSHLLv4i32_shift
6454 270742933U, // SSHLLv8i16_shift
6455 270738127U, // SSHLLv8i8_shift
6456 270730474U, // SSHLv16i8
6457 404793906U, // SSHLv1i64
6458 270741882U, // SSHLv2i32
6459 270734053U, // SSHLv2i64
6460 270736148U, // SSHLv4i16
6461 270743981U, // SSHLv4i32
6462 270738109U, // SSHLv8i16
6463 270731329U, // SSHLv8i8
6464 404794774U, // SSHRd
6465 270730637U, // SSHRv16i8_shift
6466 270742291U, // SSHRv2i32_shift
6467 270734372U, // SSHRv2i64_shift
6468 270736568U, // SSHRv4i16_shift
6469 270744370U, // SSHRv4i32_shift
6470 270738464U, // SSHRv8i16_shift
6471 270731600U, // SSHRv8i8_shift
6472 2820735356U, // SSRA_ZZI_B
6473 539066748U, // SSRA_ZZI_D
6474 958529916U, // SSRA_ZZI_H
6475 673350012U, // SSRA_ZZI_S
6476 2418508156U, // SSRAd
6477 1344504705U, // SSRAv16i8_shift
6478 1344515996U, // SSRAv2i32_shift
6479 1344508214U, // SSRAv2i64_shift
6480 1344510285U, // SSRAv4i16_shift
6481 1344517928U, // SSRAv4i32_shift
6482 1344512146U, // SSRAv8i16_shift
6483 1344505633U, // SSRAv8i8_shift
6484 552239637U, // SST1B_D_IMM
6485 2431287829U, // SST1B_D_REAL
6486 2431287829U, // SST1B_D_SXTW
6487 2431287829U, // SST1B_D_UXTW
6488 686490133U, // SST1B_S_IMM
6489 2431320597U, // SST1B_S_SXTW
6490 2431320597U, // SST1B_S_UXTW
6491 552243102U, // SST1D_IMM
6492 2431291294U, // SST1D_REAL
6493 2431291294U, // SST1D_SCALED_SCALED_REAL
6494 2431291294U, // SST1D_SXTW
6495 2431291294U, // SST1D_SXTW_SCALED
6496 2431291294U, // SST1D_UXTW
6497 2431291294U, // SST1D_UXTW_SCALED
6498 552245358U, // SST1H_D_IMM
6499 2431293550U, // SST1H_D_REAL
6500 2431293550U, // SST1H_D_SCALED_SCALED_REAL
6501 2431293550U, // SST1H_D_SXTW
6502 2431293550U, // SST1H_D_SXTW_SCALED
6503 2431293550U, // SST1H_D_UXTW
6504 2431293550U, // SST1H_D_UXTW_SCALED
6505 686495854U, // SST1H_S_IMM
6506 2431326318U, // SST1H_S_SXTW
6507 2431326318U, // SST1H_S_SXTW_SCALED
6508 2431326318U, // SST1H_S_UXTW
6509 2431326318U, // SST1H_S_UXTW_SCALED
6510 552255934U, // SST1W_D_IMM
6511 2431304126U, // SST1W_D_REAL
6512 2431304126U, // SST1W_D_SCALED_SCALED_REAL
6513 2431304126U, // SST1W_D_SXTW
6514 2431304126U, // SST1W_D_SXTW_SCALED
6515 2431304126U, // SST1W_D_UXTW
6516 2431304126U, // SST1W_D_UXTW_SCALED
6517 686506430U, // SST1W_IMM
6518 2431336894U, // SST1W_SXTW
6519 2431336894U, // SST1W_SXTW_SCALED
6520 2431336894U, // SST1W_UXTW
6521 2431336894U, // SST1W_UXTW_SCALED
6522 1881259653U, // SSUBLBT_ZZZ_D
6523 1046625925U, // SSUBLBT_ZZZ_H
6524 807583365U, // SSUBLBT_ZZZ_S
6525 1881246627U, // SSUBLB_ZZZ_D
6526 1046612899U, // SSUBLB_ZZZ_H
6527 807570339U, // SSUBLB_ZZZ_S
6528 1881247282U, // SSUBLTB_ZZZ_D
6529 1046613554U, // SSUBLTB_ZZZ_H
6530 807570994U, // SSUBLTB_ZZZ_S
6531 1881259809U, // SSUBLT_ZZZ_D
6532 1046626081U, // SSUBLT_ZZZ_H
6533 807583521U, // SSUBLT_ZZZ_S
6534 270737126U, // SSUBLv16i8_v8i16
6535 270733931U, // SSUBLv2i32_v2i64
6536 270743859U, // SSUBLv4i16_v4i32
6537 270733354U, // SSUBLv4i32_v2i64
6538 270742867U, // SSUBLv8i16_v4i32
6539 270737987U, // SSUBLv8i8_v8i16
6540 1075941011U, // SSUBWB_ZZZ_D
6541 952241811U, // SSUBWB_ZZZ_H
6542 1881312915U, // SSUBWB_ZZZ_S
6543 1075953842U, // SSUBWT_ZZZ_D
6544 952254642U, // SSUBWT_ZZZ_H
6545 1881325746U, // SSUBWT_ZZZ_S
6546 270737443U, // SSUBWv16i8_v8i16
6547 270734639U, // SSUBWv2i32_v2i64
6548 270744768U, // SSUBWv4i16_v4i32
6549 270733539U, // SSUBWv4i32_v2i64
6550 270743187U, // SSUBWv8i16_v4i32
6551 270738862U, // SSUBWv8i8_v8i16
6552 2431386133U, // ST1B
6553 2431287829U, // ST1B_D
6554 2431287829U, // ST1B_D_IMM
6555 2431418901U, // ST1B_H
6556 2431418901U, // ST1B_H_IMM
6557 2431386133U, // ST1B_IMM
6558 2431320597U, // ST1B_S
6559 2431320597U, // ST1B_S_IMM
6560 2431291294U, // ST1D
6561 2431291294U, // ST1D_IMM
6562 852008U, // ST1Fourv16b
6563 59605032U, // ST1Fourv16b_POST
6564 917544U, // ST1Fourv1d
6565 61767720U, // ST1Fourv1d_POST
6566 983080U, // ST1Fourv2d
6567 59736104U, // ST1Fourv2d_POST
6568 1048616U, // ST1Fourv2s
6569 61898792U, // ST1Fourv2s_POST
6570 1114152U, // ST1Fourv4h
6571 61964328U, // ST1Fourv4h_POST
6572 1179688U, // ST1Fourv4s
6573 59932712U, // ST1Fourv4s_POST
6574 1245224U, // ST1Fourv8b
6575 62095400U, // ST1Fourv8b_POST
6576 1310760U, // ST1Fourv8h
6577 60063784U, // ST1Fourv8h_POST
6578 2431424622U, // ST1H
6579 2431293550U, // ST1H_D
6580 2431293550U, // ST1H_D_IMM
6581 2431424622U, // ST1H_IMM
6582 2431326318U, // ST1H_S
6583 2431326318U, // ST1H_S_IMM
6584 852008U, // ST1Onev16b
6585 63799336U, // ST1Onev16b_POST
6586 917544U, // ST1Onev1d
6587 65962024U, // ST1Onev1d_POST
6588 983080U, // ST1Onev2d
6589 63930408U, // ST1Onev2d_POST
6590 1048616U, // ST1Onev2s
6591 66093096U, // ST1Onev2s_POST
6592 1114152U, // ST1Onev4h
6593 66158632U, // ST1Onev4h_POST
6594 1179688U, // ST1Onev4s
6595 64127016U, // ST1Onev4s_POST
6596 1245224U, // ST1Onev8b
6597 66289704U, // ST1Onev8b_POST
6598 1310760U, // ST1Onev8h
6599 64258088U, // ST1Onev8h_POST
6600 852008U, // ST1Threev16b
6601 74285096U, // ST1Threev16b_POST
6602 917544U, // ST1Threev1d
6603 76447784U, // ST1Threev1d_POST
6604 983080U, // ST1Threev2d
6605 74416168U, // ST1Threev2d_POST
6606 1048616U, // ST1Threev2s
6607 76578856U, // ST1Threev2s_POST
6608 1114152U, // ST1Threev4h
6609 76644392U, // ST1Threev4h_POST
6610 1179688U, // ST1Threev4s
6611 74612776U, // ST1Threev4s_POST
6612 1245224U, // ST1Threev8b
6613 76775464U, // ST1Threev8b_POST
6614 1310760U, // ST1Threev8h
6615 74743848U, // ST1Threev8h_POST
6616 852008U, // ST1Twov16b
6617 61702184U, // ST1Twov16b_POST
6618 917544U, // ST1Twov1d
6619 63864872U, // ST1Twov1d_POST
6620 983080U, // ST1Twov2d
6621 61833256U, // ST1Twov2d_POST
6622 1048616U, // ST1Twov2s
6623 63995944U, // ST1Twov2s_POST
6624 1114152U, // ST1Twov4h
6625 64061480U, // ST1Twov4h_POST
6626 1179688U, // ST1Twov4s
6627 62029864U, // ST1Twov4s_POST
6628 1245224U, // ST1Twov8b
6629 64192552U, // ST1Twov8b_POST
6630 1310760U, // ST1Twov8h
6631 62160936U, // ST1Twov8h_POST
6632 2431336894U, // ST1W
6633 2431304126U, // ST1W_D
6634 2431304126U, // ST1W_D_IMM
6635 2431336894U, // ST1W_IMM
6636 1835048U, // ST1i16
6637 1995767848U, // ST1i16_POST
6638 1867816U, // ST1i32
6639 2130051112U, // ST1i32_POST
6640 1900584U, // ST1i64
6641 2264334376U, // ST1i64_POST
6642 1933352U, // ST1i8
6643 2398617640U, // ST1i8_POST
6644 2431386153U, // ST2B
6645 2431386153U, // ST2B_IMM
6646 2431292858U, // ST2D
6647 2431292858U, // ST2D_IMM
6648 417372014U, // ST2GOffset
6649 2431096686U, // ST2GPostIndex
6650 2431096686U, // ST2GPreIndex
6651 2431424696U, // ST2H
6652 2431424696U, // ST2H_IMM
6653 852097U, // ST2Twov16b
6654 61702273U, // ST2Twov16b_POST
6655 983169U, // ST2Twov2d
6656 61833345U, // ST2Twov2d_POST
6657 1048705U, // ST2Twov2s
6658 63996033U, // ST2Twov2s_POST
6659 1114241U, // ST2Twov4h
6660 64061569U, // ST2Twov4h_POST
6661 1179777U, // ST2Twov4s
6662 62029953U, // ST2Twov4s_POST
6663 1245313U, // ST2Twov8b
6664 64192641U, // ST2Twov8b_POST
6665 1310849U, // ST2Twov8h
6666 62161025U, // ST2Twov8h_POST
6667 2431336914U, // ST2W
6668 2431336914U, // ST2W_IMM
6669 1835137U, // ST2i16
6670 2129985665U, // ST2i16_POST
6671 1867905U, // ST2i32
6672 2264268929U, // ST2i32_POST
6673 1900673U, // ST2i64
6674 2532769921U, // ST2i64_POST
6675 1933441U, // ST2i8
6676 1995964545U, // ST2i8_POST
6677 2431386165U, // ST3B
6678 2431386165U, // ST3B_IMM
6679 2431292870U, // ST3D
6680 2431292870U, // ST3D_IMM
6681 2431424708U, // ST3H
6682 2431424708U, // ST3H_IMM
6683 852120U, // ST3Threev16b
6684 74285208U, // ST3Threev16b_POST
6685 983192U, // ST3Threev2d
6686 74416280U, // ST3Threev2d_POST
6687 1048728U, // ST3Threev2s
6688 76578968U, // ST3Threev2s_POST
6689 1114264U, // ST3Threev4h
6690 76644504U, // ST3Threev4h_POST
6691 1179800U, // ST3Threev4s
6692 74612888U, // ST3Threev4s_POST
6693 1245336U, // ST3Threev8b
6694 76775576U, // ST3Threev8b_POST
6695 1310872U, // ST3Threev8h
6696 74743960U, // ST3Threev8h_POST
6697 2431336926U, // ST3W
6698 2431336926U, // ST3W_IMM
6699 1835160U, // ST3i16
6700 2666856600U, // ST3i16_POST
6701 1867928U, // ST3i32
6702 2801139864U, // ST3i32_POST
6703 1900696U, // ST3i64
6704 2935423128U, // ST3i64_POST
6705 1933464U, // ST3i8
6706 3069706392U, // ST3i8_POST
6707 2431386191U, // ST4B
6708 2431386191U, // ST4B_IMM
6709 2431292882U, // ST4D
6710 2431292882U, // ST4D_IMM
6711 852130U, // ST4Fourv16b
6712 59605154U, // ST4Fourv16b_POST
6713 983202U, // ST4Fourv2d
6714 59736226U, // ST4Fourv2d_POST
6715 1048738U, // ST4Fourv2s
6716 61898914U, // ST4Fourv2s_POST
6717 1114274U, // ST4Fourv4h
6718 61964450U, // ST4Fourv4h_POST
6719 1179810U, // ST4Fourv4s
6720 59932834U, // ST4Fourv4s_POST
6721 1245346U, // ST4Fourv8b
6722 62095522U, // ST4Fourv8b_POST
6723 1310882U, // ST4Fourv8h
6724 60063906U, // ST4Fourv8h_POST
6725 2431426191U, // ST4H
6726 2431426191U, // ST4H_IMM
6727 2431336938U, // ST4W
6728 2431336938U, // ST4W_IMM
6729 1835170U, // ST4i16
6730 2264203426U, // ST4i16_POST
6731 1867938U, // ST4i32
6732 2532704418U, // ST4i32_POST
6733 1900706U, // ST4i64
6734 3203858594U, // ST4i64_POST
6735 1933474U, // ST4i8
6736 2130182306U, // ST4i8_POST
6737 1638978U, // ST64B
6738 3223372047U, // ST64BV
6739 3223355393U, // ST64BV0
6740 417377024U, // STGM
6741 417372078U, // STGOffset
6742 404794430U, // STGPi
6743 2431096750U, // STGPostIndex
6744 2418519102U, // STGPpost
6745 2418519102U, // STGPpre
6746 2431096750U, // STGPreIndex
6747 417369421U, // STLLRB
6748 417376242U, // STLLRH
6749 417377760U, // STLLRW
6750 417377760U, // STLLRX
6751 417369429U, // STLRB
6752 417376250U, // STLRH
6753 417377773U, // STLRW
6754 417377773U, // STLRX
6755 417369479U, // STLURBi
6756 417376300U, // STLURHi
6757 417377870U, // STLURWi
6758 417377870U, // STLURXi
6759 404794598U, // STLXPW
6760 404794598U, // STLXPX
6761 404786606U, // STLXRB
6762 404793427U, // STLXRH
6763 404795022U, // STLXRW
6764 404795022U, // STLXRX
6765 404794510U, // STNPDi
6766 404794510U, // STNPQi
6767 404794510U, // STNPSi
6768 404794510U, // STNPWi
6769 404794510U, // STNPXi
6770 2431386125U, // STNT1B_ZRI
6771 2431386125U, // STNT1B_ZRR
6772 552239629U, // STNT1B_ZZR_D_REAL
6773 686490125U, // STNT1B_ZZR_S_REAL
6774 2431291286U, // STNT1D_ZRI
6775 2431291286U, // STNT1D_ZRR
6776 552243094U, // STNT1D_ZZR_D_REAL
6777 2431424614U, // STNT1H_ZRI
6778 2431424614U, // STNT1H_ZRR
6779 552245350U, // STNT1H_ZZR_D_REAL
6780 686495846U, // STNT1H_ZZR_S_REAL
6781 2431336886U, // STNT1W_ZRI
6782 2431336886U, // STNT1W_ZRR
6783 552255926U, // STNT1W_ZZR_D_REAL
6784 686506422U, // STNT1W_ZZR_S_REAL
6785 404794548U, // STPDi
6786 2418519220U, // STPDpost
6787 2418519220U, // STPDpre
6788 404794548U, // STPQi
6789 2418519220U, // STPQpost
6790 2418519220U, // STPQpre
6791 404794548U, // STPSi
6792 2418519220U, // STPSpost
6793 2418519220U, // STPSpre
6794 404794548U, // STPWi
6795 2418519220U, // STPWpost
6796 2418519220U, // STPWpre
6797 404794548U, // STPXi
6798 2418519220U, // STPXpost
6799 2418519220U, // STPXpre
6800 2431094131U, // STRBBpost
6801 2431094131U, // STRBBpre
6802 417369459U, // STRBBroW
6803 417369459U, // STRBBroX
6804 417369459U, // STRBBui
6805 2431102519U, // STRBpost
6806 2431102519U, // STRBpre
6807 417377847U, // STRBroW
6808 417377847U, // STRBroX
6809 417377847U, // STRBui
6810 2431102519U, // STRDpost
6811 2431102519U, // STRDpre
6812 417377847U, // STRDroW
6813 417377847U, // STRDroX
6814 417377847U, // STRDui
6815 2431100952U, // STRHHpost
6816 2431100952U, // STRHHpre
6817 417376280U, // STRHHroW
6818 417376280U, // STRHHroX
6819 417376280U, // STRHHui
6820 2431102519U, // STRHpost
6821 2431102519U, // STRHpre
6822 417377847U, // STRHroW
6823 417377847U, // STRHroX
6824 417377847U, // STRHui
6825 2431102519U, // STRQpost
6826 2431102519U, // STRQpre
6827 417377847U, // STRQroW
6828 417377847U, // STRQroX
6829 417377847U, // STRQui
6830 2431102519U, // STRSpost
6831 2431102519U, // STRSpre
6832 417377847U, // STRSroW
6833 417377847U, // STRSroX
6834 417377847U, // STRSui
6835 2431102519U, // STRWpost
6836 2431102519U, // STRWpre
6837 417377847U, // STRWroW
6838 417377847U, // STRWroX
6839 417377847U, // STRWui
6840 2431102519U, // STRXpost
6841 2431102519U, // STRXpre
6842 417377847U, // STRXroW
6843 417377847U, // STRXroX
6844 417377847U, // STRXui
6845 419016247U, // STR_PXI
6846 419016247U, // STR_ZXI
6847 417369465U, // STTRBi
6848 417376286U, // STTRHi
6849 417377852U, // STTRWi
6850 417377852U, // STTRXi
6851 417369496U, // STURBBi
6852 417377885U, // STURBi
6853 417377885U, // STURDi
6854 417376317U, // STURHHi
6855 417377885U, // STURHi
6856 417377885U, // STURQi
6857 417377885U, // STURSi
6858 417377885U, // STURWi
6859 417377885U, // STURXi
6860 404794605U, // STXPW
6861 404794605U, // STXPX
6862 404786614U, // STXRB
6863 404793435U, // STXRH
6864 404795029U, // STXRW
6865 404795029U, // STXRX
6866 417372020U, // STZ2GOffset
6867 2431096692U, // STZ2GPostIndex
6868 2431096692U, // STZ2GPreIndex
6869 417377030U, // STZGM
6870 417372083U, // STZGOffset
6871 2431096755U, // STZGPostIndex
6872 2431096755U, // STZGPreIndex
6873 404789115U, // SUBG
6874 807472277U, // SUBHNB_ZZZ_B
6875 945949845U, // SUBHNB_ZZZ_H
6876 1076006037U, // SUBHNB_ZZZ_S
6877 1210138593U, // SUBHNT_ZZZ_B
6878 948060129U, // SUBHNT_ZZZ_H
6879 539148257U, // SUBHNT_ZZZ_S
6880 270741943U, // SUBHNv2i64_v2i32
6881 1344517618U, // SUBHNv2i64_v4i32
6882 270736209U, // SUBHNv4i32_v4i16
6883 1344511862U, // SUBHNv4i32_v8i16
6884 1344504447U, // SUBHNv8i16_v16i8
6885 270731365U, // SUBHNv8i16_v8i8
6886 404794374U, // SUBP
6887 404799013U, // SUBPS
6888 1747004746U, // SUBR_ZI_B
6889 1075948874U, // SUBR_ZI_D
6890 952249674U, // SUBR_ZI_H
6891 1881320778U, // SUBR_ZI_S
6892 1478569290U, // SUBR_ZPmZ_B
6893 1478602058U, // SUBR_ZPmZ_D
6894 1621241162U, // SUBR_ZPmZ_H
6895 1478667594U, // SUBR_ZPmZ_S
6896 404798883U, // SUBSWri
6897 404798883U, // SUBSWrs
6898 404798883U, // SUBSWrx
6899 404798883U, // SUBSXri
6900 404798883U, // SUBSXrs
6901 404798883U, // SUBSXrx
6902 404798883U, // SUBSXrx64
6903 404786781U, // SUBWri
6904 404786781U, // SUBWrs
6905 404786781U, // SUBWrx
6906 404786781U, // SUBXri
6907 404786781U, // SUBXrs
6908 404786781U, // SUBXrx
6909 404786781U, // SUBXrx64
6910 1746996829U, // SUB_ZI_B
6911 1075940957U, // SUB_ZI_D
6912 952241757U, // SUB_ZI_H
6913 1881312861U, // SUB_ZI_S
6914 1478561373U, // SUB_ZPmZ_B
6915 1478594141U, // SUB_ZPmZ_D
6916 1621233245U, // SUB_ZPmZ_H
6917 1478659677U, // SUB_ZPmZ_S
6918 1746996829U, // SUB_ZZZ_B
6919 1075940957U, // SUB_ZZZ_D
6920 952241757U, // SUB_ZZZ_H
6921 1881312861U, // SUB_ZZZ_S
6922 270730135U, // SUBv16i8
6923 404786781U, // SUBv1i64
6924 270741434U, // SUBv2i32
6925 270733652U, // SUBv2i64
6926 270735723U, // SUBv4i16
6927 270743390U, // SUBv4i32
6928 270737584U, // SUBv8i16
6929 270731061U, // SUBv8i8
6930 2820849778U, // SUDOT_ZZZI
6931 1344520306U, // SUDOTlanev16i8
6932 1344520306U, // SUDOTlanev8i8
6933 1881254152U, // SUNPKHI_ZZ_D
6934 2254579976U, // SUNPKHI_ZZ_H
6935 807577864U, // SUNPKHI_ZZ_S
6936 1881254886U, // SUNPKLO_ZZ_D
6937 2254580710U, // SUNPKLO_ZZ_H
6938 807578598U, // SUNPKLO_ZZ_S
6939 1478563446U, // SUQADD_ZPmZ_B
6940 1478596214U, // SUQADD_ZPmZ_D
6941 1621235318U, // SUQADD_ZPmZ_H
6942 1478661750U, // SUQADD_ZPmZ_S
6943 1344504879U, // SUQADDv16i8
6944 2418513526U, // SUQADDv1i16
6945 2418513526U, // SUQADDv1i32
6946 2418513526U, // SUQADDv1i64
6947 2418513526U, // SUQADDv1i8
6948 1344516181U, // SUQADDv2i32
6949 1344508311U, // SUQADDv2i64
6950 1344510470U, // SUQADDv4i16
6951 1344518147U, // SUQADDv4i32
6952 1344512331U, // SUQADDv8i16
6953 1344505770U, // SUQADDv8i8
6954 429839U, // SVC
6955 1210550875U, // SWPAB
6956 1210558027U, // SWPAH
6957 1210551135U, // SWPALB
6958 1210558183U, // SWPALH
6959 1210558852U, // SWPALW
6960 1210558852U, // SWPALX
6961 1210548561U, // SWPAW
6962 1210548561U, // SWPAX
6963 1210551579U, // SWPB
6964 1210558400U, // SWPH
6965 1210551344U, // SWPLB
6966 1210558280U, // SWPLH
6967 1210559079U, // SWPLW
6968 1210559079U, // SWPLX
6969 1210559679U, // SWPW
6970 1210559679U, // SWPX
6971 2199120U, // SXTB_ZPmZ_D
6972 138546768U, // SXTB_ZPmZ_H
6973 2264656U, // SXTB_ZPmZ_S
6974 2205899U, // SXTH_ZPmZ_D
6975 2271435U, // SXTH_ZPmZ_S
6976 2212503U, // SXTW_ZPmZ_D
6977 404794009U, // SYSLxt
6978 3357589092U, // SYSxt
6979 2173377U, // TBL_ZZZZ_B
6980 3491867073U, // TBL_ZZZZ_D
6981 117582273U, // TBL_ZZZZ_H
6982 3626150337U, // TBL_ZZZZ_S
6983 2173377U, // TBL_ZZZ_B
6984 3491867073U, // TBL_ZZZ_D
6985 117582273U, // TBL_ZZZ_H
6986 3626150337U, // TBL_ZZZ_S
6987 3877841345U, // TBLv16i8Four
6988 3877841345U, // TBLv16i8One
6989 3877841345U, // TBLv16i8Three
6990 3877841345U, // TBLv16i8Two
6991 3879938497U, // TBLv8i8Four
6992 3879938497U, // TBLv8i8One
6993 3879938497U, // TBLv8i8Three
6994 3879938497U, // TBLv8i8Two
6995 404800378U, // TBNZW
6996 404800378U, // TBNZX
6997 2820752097U, // TBX_ZZZ_B
6998 539083489U, // TBX_ZZZ_D
6999 958546657U, // TBX_ZZZ_H
7000 673366753U, // TBX_ZZZ_S
7001 4012098273U, // TBXv16i8Four
7002 4012098273U, // TBXv16i8One
7003 4012098273U, // TBXv16i8Three
7004 4012098273U, // TBXv16i8Two
7005 4014195425U, // TBXv8i8Four
7006 4014195425U, // TBXv8i8One
7007 4014195425U, // TBXv8i8Three
7008 4014195425U, // TBXv8i8Two
7009 404800362U, // TBZW
7010 404800362U, // TBZX
7011 436718U, // TCANCEL
7012 17807U, // TCOMMIT
7013 1746993167U, // TRN1_PPP_B
7014 1075937295U, // TRN1_PPP_D
7015 952238095U, // TRN1_PPP_H
7016 1881309199U, // TRN1_PPP_S
7017 1746993167U, // TRN1_ZZZ_B
7018 1075937295U, // TRN1_ZZZ_D
7019 952238095U, // TRN1_ZZZ_H
7020 967442447U, // TRN1_ZZZ_Q
7021 1881309199U, // TRN1_ZZZ_S
7022 270729813U, // TRN1v16i8
7023 270741283U, // TRN1v2i32
7024 270733234U, // TRN1v2i64
7025 270735562U, // TRN1v4i16
7026 270742719U, // TRN1v4i32
7027 270737045U, // TRN1v8i16
7028 270730911U, // TRN1v8i8
7029 1746993239U, // TRN2_PPP_B
7030 1075937367U, // TRN2_PPP_D
7031 952238167U, // TRN2_PPP_H
7032 1881309271U, // TRN2_PPP_S
7033 1746993239U, // TRN2_ZZZ_B
7034 1075937367U, // TRN2_ZZZ_D
7035 952238167U, // TRN2_ZZZ_H
7036 967442519U, // TRN2_ZZZ_Q
7037 1881309271U, // TRN2_ZZZ_S
7038 270729934U, // TRN2v16i8
7039 270741310U, // TRN2v2i32
7040 270733512U, // TRN2v2i64
7041 270735599U, // TRN2v4i16
7042 270743099U, // TRN2v4i32
7043 270737343U, // TRN2v8i16
7044 270730948U, // TRN2v8i8
7045 593445U, // TSB
7046 49279U, // TSTART
7047 49301U, // TTEST
7048 673286932U, // UABALB_ZZZ_D
7049 1052904212U, // UABALB_ZZZ_H
7050 1210223380U, // UABALB_ZZZ_S
7051 673300214U, // UABALT_ZZZ_D
7052 1052917494U, // UABALT_ZZZ_H
7053 1210236662U, // UABALT_ZZZ_S
7054 1344511685U, // UABALv16i8_v8i16
7055 1344508481U, // UABALv2i32_v2i64
7056 1344518409U, // UABALv4i16_v4i32
7057 1344507900U, // UABALv4i32_v2i64
7058 1344517413U, // UABALv8i16_v4i32
7059 1344512549U, // UABALv8i8_v8i16
7060 2820735176U, // UABA_ZZZ_B
7061 539066568U, // UABA_ZZZ_D
7062 958529736U, // UABA_ZZZ_H
7063 673349832U, // UABA_ZZZ_S
7064 1344504664U, // UABAv16i8
7065 1344515948U, // UABAv2i32
7066 1344510237U, // UABAv4i16
7067 1344517880U, // UABAv4i32
7068 1344512098U, // UABAv8i16
7069 1344505596U, // UABAv8i8
7070 1881246665U, // UABDLB_ZZZ_D
7071 1046612937U, // UABDLB_ZZZ_H
7072 807570377U, // UABDLB_ZZZ_S
7073 1881259847U, // UABDLT_ZZZ_D
7074 1046626119U, // UABDLT_ZZZ_H
7075 807583559U, // UABDLT_ZZZ_S
7076 270737159U, // UABDLv16i8_v8i16
7077 270733961U, // UABDLv2i32_v2i64
7078 270743889U, // UABDLv4i16_v4i32
7079 270733387U, // UABDLv4i32_v2i64
7080 270742900U, // UABDLv8i16_v4i32
7081 270738017U, // UABDLv8i8_v8i16
7082 1478563320U, // UABD_ZPmZ_B
7083 1478596088U, // UABD_ZPmZ_D
7084 1621235192U, // UABD_ZPmZ_H
7085 1478661624U, // UABD_ZPmZ_S
7086 270730219U, // UABDv16i8
7087 270741508U, // UABDv2i32
7088 270735797U, // UABDv4i16
7089 270743474U, // UABDv4i32
7090 270737658U, // UABDv8i16
7091 270731116U, // UABDv8i8
7092 1478601804U, // UADALP_ZPmZ_D
7093 1621240908U, // UADALP_ZPmZ_H
7094 1478667340U, // UADALP_ZPmZ_S
7095 1344512890U, // UADALPv16i8_v8i16
7096 1344507735U, // UADALPv2i32_v1i64
7097 1344516717U, // UADALPv4i16_v2i32
7098 1344508830U, // UADALPv4i32_v2i64
7099 1344518796U, // UADALPv8i16_v4i32
7100 1344510994U, // UADALPv8i8_v4i16
7101 1881246690U, // UADDLB_ZZZ_D
7102 1046612962U, // UADDLB_ZZZ_H
7103 807570402U, // UADDLB_ZZZ_S
7104 270738320U, // UADDLPv16i8_v8i16
7105 270733165U, // UADDLPv2i32_v1i64
7106 270742147U, // UADDLPv4i16_v2i32
7107 270734260U, // UADDLPv4i32_v2i64
7108 270744226U, // UADDLPv8i16_v4i32
7109 270736424U, // UADDLPv8i8_v4i16
7110 1881259863U, // UADDLT_ZZZ_D
7111 1046626135U, // UADDLT_ZZZ_H
7112 807583575U, // UADDLT_ZZZ_S
7113 270566976U, // UADDLVv16i8v
7114 270573022U, // UADDLVv4i16v
7115 270580824U, // UADDLVv4i32v
7116 270574918U, // UADDLVv8i16v
7117 270567921U, // UADDLVv8i8v
7118 270737181U, // UADDLv16i8_v8i16
7119 270733981U, // UADDLv2i32_v2i64
7120 270743909U, // UADDLv4i16_v4i32
7121 270733409U, // UADDLv4i32_v2i64
7122 270742922U, // UADDLv8i16_v4i32
7123 270738037U, // UADDLv8i8_v8i16
7124 2261041445U, // UADDV_VPZ_B
7125 2164572453U, // UADDV_VPZ_D
7126 2166669605U, // UADDV_VPZ_H
7127 2156183845U, // UADDV_VPZ_S
7128 1075941035U, // UADDWB_ZZZ_D
7129 952241835U, // UADDWB_ZZZ_H
7130 1881312939U, // UADDWB_ZZZ_S
7131 1075953866U, // UADDWT_ZZZ_D
7132 952254666U, // UADDWT_ZZZ_H
7133 1881325770U, // UADDWT_ZZZ_S
7134 270737476U, // UADDWv16i8_v8i16
7135 270734669U, // UADDWv2i32_v2i64
7136 270744798U, // UADDWv4i16_v4i32
7137 270733572U, // UADDWv4i32_v2i64
7138 270743220U, // UADDWv8i16_v4i32
7139 270738892U, // UADDWv8i8_v8i16
7140 404794094U, // UBFMWri
7141 404794094U, // UBFMXri
7142 404789095U, // UCVTFSWDri
7143 404789095U, // UCVTFSWHri
7144 404789095U, // UCVTFSWSri
7145 404789095U, // UCVTFSXDri
7146 404789095U, // UCVTFSXHri
7147 404789095U, // UCVTFSXSri
7148 404789095U, // UCVTFUWDri
7149 404789095U, // UCVTFUWHri
7150 404789095U, // UCVTFUWSri
7151 404789095U, // UCVTFUXDri
7152 404789095U, // UCVTFUXHri
7153 404789095U, // UCVTFUXSri
7154 2201447U, // UCVTF_ZPmZ_DtoD
7155 541202279U, // UCVTF_ZPmZ_DtoH
7156 2266983U, // UCVTF_ZPmZ_DtoS
7157 138549095U, // UCVTF_ZPmZ_HtoH
7158 2201447U, // UCVTF_ZPmZ_StoD
7159 2286032743U, // UCVTF_ZPmZ_StoH
7160 2266983U, // UCVTF_ZPmZ_StoS
7161 404789095U, // UCVTFd
7162 404789095U, // UCVTFh
7163 404789095U, // UCVTFs
7164 404789095U, // UCVTFv1i16
7165 404789095U, // UCVTFv1i32
7166 404789095U, // UCVTFv1i64
7167 270741686U, // UCVTFv2f32
7168 270733793U, // UCVTFv2f64
7169 270741686U, // UCVTFv2i32_shift
7170 270733793U, // UCVTFv2i64_shift
7171 270735952U, // UCVTFv4f16
7172 270743661U, // UCVTFv4f32
7173 270735952U, // UCVTFv4i16_shift
7174 270743661U, // UCVTFv4i32_shift
7175 270737813U, // UCVTFv8f16
7176 270737813U, // UCVTFv8i16_shift
7177 38747U, // UDF
7178 1478602353U, // UDIVR_ZPmZ_D
7179 1478667889U, // UDIVR_ZPmZ_S
7180 404799811U, // UDIVWr
7181 404799811U, // UDIVXr
7182 1478607171U, // UDIV_ZPmZ_D
7183 1478672707U, // UDIV_ZPmZ_S
7184 1210171507U, // UDOT_ZZZI_D
7185 2820849779U, // UDOT_ZZZI_S
7186 1210171507U, // UDOT_ZZZ_D
7187 2820849779U, // UDOT_ZZZ_S
7188 1344520307U, // UDOTlanev16i8
7189 1344520307U, // UDOTlanev8i8
7190 17835U, // UDOTv16i8
7191 17835U, // UDOTv8i8
7192 1478563416U, // UHADD_ZPmZ_B
7193 1478596184U, // UHADD_ZPmZ_D
7194 1621235288U, // UHADD_ZPmZ_H
7195 1478661720U, // UHADD_ZPmZ_S
7196 270730264U, // UHADDv16i8
7197 270741568U, // UHADDv2i32
7198 270735857U, // UHADDv4i16
7199 270743534U, // UHADDv4i32
7200 270737718U, // UHADDv8i16
7201 270731157U, // UHADDv8i8
7202 1478569304U, // UHSUBR_ZPmZ_B
7203 1478602072U, // UHSUBR_ZPmZ_D
7204 1621241176U, // UHSUBR_ZPmZ_H
7205 1478667608U, // UHSUBR_ZPmZ_S
7206 1478561385U, // UHSUB_ZPmZ_B
7207 1478594153U, // UHSUB_ZPmZ_D
7208 1621233257U, // UHSUB_ZPmZ_H
7209 1478659689U, // UHSUB_ZPmZ_S
7210 270730144U, // UHSUBv16i8
7211 270741452U, // UHSUBv2i32
7212 270735741U, // UHSUBv4i16
7213 270743408U, // UHSUBv4i32
7214 270737602U, // UHSUBv8i16
7215 270731069U, // UHSUBv8i8
7216 404793830U, // UMADDLrrr
7217 1478569177U, // UMAXP_ZPmZ_B
7218 1478601945U, // UMAXP_ZPmZ_D
7219 1621241049U, // UMAXP_ZPmZ_H
7220 1478667481U, // UMAXP_ZPmZ_S
7221 270730594U, // UMAXPv16i8
7222 270742251U, // UMAXPv2i32
7223 270736528U, // UMAXPv4i16
7224 270744330U, // UMAXPv4i32
7225 270738424U, // UMAXPv8i16
7226 270731561U, // UMAXPv8i8
7227 278929U, // UMAXV_VPZ_B
7228 2164572561U, // UMAXV_VPZ_D
7229 2166702481U, // UMAXV_VPZ_H
7230 2156249489U, // UMAXV_VPZ_S
7231 270567021U, // UMAXVv16i8v
7232 270573116U, // UMAXVv4i16v
7233 270580918U, // UMAXVv4i32v
7234 270575012U, // UMAXVv8i16v
7235 270567962U, // UMAXVv8i8v
7236 1747010267U, // UMAX_ZI_B
7237 1075954395U, // UMAX_ZI_D
7238 952255195U, // UMAX_ZI_H
7239 1881326299U, // UMAX_ZI_S
7240 1478574811U, // UMAX_ZPmZ_B
7241 1478607579U, // UMAX_ZPmZ_D
7242 1621246683U, // UMAX_ZPmZ_H
7243 1478673115U, // UMAX_ZPmZ_S
7244 270730892U, // UMAXv16i8
7245 270742618U, // UMAXv2i32
7246 270736984U, // UMAXv4i16
7247 270744852U, // UMAXv4i32
7248 270738920U, // UMAXv8i16
7249 270731821U, // UMAXv8i8
7250 1478569095U, // UMINP_ZPmZ_B
7251 1478601863U, // UMINP_ZPmZ_D
7252 1621240967U, // UMINP_ZPmZ_H
7253 1478667399U, // UMINP_ZPmZ_S
7254 270730563U, // UMINPv16i8
7255 270742202U, // UMINPv2i32
7256 270736479U, // UMINPv4i16
7257 270744281U, // UMINPv4i32
7258 270738375U, // UMINPv8i16
7259 270731533U, // UMINPv8i8
7260 278889U, // UMINV_VPZ_B
7261 2164572521U, // UMINV_VPZ_D
7262 2166702441U, // UMINV_VPZ_H
7263 2156249449U, // UMINV_VPZ_S
7264 270566999U, // UMINVv16i8v
7265 270573077U, // UMINVv4i16v
7266 270580879U, // UMINVv4i32v
7267 270574973U, // UMINVv8i16v
7268 270567942U, // UMINVv8i8v
7269 1747004240U, // UMIN_ZI_B
7270 1075948368U, // UMIN_ZI_D
7271 952249168U, // UMIN_ZI_H
7272 1881320272U, // UMIN_ZI_S
7273 1478568784U, // UMIN_ZPmZ_B
7274 1478601552U, // UMIN_ZPmZ_D
7275 1621240656U, // UMIN_ZPmZ_H
7276 1478667088U, // UMIN_ZPmZ_S
7277 270730523U, // UMINv16i8
7278 270741982U, // UMINv2i32
7279 270736248U, // UMINv4i16
7280 270744153U, // UMINv4i32
7281 270738257U, // UMINv8i16
7282 270731395U, // UMINv8i8
7283 673286977U, // UMLALB_ZZZI_D
7284 1210223425U, // UMLALB_ZZZI_S
7285 673286977U, // UMLALB_ZZZ_D
7286 1052904257U, // UMLALB_ZZZ_H
7287 1210223425U, // UMLALB_ZZZ_S
7288 673300249U, // UMLALT_ZZZI_D
7289 1210236697U, // UMLALT_ZZZI_S
7290 673300249U, // UMLALT_ZZZ_D
7291 1052917529U, // UMLALT_ZZZ_H
7292 1210236697U, // UMLALT_ZZZ_S
7293 1344511707U, // UMLALv16i8_v8i16
7294 1344508513U, // UMLALv2i32_indexed
7295 1344508513U, // UMLALv2i32_v2i64
7296 1344518441U, // UMLALv4i16_indexed
7297 1344518441U, // UMLALv4i16_v4i32
7298 1344507935U, // UMLALv4i32_indexed
7299 1344507935U, // UMLALv4i32_v2i64
7300 1344517448U, // UMLALv8i16_indexed
7301 1344517448U, // UMLALv8i16_v4i32
7302 1344512569U, // UMLALv8i8_v8i16
7303 673287274U, // UMLSLB_ZZZI_D
7304 1210223722U, // UMLSLB_ZZZI_S
7305 673287274U, // UMLSLB_ZZZ_D
7306 1052904554U, // UMLSLB_ZZZ_H
7307 1210223722U, // UMLSLB_ZZZ_S
7308 673300423U, // UMLSLT_ZZZI_D
7309 1210236871U, // UMLSLT_ZZZI_S
7310 673300423U, // UMLSLT_ZZZ_D
7311 1052917703U, // UMLSLT_ZZZ_H
7312 1210236871U, // UMLSLT_ZZZ_S
7313 1344511850U, // UMLSLv16i8_v8i16
7314 1344508737U, // UMLSLv2i32_indexed
7315 1344508737U, // UMLSLv2i32_v2i64
7316 1344518665U, // UMLSLv4i16_indexed
7317 1344518665U, // UMLSLv4i16_v4i32
7318 1344508093U, // UMLSLv4i32_indexed
7319 1344508093U, // UMLSLv4i32_v2i64
7320 1344517606U, // UMLSLv8i16_indexed
7321 1344517606U, // UMLSLv8i16_v4i32
7322 1344512779U, // UMLSLv8i8_v8i16
7323 17704U, // UMMLA
7324 2820833571U, // UMMLA_ZZZ
7325 270571568U, // UMOVvi16
7326 270577426U, // UMOVvi32
7327 270569275U, // UMOVvi64
7328 270565863U, // UMOVvi8
7329 404793806U, // UMSUBLrrr
7330 1478567819U, // UMULH_ZPmZ_B
7331 1478600587U, // UMULH_ZPmZ_D
7332 1621239691U, // UMULH_ZPmZ_H
7333 1478666123U, // UMULH_ZPmZ_S
7334 1747003275U, // UMULH_ZZZ_B
7335 1075947403U, // UMULH_ZZZ_D
7336 952248203U, // UMULH_ZZZ_H
7337 1881319307U, // UMULH_ZZZ_S
7338 404793227U, // UMULHrr
7339 1881246740U, // UMULLB_ZZZI_D
7340 807570452U, // UMULLB_ZZZI_S
7341 1881246740U, // UMULLB_ZZZ_D
7342 1046613012U, // UMULLB_ZZZ_H
7343 807570452U, // UMULLB_ZZZ_S
7344 1881259927U, // UMULLT_ZZZI_D
7345 807583639U, // UMULLT_ZZZI_S
7346 1881259927U, // UMULLT_ZZZ_D
7347 1046626199U, // UMULLT_ZZZ_H
7348 807583639U, // UMULLT_ZZZ_S
7349 270737236U, // UMULLv16i8_v8i16
7350 270734113U, // UMULLv2i32_indexed
7351 270734113U, // UMULLv2i32_v2i64
7352 270744041U, // UMULLv4i16_indexed
7353 270744041U, // UMULLv4i16_v4i32
7354 270733466U, // UMULLv4i32_indexed
7355 270733466U, // UMULLv4i32_v2i64
7356 270742979U, // UMULLv8i16_indexed
7357 270742979U, // UMULLv8i16_v4i32
7358 270738167U, // UMULLv8i8_v8i16
7359 1746998903U, // UQADD_ZI_B
7360 1075943031U, // UQADD_ZI_D
7361 952243831U, // UQADD_ZI_H
7362 1881314935U, // UQADD_ZI_S
7363 1478563447U, // UQADD_ZPmZ_B
7364 1478596215U, // UQADD_ZPmZ_D
7365 1621235319U, // UQADD_ZPmZ_H
7366 1478661751U, // UQADD_ZPmZ_S
7367 1746998903U, // UQADD_ZZZ_B
7368 1075943031U, // UQADD_ZZZ_D
7369 952243831U, // UQADD_ZZZ_H
7370 1881314935U, // UQADD_ZZZ_S
7371 270730288U, // UQADDv16i8
7372 404788855U, // UQADDv1i16
7373 404788855U, // UQADDv1i32
7374 404788855U, // UQADDv1i64
7375 404788855U, // UQADDv1i8
7376 270741590U, // UQADDv2i32
7377 270733720U, // UQADDv2i64
7378 270735879U, // UQADDv4i16
7379 270743556U, // UQADDv4i32
7380 270737740U, // UQADDv8i16
7381 270731179U, // UQADDv8i8
7382 3491793597U, // UQDECB_WPiI
7383 3491793597U, // UQDECB_XPiI
7384 3491796493U, // UQDECD_WPiI
7385 3491796493U, // UQDECD_XPiI
7386 3491862029U, // UQDECD_ZPiI
7387 3491800729U, // UQDECH_WPiI
7388 3491800729U, // UQDECH_XPiI
7389 21112473U, // UQDECH_ZPiI
7390 1746971668U, // UQDECP_WP_B
7391 1075883028U, // UQDECP_WP_D
7392 807447572U, // UQDECP_WP_H
7393 1881189396U, // UQDECP_WP_S
7394 1746971668U, // UQDECP_XP_B
7395 1075883028U, // UQDECP_XP_D
7396 807447572U, // UQDECP_XP_H
7397 1881189396U, // UQDECP_XP_S
7398 539077652U, // UQDECP_ZP_D
7399 2166500372U, // UQDECP_ZP_H
7400 673360916U, // UQDECP_ZP_S
7401 3491807745U, // UQDECW_WPiI
7402 3491807745U, // UQDECW_XPiI
7403 3491938817U, // UQDECW_ZPiI
7404 3491793613U, // UQINCB_WPiI
7405 3491793613U, // UQINCB_XPiI
7406 3491796509U, // UQINCD_WPiI
7407 3491796509U, // UQINCD_XPiI
7408 3491862045U, // UQINCD_ZPiI
7409 3491800745U, // UQINCH_WPiI
7410 3491800745U, // UQINCH_XPiI
7411 21112489U, // UQINCH_ZPiI
7412 1746971684U, // UQINCP_WP_B
7413 1075883044U, // UQINCP_WP_D
7414 807447588U, // UQINCP_WP_H
7415 1881189412U, // UQINCP_WP_S
7416 1746971684U, // UQINCP_XP_B
7417 1075883044U, // UQINCP_XP_D
7418 807447588U, // UQINCP_XP_H
7419 1881189412U, // UQINCP_XP_S
7420 539077668U, // UQINCP_ZP_D
7421 2166500388U, // UQINCP_ZP_H
7422 673360932U, // UQINCP_ZP_S
7423 3491807761U, // UQINCW_WPiI
7424 3491807761U, // UQINCW_XPiI
7425 3491938833U, // UQINCW_ZPiI
7426 1478569415U, // UQRSHLR_ZPmZ_B
7427 1478602183U, // UQRSHLR_ZPmZ_D
7428 1621241287U, // UQRSHLR_ZPmZ_H
7429 1478667719U, // UQRSHLR_ZPmZ_S
7430 1478568476U, // UQRSHL_ZPmZ_B
7431 1478601244U, // UQRSHL_ZPmZ_D
7432 1621240348U, // UQRSHL_ZPmZ_H
7433 1478666780U, // UQRSHL_ZPmZ_S
7434 270730440U, // UQRSHLv16i8
7435 404793884U, // UQRSHLv1i16
7436 404793884U, // UQRSHLv1i32
7437 404793884U, // UQRSHLv1i64
7438 404793884U, // UQRSHLv1i8
7439 270741851U, // UQRSHLv2i32
7440 270734022U, // UQRSHLv2i64
7441 270736117U, // UQRSHLv4i16
7442 270743950U, // UQRSHLv4i32
7443 270738078U, // UQRSHLv8i16
7444 270731298U, // UQRSHLv8i8
7445 807472340U, // UQRSHRNB_ZZI_B
7446 945949908U, // UQRSHRNB_ZZI_H
7447 1076006100U, // UQRSHRNB_ZZI_S
7448 1210138644U, // UQRSHRNT_ZZI_B
7449 948060180U, // UQRSHRNT_ZZI_H
7450 539148308U, // UQRSHRNT_ZZI_S
7451 404794240U, // UQRSHRNb
7452 404794240U, // UQRSHRNh
7453 404794240U, // UQRSHRNs
7454 1344504512U, // UQRSHRNv16i8_shift
7455 270742025U, // UQRSHRNv2i32_shift
7456 270736291U, // UQRSHRNv4i16_shift
7457 1344517678U, // UQRSHRNv4i32_shift
7458 1344511922U, // UQRSHRNv8i16_shift
7459 270731438U, // UQRSHRNv8i8_shift
7460 1478569398U, // UQSHLR_ZPmZ_B
7461 1478602166U, // UQSHLR_ZPmZ_D
7462 1621241270U, // UQSHLR_ZPmZ_H
7463 1478667702U, // UQSHLR_ZPmZ_S
7464 1478568461U, // UQSHL_ZPmI_B
7465 1478601229U, // UQSHL_ZPmI_D
7466 1621240333U, // UQSHL_ZPmI_H
7467 1478666765U, // UQSHL_ZPmI_S
7468 1478568461U, // UQSHL_ZPmZ_B
7469 1478601229U, // UQSHL_ZPmZ_D
7470 1621240333U, // UQSHL_ZPmZ_H
7471 1478666765U, // UQSHL_ZPmZ_S
7472 404793869U, // UQSHLb
7473 404793869U, // UQSHLd
7474 404793869U, // UQSHLh
7475 404793869U, // UQSHLs
7476 270730417U, // UQSHLv16i8
7477 270730417U, // UQSHLv16i8_shift
7478 404793869U, // UQSHLv1i16
7479 404793869U, // UQSHLv1i32
7480 404793869U, // UQSHLv1i64
7481 404793869U, // UQSHLv1i8
7482 270741830U, // UQSHLv2i32
7483 270741830U, // UQSHLv2i32_shift
7484 270734001U, // UQSHLv2i64
7485 270734001U, // UQSHLv2i64_shift
7486 270736096U, // UQSHLv4i16
7487 270736096U, // UQSHLv4i16_shift
7488 270743929U, // UQSHLv4i32
7489 270743929U, // UQSHLv4i32_shift
7490 270738057U, // UQSHLv8i16
7491 270738057U, // UQSHLv8i16_shift
7492 270731277U, // UQSHLv8i8
7493 270731277U, // UQSHLv8i8_shift
7494 807472321U, // UQSHRNB_ZZI_B
7495 945949889U, // UQSHRNB_ZZI_H
7496 1076006081U, // UQSHRNB_ZZI_S
7497 1210138625U, // UQSHRNT_ZZI_B
7498 948060161U, // UQSHRNT_ZZI_H
7499 539148289U, // UQSHRNT_ZZI_S
7500 404794223U, // UQSHRNb
7501 404794223U, // UQSHRNh
7502 404794223U, // UQSHRNs
7503 1344504485U, // UQSHRNv16i8_shift
7504 270742002U, // UQSHRNv2i32_shift
7505 270736268U, // UQSHRNv4i16_shift
7506 1344517653U, // UQSHRNv4i32_shift
7507 1344511897U, // UQSHRNv8i16_shift
7508 270731415U, // UQSHRNv8i8_shift
7509 1478569320U, // UQSUBR_ZPmZ_B
7510 1478602088U, // UQSUBR_ZPmZ_D
7511 1621241192U, // UQSUBR_ZPmZ_H
7512 1478667624U, // UQSUBR_ZPmZ_S
7513 1746996870U, // UQSUB_ZI_B
7514 1075940998U, // UQSUB_ZI_D
7515 952241798U, // UQSUB_ZI_H
7516 1881312902U, // UQSUB_ZI_S
7517 1478561414U, // UQSUB_ZPmZ_B
7518 1478594182U, // UQSUB_ZPmZ_D
7519 1621233286U, // UQSUB_ZPmZ_H
7520 1478659718U, // UQSUB_ZPmZ_S
7521 1746996870U, // UQSUB_ZZZ_B
7522 1075940998U, // UQSUB_ZZZ_D
7523 952241798U, // UQSUB_ZZZ_H
7524 1881312902U, // UQSUB_ZZZ_S
7525 270730166U, // UQSUBv16i8
7526 404786822U, // UQSUBv1i16
7527 404786822U, // UQSUBv1i32
7528 404786822U, // UQSUBv1i64
7529 404786822U, // UQSUBv1i8
7530 270741472U, // UQSUBv2i32
7531 270733670U, // UQSUBv2i64
7532 270735761U, // UQSUBv4i16
7533 270743428U, // UQSUBv4i32
7534 270737622U, // UQSUBv8i16
7535 270731089U, // UQSUBv8i8
7536 807472358U, // UQXTNB_ZZ_B
7537 2153909478U, // UQXTNB_ZZ_H
7538 1076006118U, // UQXTNB_ZZ_S
7539 1210138671U, // UQXTNT_ZZ_B
7540 2156019759U, // UQXTNT_ZZ_H
7541 539148335U, // UQXTNT_ZZ_S
7542 1344504548U, // UQXTNv16i8
7543 404794276U, // UQXTNv1i16
7544 404794276U, // UQXTNv1i32
7545 404794276U, // UQXTNv1i8
7546 270742058U, // UQXTNv2i32
7547 270736335U, // UQXTNv4i16
7548 1344517711U, // UQXTNv4i32
7549 1344511967U, // UQXTNv8i16
7550 270731468U, // UQXTNv8i8
7551 2266909U, // URECPE_ZPmZ_S
7552 270741641U, // URECPEv2i32
7553 270743616U, // URECPEv4i32
7554 1478563401U, // URHADD_ZPmZ_B
7555 1478596169U, // URHADD_ZPmZ_D
7556 1621235273U, // URHADD_ZPmZ_H
7557 1478661705U, // URHADD_ZPmZ_S
7558 270730241U, // URHADDv16i8
7559 270741547U, // URHADDv2i32
7560 270735836U, // URHADDv4i16
7561 270743513U, // URHADDv4i32
7562 270737697U, // URHADDv8i16
7563 270731136U, // URHADDv8i8
7564 1478569432U, // URSHLR_ZPmZ_B
7565 1478602200U, // URSHLR_ZPmZ_D
7566 1621241304U, // URSHLR_ZPmZ_H
7567 1478667736U, // URSHLR_ZPmZ_S
7568 1478568491U, // URSHL_ZPmZ_B
7569 1478601259U, // URSHL_ZPmZ_D
7570 1621240363U, // URSHL_ZPmZ_H
7571 1478666795U, // URSHL_ZPmZ_S
7572 270730463U, // URSHLv16i8
7573 404793899U, // URSHLv1i64
7574 270741872U, // URSHLv2i32
7575 270734043U, // URSHLv2i64
7576 270736138U, // URSHLv4i16
7577 270743971U, // URSHLv4i32
7578 270738099U, // URSHLv8i16
7579 270731319U, // URSHLv8i8
7580 1478569359U, // URSHR_ZPmI_B
7581 1478602127U, // URSHR_ZPmI_D
7582 1621241231U, // URSHR_ZPmI_H
7583 1478667663U, // URSHR_ZPmI_S
7584 404794767U, // URSHRd
7585 270730626U, // URSHRv16i8_shift
7586 270742281U, // URSHRv2i32_shift
7587 270734362U, // URSHRv2i64_shift
7588 270736558U, // URSHRv4i16_shift
7589 270744360U, // URSHRv4i32_shift
7590 270738454U, // URSHRv8i16_shift
7591 270731590U, // URSHRv8i8_shift
7592 2266955U, // URSQRTE_ZPmZ_S
7593 270741664U, // URSQRTEv2i32
7594 270743639U, // URSQRTEv4i32
7595 2820735349U, // URSRA_ZZI_B
7596 539066741U, // URSRA_ZZI_D
7597 958529909U, // URSRA_ZZI_H
7598 673350005U, // URSRA_ZZI_S
7599 2418508149U, // URSRAd
7600 1344504694U, // URSRAv16i8_shift
7601 1344515986U, // URSRAv2i32_shift
7602 1344508204U, // URSRAv2i64_shift
7603 1344510275U, // URSRAv4i16_shift
7604 1344517918U, // URSRAv4i32_shift
7605 1344512136U, // URSRAv8i16_shift
7606 1344505623U, // URSRAv8i8_shift
7607 2820849771U, // USDOT_ZZZ
7608 2820849771U, // USDOT_ZZZI
7609 1344520299U, // USDOTlanev16i8
7610 1344520299U, // USDOTlanev8i8
7611 17829U, // USDOTv16i8
7612 17829U, // USDOTv8i8
7613 1881246706U, // USHLLB_ZZI_D
7614 1046612978U, // USHLLB_ZZI_H
7615 807570418U, // USHLLB_ZZI_S
7616 1881259893U, // USHLLT_ZZI_D
7617 1046626165U, // USHLLT_ZZI_H
7618 807583605U, // USHLLT_ZZI_S
7619 270737203U, // USHLLv16i8_shift
7620 270734081U, // USHLLv2i32_shift
7621 270744009U, // USHLLv4i16_shift
7622 270733431U, // USHLLv4i32_shift
7623 270742944U, // USHLLv8i16_shift
7624 270738137U, // USHLLv8i8_shift
7625 270730484U, // USHLv16i8
7626 404793912U, // USHLv1i64
7627 270741891U, // USHLv2i32
7628 270734062U, // USHLv2i64
7629 270736157U, // USHLv4i16
7630 270743990U, // USHLv4i32
7631 270738118U, // USHLv8i16
7632 270731338U, // USHLv8i8
7633 404794780U, // USHRd
7634 270730647U, // USHRv16i8_shift
7635 270742300U, // USHRv2i32_shift
7636 270734381U, // USHRv2i64_shift
7637 270736577U, // USHRv4i16_shift
7638 270744379U, // USHRv4i32_shift
7639 270738473U, // USHRv8i16_shift
7640 270731609U, // USHRv8i8_shift
7641 17697U, // USMMLA
7642 2820833563U, // USMMLA_ZZZ
7643 1478563438U, // USQADD_ZPmZ_B
7644 1478596206U, // USQADD_ZPmZ_D
7645 1621235310U, // USQADD_ZPmZ_H
7646 1478661742U, // USQADD_ZPmZ_S
7647 1344504867U, // USQADDv16i8
7648 2418513518U, // USQADDv1i16
7649 2418513518U, // USQADDv1i32
7650 2418513518U, // USQADDv1i64
7651 2418513518U, // USQADDv1i8
7652 1344516170U, // USQADDv2i32
7653 1344508300U, // USQADDv2i64
7654 1344510459U, // USQADDv4i16
7655 1344518136U, // USQADDv4i32
7656 1344512320U, // USQADDv8i16
7657 1344505759U, // USQADDv8i8
7658 2820735362U, // USRA_ZZI_B
7659 539066754U, // USRA_ZZI_D
7660 958529922U, // USRA_ZZI_H
7661 673350018U, // USRA_ZZI_S
7662 2418508162U, // USRAd
7663 1344504715U, // USRAv16i8_shift
7664 1344516005U, // USRAv2i32_shift
7665 1344508223U, // USRAv2i64_shift
7666 1344510294U, // USRAv4i16_shift
7667 1344517937U, // USRAv4i32_shift
7668 1344512155U, // USRAv8i16_shift
7669 1344505642U, // USRAv8i8_shift
7670 1881246635U, // USUBLB_ZZZ_D
7671 1046612907U, // USUBLB_ZZZ_H
7672 807570347U, // USUBLB_ZZZ_S
7673 1881259817U, // USUBLT_ZZZ_D
7674 1046626089U, // USUBLT_ZZZ_H
7675 807583529U, // USUBLT_ZZZ_S
7676 270737137U, // USUBLv16i8_v8i16
7677 270733941U, // USUBLv2i32_v2i64
7678 270743869U, // USUBLv4i16_v4i32
7679 270733365U, // USUBLv4i32_v2i64
7680 270742878U, // USUBLv8i16_v4i32
7681 270737997U, // USUBLv8i8_v8i16
7682 1075941019U, // USUBWB_ZZZ_D
7683 952241819U, // USUBWB_ZZZ_H
7684 1881312923U, // USUBWB_ZZZ_S
7685 1075953850U, // USUBWT_ZZZ_D
7686 952254650U, // USUBWT_ZZZ_H
7687 1881325754U, // USUBWT_ZZZ_S
7688 270737454U, // USUBWv16i8_v8i16
7689 270734649U, // USUBWv2i32_v2i64
7690 270744778U, // USUBWv4i16_v4i32
7691 270733550U, // USUBWv4i32_v2i64
7692 270743198U, // USUBWv8i16_v4i32
7693 270738872U, // USUBWv8i8_v8i16
7694 1881254161U, // UUNPKHI_ZZ_D
7695 2254579985U, // UUNPKHI_ZZ_H
7696 807577873U, // UUNPKHI_ZZ_S
7697 1881254895U, // UUNPKLO_ZZ_D
7698 2254580719U, // UUNPKLO_ZZ_H
7699 807578607U, // UUNPKLO_ZZ_S
7700 2199126U, // UXTB_ZPmZ_D
7701 138546774U, // UXTB_ZPmZ_H
7702 2264662U, // UXTB_ZPmZ_S
7703 2205905U, // UXTH_ZPmZ_D
7704 2271441U, // UXTH_ZPmZ_S
7705 2212509U, // UXTW_ZPmZ_D
7706 1746993179U, // UZP1_PPP_B
7707 1075937307U, // UZP1_PPP_D
7708 952238107U, // UZP1_PPP_H
7709 1881309211U, // UZP1_PPP_S
7710 1746993179U, // UZP1_ZZZ_B
7711 1075937307U, // UZP1_ZZZ_D
7712 952238107U, // UZP1_ZZZ_H
7713 967442459U, // UZP1_ZZZ_Q
7714 1881309211U, // UZP1_ZZZ_S
7715 270729833U, // UZP1v16i8
7716 270741301U, // UZP1v2i32
7717 270733252U, // UZP1v2i64
7718 270735580U, // UZP1v4i16
7719 270742737U, // UZP1v4i32
7720 270737063U, // UZP1v8i16
7721 270730929U, // UZP1v8i8
7722 1746993268U, // UZP2_PPP_B
7723 1075937396U, // UZP2_PPP_D
7724 952238196U, // UZP2_PPP_H
7725 1881309300U, // UZP2_PPP_S
7726 1746993268U, // UZP2_ZZZ_B
7727 1075937396U, // UZP2_ZZZ_D
7728 952238196U, // UZP2_ZZZ_H
7729 967442548U, // UZP2_ZZZ_Q
7730 1881309300U, // UZP2_ZZZ_S
7731 270730020U, // UZP2v16i8
7732 270741328U, // UZP2v2i32
7733 270733530U, // UZP2v2i64
7734 270735617U, // UZP2v4i16
7735 270743178U, // UZP2v4i32
7736 270737434U, // UZP2v8i16
7737 270730966U, // UZP2v8i8
7738 48818U, // WFET
7739 48872U, // WFIT
7740 404821704U, // WHILEGE_PWW_B
7741 404854472U, // WHILEGE_PWW_D
7742 964826824U, // WHILEGE_PWW_H
7743 404920008U, // WHILEGE_PWW_S
7744 404821704U, // WHILEGE_PXX_B
7745 404854472U, // WHILEGE_PXX_D
7746 964826824U, // WHILEGE_PXX_H
7747 404920008U, // WHILEGE_PXX_S
7748 404831947U, // WHILEGT_PWW_B
7749 404864715U, // WHILEGT_PWW_D
7750 964837067U, // WHILEGT_PWW_H
7751 404930251U, // WHILEGT_PWW_S
7752 404831947U, // WHILEGT_PXX_B
7753 404864715U, // WHILEGT_PXX_D
7754 964837067U, // WHILEGT_PXX_H
7755 404930251U, // WHILEGT_PXX_S
7756 404826358U, // WHILEHI_PWW_B
7757 404859126U, // WHILEHI_PWW_D
7758 964831478U, // WHILEHI_PWW_H
7759 404924662U, // WHILEHI_PWW_S
7760 404826358U, // WHILEHI_PXX_B
7761 404859126U, // WHILEHI_PXX_D
7762 964831478U, // WHILEHI_PXX_H
7763 404924662U, // WHILEHI_PXX_S
7764 404831696U, // WHILEHS_PWW_B
7765 404864464U, // WHILEHS_PWW_D
7766 964836816U, // WHILEHS_PWW_H
7767 404930000U, // WHILEHS_PWW_S
7768 404831696U, // WHILEHS_PXX_B
7769 404864464U, // WHILEHS_PXX_D
7770 964836816U, // WHILEHS_PXX_H
7771 404930000U, // WHILEHS_PXX_S
7772 404821735U, // WHILELE_PWW_B
7773 404854503U, // WHILELE_PWW_D
7774 964826855U, // WHILELE_PWW_H
7775 404920039U, // WHILELE_PWW_S
7776 404821735U, // WHILELE_PXX_B
7777 404854503U, // WHILELE_PXX_D
7778 964826855U, // WHILELE_PXX_H
7779 404920039U, // WHILELE_PXX_S
7780 404827092U, // WHILELO_PWW_B
7781 404859860U, // WHILELO_PWW_D
7782 964832212U, // WHILELO_PWW_H
7783 404925396U, // WHILELO_PWW_S
7784 404827092U, // WHILELO_PXX_B
7785 404859860U, // WHILELO_PXX_D
7786 964832212U, // WHILELO_PXX_H
7787 404925396U, // WHILELO_PXX_S
7788 404831723U, // WHILELS_PWW_B
7789 404864491U, // WHILELS_PWW_D
7790 964836843U, // WHILELS_PWW_H
7791 404930027U, // WHILELS_PWW_S
7792 404831723U, // WHILELS_PXX_B
7793 404864491U, // WHILELS_PXX_D
7794 964836843U, // WHILELS_PXX_H
7795 404930027U, // WHILELS_PXX_S
7796 404832095U, // WHILELT_PWW_B
7797 404864863U, // WHILELT_PWW_D
7798 964837215U, // WHILELT_PWW_H
7799 404930399U, // WHILELT_PWW_S
7800 404832095U, // WHILELT_PXX_B
7801 404864863U, // WHILELT_PXX_D
7802 964837215U, // WHILELT_PXX_H
7803 404930399U, // WHILELT_PXX_S
7804 404832822U, // WHILERW_PXX_B
7805 404865590U, // WHILERW_PXX_D
7806 964837942U, // WHILERW_PXX_H
7807 404931126U, // WHILERW_PXX_S
7808 404827768U, // WHILEWR_PXX_B
7809 404860536U, // WHILEWR_PXX_D
7810 964832888U, // WHILEWR_PXX_H
7811 404926072U, // WHILEWR_PXX_S
7812 77185U, // WRFFR
7813 17733U, // XAFLAG
7814 270734344U, // XAR
7815 1747004740U, // XAR_ZZZI_B
7816 1075948868U, // XAR_ZZZI_D
7817 952249668U, // XAR_ZZZI_H
7818 1881320772U, // XAR_ZZZI_S
7819 38398U, // XPACD
7820 43247U, // XPACI
7821 17552U, // XPACLRI
7822 1344504538U, // XTNv16i8
7823 270742050U, // XTNv2i32
7824 270736327U, // XTNv4i16
7825 1344517702U, // XTNv4i32
7826 1344511958U, // XTNv8i16
7827 270731460U, // XTNv8i8
7828 1746993173U, // ZIP1_PPP_B
7829 1075937301U, // ZIP1_PPP_D
7830 952238101U, // ZIP1_PPP_H
7831 1881309205U, // ZIP1_PPP_S
7832 1746993173U, // ZIP1_ZZZ_B
7833 1075937301U, // ZIP1_ZZZ_D
7834 952238101U, // ZIP1_ZZZ_H
7835 967442453U, // ZIP1_ZZZ_Q
7836 1881309205U, // ZIP1_ZZZ_S
7837 270729823U, // ZIP1v16i8
7838 270741292U, // ZIP1v2i32
7839 270733243U, // ZIP1v2i64
7840 270735571U, // ZIP1v4i16
7841 270742728U, // ZIP1v4i32
7842 270737054U, // ZIP1v8i16
7843 270730920U, // ZIP1v8i8
7844 1746993262U, // ZIP2_PPP_B
7845 1075937390U, // ZIP2_PPP_D
7846 952238190U, // ZIP2_PPP_H
7847 1881309294U, // ZIP2_PPP_S
7848 1746993262U, // ZIP2_ZZZ_B
7849 1075937390U, // ZIP2_ZZZ_D
7850 952238190U, // ZIP2_ZZZ_H
7851 967442542U, // ZIP2_ZZZ_Q
7852 1881309294U, // ZIP2_ZZZ_S
7853 270730010U, // ZIP2v16i8
7854 270741319U, // ZIP2v2i32
7855 270733521U, // ZIP2v2i64
7856 270735608U, // ZIP2v4i16
7857 270743169U, // ZIP2v4i32
7858 270737425U, // ZIP2v8i16
7859 270730957U, // ZIP2v8i8
7860 };
7861
7862 static const uint32_t OpInfo1[] = {
7863 0U, // PHI
7864 0U, // INLINEASM
7865 0U, // INLINEASM_BR
7866 0U, // CFI_INSTRUCTION
7867 0U, // EH_LABEL
7868 0U, // GC_LABEL
7869 0U, // ANNOTATION_LABEL
7870 0U, // KILL
7871 0U, // EXTRACT_SUBREG
7872 0U, // INSERT_SUBREG
7873 0U, // IMPLICIT_DEF
7874 0U, // SUBREG_TO_REG
7875 0U, // COPY_TO_REGCLASS
7876 0U, // DBG_VALUE
7877 0U, // DBG_INSTR_REF
7878 0U, // DBG_LABEL
7879 0U, // REG_SEQUENCE
7880 0U, // COPY
7881 0U, // BUNDLE
7882 0U, // LIFETIME_START
7883 0U, // LIFETIME_END
7884 0U, // PSEUDO_PROBE
7885 0U, // STACKMAP
7886 0U, // FENTRY_CALL
7887 0U, // PATCHPOINT
7888 0U, // LOAD_STACK_GUARD
7889 0U, // PREALLOCATED_SETUP
7890 0U, // PREALLOCATED_ARG
7891 0U, // STATEPOINT
7892 0U, // LOCAL_ESCAPE
7893 0U, // FAULTING_OP
7894 0U, // PATCHABLE_OP
7895 0U, // PATCHABLE_FUNCTION_ENTER
7896 0U, // PATCHABLE_RET
7897 0U, // PATCHABLE_FUNCTION_EXIT
7898 0U, // PATCHABLE_TAIL_CALL
7899 0U, // PATCHABLE_EVENT_CALL
7900 0U, // PATCHABLE_TYPED_EVENT_CALL
7901 0U, // ICALL_BRANCH_FUNNEL
7902 0U, // G_ADD
7903 0U, // G_SUB
7904 0U, // G_MUL
7905 0U, // G_SDIV
7906 0U, // G_UDIV
7907 0U, // G_SREM
7908 0U, // G_UREM
7909 0U, // G_AND
7910 0U, // G_OR
7911 0U, // G_XOR
7912 0U, // G_IMPLICIT_DEF
7913 0U, // G_PHI
7914 0U, // G_FRAME_INDEX
7915 0U, // G_GLOBAL_VALUE
7916 0U, // G_EXTRACT
7917 0U, // G_UNMERGE_VALUES
7918 0U, // G_INSERT
7919 0U, // G_MERGE_VALUES
7920 0U, // G_BUILD_VECTOR
7921 0U, // G_BUILD_VECTOR_TRUNC
7922 0U, // G_CONCAT_VECTORS
7923 0U, // G_PTRTOINT
7924 0U, // G_INTTOPTR
7925 0U, // G_BITCAST
7926 0U, // G_FREEZE
7927 0U, // G_INTRINSIC_TRUNC
7928 0U, // G_INTRINSIC_ROUND
7929 0U, // G_INTRINSIC_LRINT
7930 0U, // G_INTRINSIC_ROUNDEVEN
7931 0U, // G_READCYCLECOUNTER
7932 0U, // G_LOAD
7933 0U, // G_SEXTLOAD
7934 0U, // G_ZEXTLOAD
7935 0U, // G_INDEXED_LOAD
7936 0U, // G_INDEXED_SEXTLOAD
7937 0U, // G_INDEXED_ZEXTLOAD
7938 0U, // G_STORE
7939 0U, // G_INDEXED_STORE
7940 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
7941 0U, // G_ATOMIC_CMPXCHG
7942 0U, // G_ATOMICRMW_XCHG
7943 0U, // G_ATOMICRMW_ADD
7944 0U, // G_ATOMICRMW_SUB
7945 0U, // G_ATOMICRMW_AND
7946 0U, // G_ATOMICRMW_NAND
7947 0U, // G_ATOMICRMW_OR
7948 0U, // G_ATOMICRMW_XOR
7949 0U, // G_ATOMICRMW_MAX
7950 0U, // G_ATOMICRMW_MIN
7951 0U, // G_ATOMICRMW_UMAX
7952 0U, // G_ATOMICRMW_UMIN
7953 0U, // G_ATOMICRMW_FADD
7954 0U, // G_ATOMICRMW_FSUB
7955 0U, // G_FENCE
7956 0U, // G_BRCOND
7957 0U, // G_BRINDIRECT
7958 0U, // G_INTRINSIC
7959 0U, // G_INTRINSIC_W_SIDE_EFFECTS
7960 0U, // G_ANYEXT
7961 0U, // G_TRUNC
7962 0U, // G_CONSTANT
7963 0U, // G_FCONSTANT
7964 0U, // G_VASTART
7965 0U, // G_VAARG
7966 0U, // G_SEXT
7967 0U, // G_SEXT_INREG
7968 0U, // G_ZEXT
7969 0U, // G_SHL
7970 0U, // G_LSHR
7971 0U, // G_ASHR
7972 0U, // G_FSHL
7973 0U, // G_FSHR
7974 0U, // G_ICMP
7975 0U, // G_FCMP
7976 0U, // G_SELECT
7977 0U, // G_UADDO
7978 0U, // G_UADDE
7979 0U, // G_USUBO
7980 0U, // G_USUBE
7981 0U, // G_SADDO
7982 0U, // G_SADDE
7983 0U, // G_SSUBO
7984 0U, // G_SSUBE
7985 0U, // G_UMULO
7986 0U, // G_SMULO
7987 0U, // G_UMULH
7988 0U, // G_SMULH
7989 0U, // G_UADDSAT
7990 0U, // G_SADDSAT
7991 0U, // G_USUBSAT
7992 0U, // G_SSUBSAT
7993 0U, // G_USHLSAT
7994 0U, // G_SSHLSAT
7995 0U, // G_SMULFIX
7996 0U, // G_UMULFIX
7997 0U, // G_SMULFIXSAT
7998 0U, // G_UMULFIXSAT
7999 0U, // G_SDIVFIX
8000 0U, // G_UDIVFIX
8001 0U, // G_SDIVFIXSAT
8002 0U, // G_UDIVFIXSAT
8003 0U, // G_FADD
8004 0U, // G_FSUB
8005 0U, // G_FMUL
8006 0U, // G_FMA
8007 0U, // G_FMAD
8008 0U, // G_FDIV
8009 0U, // G_FREM
8010 0U, // G_FPOW
8011 0U, // G_FPOWI
8012 0U, // G_FEXP
8013 0U, // G_FEXP2
8014 0U, // G_FLOG
8015 0U, // G_FLOG2
8016 0U, // G_FLOG10
8017 0U, // G_FNEG
8018 0U, // G_FPEXT
8019 0U, // G_FPTRUNC
8020 0U, // G_FPTOSI
8021 0U, // G_FPTOUI
8022 0U, // G_SITOFP
8023 0U, // G_UITOFP
8024 0U, // G_FABS
8025 0U, // G_FCOPYSIGN
8026 0U, // G_FCANONICALIZE
8027 0U, // G_FMINNUM
8028 0U, // G_FMAXNUM
8029 0U, // G_FMINNUM_IEEE
8030 0U, // G_FMAXNUM_IEEE
8031 0U, // G_FMINIMUM
8032 0U, // G_FMAXIMUM
8033 0U, // G_PTR_ADD
8034 0U, // G_PTRMASK
8035 0U, // G_SMIN
8036 0U, // G_SMAX
8037 0U, // G_UMIN
8038 0U, // G_UMAX
8039 0U, // G_ABS
8040 0U, // G_BR
8041 0U, // G_BRJT
8042 0U, // G_INSERT_VECTOR_ELT
8043 0U, // G_EXTRACT_VECTOR_ELT
8044 0U, // G_SHUFFLE_VECTOR
8045 0U, // G_CTTZ
8046 0U, // G_CTTZ_ZERO_UNDEF
8047 0U, // G_CTLZ
8048 0U, // G_CTLZ_ZERO_UNDEF
8049 0U, // G_CTPOP
8050 0U, // G_BSWAP
8051 0U, // G_BITREVERSE
8052 0U, // G_FCEIL
8053 0U, // G_FCOS
8054 0U, // G_FSIN
8055 0U, // G_FSQRT
8056 0U, // G_FFLOOR
8057 0U, // G_FRINT
8058 0U, // G_FNEARBYINT
8059 0U, // G_ADDRSPACE_CAST
8060 0U, // G_BLOCK_ADDR
8061 0U, // G_JUMP_TABLE
8062 0U, // G_DYN_STACKALLOC
8063 0U, // G_STRICT_FADD
8064 0U, // G_STRICT_FSUB
8065 0U, // G_STRICT_FMUL
8066 0U, // G_STRICT_FDIV
8067 0U, // G_STRICT_FREM
8068 0U, // G_STRICT_FMA
8069 0U, // G_STRICT_FSQRT
8070 0U, // G_READ_REGISTER
8071 0U, // G_WRITE_REGISTER
8072 0U, // G_MEMCPY
8073 0U, // G_MEMMOVE
8074 0U, // G_MEMSET
8075 0U, // G_VECREDUCE_SEQ_FADD
8076 0U, // G_VECREDUCE_SEQ_FMUL
8077 0U, // G_VECREDUCE_FADD
8078 0U, // G_VECREDUCE_FMUL
8079 0U, // G_VECREDUCE_FMAX
8080 0U, // G_VECREDUCE_FMIN
8081 0U, // G_VECREDUCE_ADD
8082 0U, // G_VECREDUCE_MUL
8083 0U, // G_VECREDUCE_AND
8084 0U, // G_VECREDUCE_OR
8085 0U, // G_VECREDUCE_XOR
8086 0U, // G_VECREDUCE_SMAX
8087 0U, // G_VECREDUCE_SMIN
8088 0U, // G_VECREDUCE_UMAX
8089 0U, // G_VECREDUCE_UMIN
8090 0U, // ADDSWrr
8091 0U, // ADDSXrr
8092 0U, // ADDWrr
8093 0U, // ADDXrr
8094 0U, // ADD_ZPZZ_UNDEF_B
8095 0U, // ADD_ZPZZ_UNDEF_D
8096 0U, // ADD_ZPZZ_UNDEF_H
8097 0U, // ADD_ZPZZ_UNDEF_S
8098 0U, // ADD_ZPZZ_ZERO_B
8099 0U, // ADD_ZPZZ_ZERO_D
8100 0U, // ADD_ZPZZ_ZERO_H
8101 0U, // ADD_ZPZZ_ZERO_S
8102 0U, // ADDlowTLS
8103 0U, // ADJCALLSTACKDOWN
8104 0U, // ADJCALLSTACKUP
8105 0U, // AESIMCrrTied
8106 0U, // AESMCrrTied
8107 0U, // ANDSWrr
8108 0U, // ANDSXrr
8109 0U, // ANDWrr
8110 0U, // ANDXrr
8111 0U, // ASRD_ZPZI_ZERO_B
8112 0U, // ASRD_ZPZI_ZERO_D
8113 0U, // ASRD_ZPZI_ZERO_H
8114 0U, // ASRD_ZPZI_ZERO_S
8115 0U, // ASR_ZPZI_UNDEF_B
8116 0U, // ASR_ZPZI_UNDEF_D
8117 0U, // ASR_ZPZI_UNDEF_H
8118 0U, // ASR_ZPZI_UNDEF_S
8119 0U, // ASR_ZPZZ_UNDEF_B
8120 0U, // ASR_ZPZZ_UNDEF_D
8121 0U, // ASR_ZPZZ_UNDEF_H
8122 0U, // ASR_ZPZZ_UNDEF_S
8123 0U, // ASR_ZPZZ_ZERO_B
8124 0U, // ASR_ZPZZ_ZERO_D
8125 0U, // ASR_ZPZZ_ZERO_H
8126 0U, // ASR_ZPZZ_ZERO_S
8127 0U, // BICSWrr
8128 0U, // BICSXrr
8129 0U, // BICWrr
8130 0U, // BICXrr
8131 0U, // BLRNoIP
8132 0U, // BLR_RVMARKER
8133 0U, // BSPv16i8
8134 0U, // BSPv8i8
8135 0U, // CATCHRET
8136 0U, // CLEANUPRET
8137 0U, // CMP_SWAP_128
8138 0U, // CMP_SWAP_16
8139 0U, // CMP_SWAP_32
8140 0U, // CMP_SWAP_64
8141 0U, // CMP_SWAP_8
8142 0U, // CompilerBarrier
8143 0U, // EMITBKEY
8144 0U, // EONWrr
8145 0U, // EONXrr
8146 0U, // EORWrr
8147 0U, // EORXrr
8148 0U, // F128CSEL
8149 0U, // FABD_ZPZZ_ZERO_D
8150 0U, // FABD_ZPZZ_ZERO_H
8151 0U, // FABD_ZPZZ_ZERO_S
8152 0U, // FADD_ZPZZ_UNDEF_D
8153 0U, // FADD_ZPZZ_UNDEF_H
8154 0U, // FADD_ZPZZ_UNDEF_S
8155 0U, // FADD_ZPZZ_ZERO_D
8156 0U, // FADD_ZPZZ_ZERO_H
8157 0U, // FADD_ZPZZ_ZERO_S
8158 0U, // FDIVR_ZPZZ_ZERO_D
8159 0U, // FDIVR_ZPZZ_ZERO_H
8160 0U, // FDIVR_ZPZZ_ZERO_S
8161 0U, // FDIV_ZPZZ_UNDEF_D
8162 0U, // FDIV_ZPZZ_UNDEF_H
8163 0U, // FDIV_ZPZZ_UNDEF_S
8164 0U, // FDIV_ZPZZ_ZERO_D
8165 0U, // FDIV_ZPZZ_ZERO_H
8166 0U, // FDIV_ZPZZ_ZERO_S
8167 0U, // FMAXNM_ZPZZ_UNDEF_D
8168 0U, // FMAXNM_ZPZZ_UNDEF_H
8169 0U, // FMAXNM_ZPZZ_UNDEF_S
8170 0U, // FMAXNM_ZPZZ_ZERO_D
8171 0U, // FMAXNM_ZPZZ_ZERO_H
8172 0U, // FMAXNM_ZPZZ_ZERO_S
8173 0U, // FMAX_ZPZZ_ZERO_D
8174 0U, // FMAX_ZPZZ_ZERO_H
8175 0U, // FMAX_ZPZZ_ZERO_S
8176 0U, // FMINNM_ZPZZ_UNDEF_D
8177 0U, // FMINNM_ZPZZ_UNDEF_H
8178 0U, // FMINNM_ZPZZ_UNDEF_S
8179 0U, // FMINNM_ZPZZ_ZERO_D
8180 0U, // FMINNM_ZPZZ_ZERO_H
8181 0U, // FMINNM_ZPZZ_ZERO_S
8182 0U, // FMIN_ZPZZ_ZERO_D
8183 0U, // FMIN_ZPZZ_ZERO_H
8184 0U, // FMIN_ZPZZ_ZERO_S
8185 0U, // FMOVD0
8186 0U, // FMOVH0
8187 0U, // FMOVS0
8188 0U, // FMULX_ZPZZ_ZERO_D
8189 0U, // FMULX_ZPZZ_ZERO_H
8190 0U, // FMULX_ZPZZ_ZERO_S
8191 0U, // FMUL_ZPZZ_UNDEF_D
8192 0U, // FMUL_ZPZZ_UNDEF_H
8193 0U, // FMUL_ZPZZ_UNDEF_S
8194 0U, // FMUL_ZPZZ_ZERO_D
8195 0U, // FMUL_ZPZZ_ZERO_H
8196 0U, // FMUL_ZPZZ_ZERO_S
8197 0U, // FSUBR_ZPZZ_ZERO_D
8198 0U, // FSUBR_ZPZZ_ZERO_H
8199 0U, // FSUBR_ZPZZ_ZERO_S
8200 0U, // FSUB_ZPZZ_UNDEF_D
8201 0U, // FSUB_ZPZZ_UNDEF_H
8202 0U, // FSUB_ZPZZ_UNDEF_S
8203 0U, // FSUB_ZPZZ_ZERO_D
8204 0U, // FSUB_ZPZZ_ZERO_H
8205 0U, // FSUB_ZPZZ_ZERO_S
8206 0U, // GLD1B_D
8207 0U, // GLD1B_D_IMM
8208 0U, // GLD1B_D_SXTW
8209 0U, // GLD1B_D_UXTW
8210 0U, // GLD1B_S_IMM
8211 0U, // GLD1B_S_SXTW
8212 0U, // GLD1B_S_UXTW
8213 0U, // GLD1D
8214 0U, // GLD1D_IMM
8215 0U, // GLD1D_SCALED
8216 0U, // GLD1D_SXTW
8217 0U, // GLD1D_SXTW_SCALED
8218 0U, // GLD1D_UXTW
8219 0U, // GLD1D_UXTW_SCALED
8220 0U, // GLD1H_D
8221 0U, // GLD1H_D_IMM
8222 0U, // GLD1H_D_SCALED
8223 0U, // GLD1H_D_SXTW
8224 0U, // GLD1H_D_SXTW_SCALED
8225 0U, // GLD1H_D_UXTW
8226 0U, // GLD1H_D_UXTW_SCALED
8227 0U, // GLD1H_S_IMM
8228 0U, // GLD1H_S_SXTW
8229 0U, // GLD1H_S_SXTW_SCALED
8230 0U, // GLD1H_S_UXTW
8231 0U, // GLD1H_S_UXTW_SCALED
8232 0U, // GLD1SB_D
8233 0U, // GLD1SB_D_IMM
8234 0U, // GLD1SB_D_SXTW
8235 0U, // GLD1SB_D_UXTW
8236 0U, // GLD1SB_S_IMM
8237 0U, // GLD1SB_S_SXTW
8238 0U, // GLD1SB_S_UXTW
8239 0U, // GLD1SH_D
8240 0U, // GLD1SH_D_IMM
8241 0U, // GLD1SH_D_SCALED
8242 0U, // GLD1SH_D_SXTW
8243 0U, // GLD1SH_D_SXTW_SCALED
8244 0U, // GLD1SH_D_UXTW
8245 0U, // GLD1SH_D_UXTW_SCALED
8246 0U, // GLD1SH_S_IMM
8247 0U, // GLD1SH_S_SXTW
8248 0U, // GLD1SH_S_SXTW_SCALED
8249 0U, // GLD1SH_S_UXTW
8250 0U, // GLD1SH_S_UXTW_SCALED
8251 0U, // GLD1SW_D
8252 0U, // GLD1SW_D_IMM
8253 0U, // GLD1SW_D_SCALED
8254 0U, // GLD1SW_D_SXTW
8255 0U, // GLD1SW_D_SXTW_SCALED
8256 0U, // GLD1SW_D_UXTW
8257 0U, // GLD1SW_D_UXTW_SCALED
8258 0U, // GLD1W_D
8259 0U, // GLD1W_D_IMM
8260 0U, // GLD1W_D_SCALED
8261 0U, // GLD1W_D_SXTW
8262 0U, // GLD1W_D_SXTW_SCALED
8263 0U, // GLD1W_D_UXTW
8264 0U, // GLD1W_D_UXTW_SCALED
8265 0U, // GLD1W_IMM
8266 0U, // GLD1W_SXTW
8267 0U, // GLD1W_SXTW_SCALED
8268 0U, // GLD1W_UXTW
8269 0U, // GLD1W_UXTW_SCALED
8270 0U, // GLDFF1B_D
8271 0U, // GLDFF1B_D_IMM
8272 0U, // GLDFF1B_D_SXTW
8273 0U, // GLDFF1B_D_UXTW
8274 0U, // GLDFF1B_S_IMM
8275 0U, // GLDFF1B_S_SXTW
8276 0U, // GLDFF1B_S_UXTW
8277 0U, // GLDFF1D
8278 0U, // GLDFF1D_IMM
8279 0U, // GLDFF1D_SCALED
8280 0U, // GLDFF1D_SXTW
8281 0U, // GLDFF1D_SXTW_SCALED
8282 0U, // GLDFF1D_UXTW
8283 0U, // GLDFF1D_UXTW_SCALED
8284 0U, // GLDFF1H_D
8285 0U, // GLDFF1H_D_IMM
8286 0U, // GLDFF1H_D_SCALED
8287 0U, // GLDFF1H_D_SXTW
8288 0U, // GLDFF1H_D_SXTW_SCALED
8289 0U, // GLDFF1H_D_UXTW
8290 0U, // GLDFF1H_D_UXTW_SCALED
8291 0U, // GLDFF1H_S_IMM
8292 0U, // GLDFF1H_S_SXTW
8293 0U, // GLDFF1H_S_SXTW_SCALED
8294 0U, // GLDFF1H_S_UXTW
8295 0U, // GLDFF1H_S_UXTW_SCALED
8296 0U, // GLDFF1SB_D
8297 0U, // GLDFF1SB_D_IMM
8298 0U, // GLDFF1SB_D_SXTW
8299 0U, // GLDFF1SB_D_UXTW
8300 0U, // GLDFF1SB_S_IMM
8301 0U, // GLDFF1SB_S_SXTW
8302 0U, // GLDFF1SB_S_UXTW
8303 0U, // GLDFF1SH_D
8304 0U, // GLDFF1SH_D_IMM
8305 0U, // GLDFF1SH_D_SCALED
8306 0U, // GLDFF1SH_D_SXTW
8307 0U, // GLDFF1SH_D_SXTW_SCALED
8308 0U, // GLDFF1SH_D_UXTW
8309 0U, // GLDFF1SH_D_UXTW_SCALED
8310 0U, // GLDFF1SH_S_IMM
8311 0U, // GLDFF1SH_S_SXTW
8312 0U, // GLDFF1SH_S_SXTW_SCALED
8313 0U, // GLDFF1SH_S_UXTW
8314 0U, // GLDFF1SH_S_UXTW_SCALED
8315 0U, // GLDFF1SW_D
8316 0U, // GLDFF1SW_D_IMM
8317 0U, // GLDFF1SW_D_SCALED
8318 0U, // GLDFF1SW_D_SXTW
8319 0U, // GLDFF1SW_D_SXTW_SCALED
8320 0U, // GLDFF1SW_D_UXTW
8321 0U, // GLDFF1SW_D_UXTW_SCALED
8322 0U, // GLDFF1W_D
8323 0U, // GLDFF1W_D_IMM
8324 0U, // GLDFF1W_D_SCALED
8325 0U, // GLDFF1W_D_SXTW
8326 0U, // GLDFF1W_D_SXTW_SCALED
8327 0U, // GLDFF1W_D_UXTW
8328 0U, // GLDFF1W_D_UXTW_SCALED
8329 0U, // GLDFF1W_IMM
8330 0U, // GLDFF1W_SXTW
8331 0U, // GLDFF1W_SXTW_SCALED
8332 0U, // GLDFF1W_UXTW
8333 0U, // GLDFF1W_UXTW_SCALED
8334 0U, // G_ADD_LOW
8335 0U, // G_DUP
8336 0U, // G_DUPLANE16
8337 0U, // G_DUPLANE32
8338 0U, // G_DUPLANE64
8339 0U, // G_DUPLANE8
8340 0U, // G_EXT
8341 0U, // G_REV16
8342 0U, // G_REV32
8343 0U, // G_REV64
8344 0U, // G_SITOF
8345 0U, // G_TRN1
8346 0U, // G_TRN2
8347 0U, // G_UITOF
8348 0U, // G_UZP1
8349 0U, // G_UZP2
8350 0U, // G_VASHR
8351 0U, // G_VLSHR
8352 0U, // G_ZIP1
8353 0U, // G_ZIP2
8354 0U, // HWASAN_CHECK_MEMACCESS
8355 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES
8356 0U, // IRGstack
8357 0U, // JumpTableDest16
8358 0U, // JumpTableDest32
8359 0U, // JumpTableDest8
8360 0U, // LD1B_D_IMM
8361 0U, // LD1B_H_IMM
8362 0U, // LD1B_IMM
8363 0U, // LD1B_S_IMM
8364 0U, // LD1D_IMM
8365 0U, // LD1H_D_IMM
8366 0U, // LD1H_IMM
8367 0U, // LD1H_S_IMM
8368 0U, // LD1SB_D_IMM
8369 0U, // LD1SB_H_IMM
8370 0U, // LD1SB_S_IMM
8371 0U, // LD1SH_D_IMM
8372 0U, // LD1SH_S_IMM
8373 0U, // LD1SW_D_IMM
8374 0U, // LD1W_D_IMM
8375 0U, // LD1W_IMM
8376 0U, // LDFF1B
8377 0U, // LDFF1B_D
8378 0U, // LDFF1B_H
8379 0U, // LDFF1B_S
8380 0U, // LDFF1D
8381 0U, // LDFF1H
8382 0U, // LDFF1H_D
8383 0U, // LDFF1H_S
8384 0U, // LDFF1SB_D
8385 0U, // LDFF1SB_H
8386 0U, // LDFF1SB_S
8387 0U, // LDFF1SH_D
8388 0U, // LDFF1SH_S
8389 0U, // LDFF1SW_D
8390 0U, // LDFF1W
8391 0U, // LDFF1W_D
8392 0U, // LDNF1B_D_IMM
8393 0U, // LDNF1B_H_IMM
8394 0U, // LDNF1B_IMM
8395 0U, // LDNF1B_S_IMM
8396 0U, // LDNF1D_IMM
8397 0U, // LDNF1H_D_IMM
8398 0U, // LDNF1H_IMM
8399 0U, // LDNF1H_S_IMM
8400 0U, // LDNF1SB_D_IMM
8401 0U, // LDNF1SB_H_IMM
8402 0U, // LDNF1SB_S_IMM
8403 0U, // LDNF1SH_D_IMM
8404 0U, // LDNF1SH_S_IMM
8405 0U, // LDNF1SW_D_IMM
8406 0U, // LDNF1W_D_IMM
8407 0U, // LDNF1W_IMM
8408 0U, // LDR_ZZXI
8409 0U, // LDR_ZZZXI
8410 0U, // LDR_ZZZZXI
8411 0U, // LOADgot
8412 0U, // LSL_ZPZI_UNDEF_B
8413 0U, // LSL_ZPZI_UNDEF_D
8414 0U, // LSL_ZPZI_UNDEF_H
8415 0U, // LSL_ZPZI_UNDEF_S
8416 0U, // LSL_ZPZZ_UNDEF_B
8417 0U, // LSL_ZPZZ_UNDEF_D
8418 0U, // LSL_ZPZZ_UNDEF_H
8419 0U, // LSL_ZPZZ_UNDEF_S
8420 0U, // LSL_ZPZZ_ZERO_B
8421 0U, // LSL_ZPZZ_ZERO_D
8422 0U, // LSL_ZPZZ_ZERO_H
8423 0U, // LSL_ZPZZ_ZERO_S
8424 0U, // LSR_ZPZI_UNDEF_B
8425 0U, // LSR_ZPZI_UNDEF_D
8426 0U, // LSR_ZPZI_UNDEF_H
8427 0U, // LSR_ZPZI_UNDEF_S
8428 0U, // LSR_ZPZZ_UNDEF_B
8429 0U, // LSR_ZPZZ_UNDEF_D
8430 0U, // LSR_ZPZZ_UNDEF_H
8431 0U, // LSR_ZPZZ_UNDEF_S
8432 0U, // LSR_ZPZZ_ZERO_B
8433 0U, // LSR_ZPZZ_ZERO_D
8434 0U, // LSR_ZPZZ_ZERO_H
8435 0U, // LSR_ZPZZ_ZERO_S
8436 0U, // MOVMCSym
8437 0U, // MOVaddr
8438 0U, // MOVaddrBA
8439 0U, // MOVaddrCP
8440 0U, // MOVaddrEXT
8441 0U, // MOVaddrJT
8442 0U, // MOVaddrTLS
8443 0U, // MOVbaseTLS
8444 0U, // MOVi32imm
8445 0U, // MOVi64imm
8446 0U, // MUL_ZPZZ_UNDEF_B
8447 0U, // MUL_ZPZZ_UNDEF_D
8448 0U, // MUL_ZPZZ_UNDEF_H
8449 0U, // MUL_ZPZZ_UNDEF_S
8450 0U, // ORNWrr
8451 0U, // ORNXrr
8452 0U, // ORRWrr
8453 0U, // ORRXrr
8454 0U, // RDFFR_P
8455 0U, // RDFFR_PPz
8456 0U, // RET_ReallyLR
8457 0U, // SDIV_ZPZZ_UNDEF_D
8458 0U, // SDIV_ZPZZ_UNDEF_S
8459 0U, // SEH_AddFP
8460 0U, // SEH_EpilogEnd
8461 0U, // SEH_EpilogStart
8462 0U, // SEH_Nop
8463 0U, // SEH_PrologEnd
8464 0U, // SEH_SaveFPLR
8465 0U, // SEH_SaveFPLR_X
8466 0U, // SEH_SaveFReg
8467 0U, // SEH_SaveFRegP
8468 0U, // SEH_SaveFRegP_X
8469 0U, // SEH_SaveFReg_X
8470 0U, // SEH_SaveReg
8471 0U, // SEH_SaveRegP
8472 0U, // SEH_SaveRegP_X
8473 0U, // SEH_SaveReg_X
8474 0U, // SEH_SetFP
8475 0U, // SEH_StackAlloc
8476 0U, // SMAX_ZPZZ_UNDEF_B
8477 0U, // SMAX_ZPZZ_UNDEF_D
8478 0U, // SMAX_ZPZZ_UNDEF_H
8479 0U, // SMAX_ZPZZ_UNDEF_S
8480 0U, // SMIN_ZPZZ_UNDEF_B
8481 0U, // SMIN_ZPZZ_UNDEF_D
8482 0U, // SMIN_ZPZZ_UNDEF_H
8483 0U, // SMIN_ZPZZ_UNDEF_S
8484 0U, // SPACE
8485 0U, // SQSHLU_ZPZI_ZERO_B
8486 0U, // SQSHLU_ZPZI_ZERO_D
8487 0U, // SQSHLU_ZPZI_ZERO_H
8488 0U, // SQSHLU_ZPZI_ZERO_S
8489 0U, // SQSHL_ZPZI_ZERO_B
8490 0U, // SQSHL_ZPZI_ZERO_D
8491 0U, // SQSHL_ZPZI_ZERO_H
8492 0U, // SQSHL_ZPZI_ZERO_S
8493 0U, // SRSHR_ZPZI_ZERO_B
8494 0U, // SRSHR_ZPZI_ZERO_D
8495 0U, // SRSHR_ZPZI_ZERO_H
8496 0U, // SRSHR_ZPZI_ZERO_S
8497 0U, // STGloop
8498 0U, // STGloop_wback
8499 0U, // STR_ZZXI
8500 0U, // STR_ZZZXI
8501 0U, // STR_ZZZZXI
8502 0U, // STZGloop
8503 0U, // STZGloop_wback
8504 0U, // SUBR_ZPZZ_ZERO_B
8505 0U, // SUBR_ZPZZ_ZERO_D
8506 0U, // SUBR_ZPZZ_ZERO_H
8507 0U, // SUBR_ZPZZ_ZERO_S
8508 0U, // SUBSWrr
8509 0U, // SUBSXrr
8510 0U, // SUBWrr
8511 0U, // SUBXrr
8512 0U, // SUB_ZPZZ_UNDEF_B
8513 0U, // SUB_ZPZZ_UNDEF_D
8514 0U, // SUB_ZPZZ_UNDEF_H
8515 0U, // SUB_ZPZZ_UNDEF_S
8516 0U, // SUB_ZPZZ_ZERO_B
8517 0U, // SUB_ZPZZ_ZERO_D
8518 0U, // SUB_ZPZZ_ZERO_H
8519 0U, // SUB_ZPZZ_ZERO_S
8520 0U, // SpeculationBarrierISBDSBEndBB
8521 0U, // SpeculationBarrierSBEndBB
8522 0U, // SpeculationSafeValueW
8523 0U, // SpeculationSafeValueX
8524 0U, // TAGPstack
8525 0U, // TCRETURNdi
8526 0U, // TCRETURNri
8527 0U, // TCRETURNriALL
8528 0U, // TCRETURNriBTI
8529 0U, // TLSDESCCALL
8530 0U, // TLSDESC_CALLSEQ
8531 0U, // UDIV_ZPZZ_UNDEF_D
8532 0U, // UDIV_ZPZZ_UNDEF_S
8533 0U, // UMAX_ZPZZ_UNDEF_B
8534 0U, // UMAX_ZPZZ_UNDEF_D
8535 0U, // UMAX_ZPZZ_UNDEF_H
8536 0U, // UMAX_ZPZZ_UNDEF_S
8537 0U, // UMIN_ZPZZ_UNDEF_B
8538 0U, // UMIN_ZPZZ_UNDEF_D
8539 0U, // UMIN_ZPZZ_UNDEF_H
8540 0U, // UMIN_ZPZZ_UNDEF_S
8541 0U, // UQSHL_ZPZI_ZERO_B
8542 0U, // UQSHL_ZPZI_ZERO_D
8543 0U, // UQSHL_ZPZI_ZERO_H
8544 0U, // UQSHL_ZPZI_ZERO_S
8545 0U, // URSHR_ZPZI_ZERO_B
8546 0U, // URSHR_ZPZI_ZERO_D
8547 0U, // URSHR_ZPZI_ZERO_H
8548 0U, // URSHR_ZPZI_ZERO_S
8549 0U, // ABS_ZPmZ_B
8550 2U, // ABS_ZPmZ_D
8551 0U, // ABS_ZPmZ_H
8552 4U, // ABS_ZPmZ_S
8553 6U, // ABSv16i8
8554 6U, // ABSv1i64
8555 6U, // ABSv2i32
8556 6U, // ABSv2i64
8557 6U, // ABSv4i16
8558 6U, // ABSv4i32
8559 6U, // ABSv8i16
8560 6U, // ABSv8i8
8561 264U, // ADCLB_ZZZ_D
8562 520U, // ADCLB_ZZZ_S
8563 264U, // ADCLT_ZZZ_D
8564 520U, // ADCLT_ZZZ_S
8565 776U, // ADCSWr
8566 776U, // ADCSXr
8567 776U, // ADCWr
8568 776U, // ADCXr
8569 33800U, // ADDG
8570 1288U, // ADDHNB_ZZZ_B
8571 10U, // ADDHNB_ZZZ_H
8572 1544U, // ADDHNB_ZZZ_S
8573 1800U, // ADDHNT_ZZZ_B
8574 4U, // ADDHNT_ZZZ_H
8575 264U, // ADDHNT_ZZZ_S
8576 2056U, // ADDHNv2i64_v2i32
8577 2312U, // ADDHNv2i64_v4i32
8578 2056U, // ADDHNv4i32_v4i16
8579 2312U, // ADDHNv4i32_v8i16
8580 2312U, // ADDHNv8i16_v16i8
8581 2056U, // ADDHNv8i16_v8i8
8582 776U, // ADDPL_XXI
8583 1083916U, // ADDP_ZPmZ_B
8584 2131468U, // ADDP_ZPmZ_D
8585 3214094U, // ADDP_ZPmZ_H
8586 4230156U, // ADDP_ZPmZ_S
8587 2056U, // ADDPv16i8
8588 2056U, // ADDPv2i32
8589 2056U, // ADDPv2i64
8590 6U, // ADDPv2i64p
8591 2056U, // ADDPv4i16
8592 2056U, // ADDPv4i32
8593 2056U, // ADDPv8i16
8594 2056U, // ADDPv8i8
8595 3336U, // ADDSWri
8596 3592U, // ADDSWrs
8597 3848U, // ADDSWrx
8598 3336U, // ADDSXri
8599 3592U, // ADDSXrs
8600 3848U, // ADDSXrx
8601 99080U, // ADDSXrx64
8602 776U, // ADDVL_XXI
8603 6U, // ADDVv16i8v
8604 6U, // ADDVv4i16v
8605 6U, // ADDVv4i32v
8606 6U, // ADDVv8i16v
8607 6U, // ADDVv8i8v
8608 3336U, // ADDWri
8609 3592U, // ADDWrs
8610 3848U, // ADDWrx
8611 3336U, // ADDXri
8612 3592U, // ADDXrs
8613 3848U, // ADDXrx
8614 99080U, // ADDXrx64
8615 4104U, // ADD_ZI_B
8616 4360U, // ADD_ZI_D
8617 16U, // ADD_ZI_H
8618 4616U, // ADD_ZI_S
8619 1083916U, // ADD_ZPmZ_B
8620 2131468U, // ADD_ZPmZ_D
8621 3214094U, // ADD_ZPmZ_H
8622 4230156U, // ADD_ZPmZ_S
8623 2568U, // ADD_ZZZ_B
8624 1544U, // ADD_ZZZ_D
8625 14U, // ADD_ZZZ_H
8626 3080U, // ADD_ZZZ_S
8627 2056U, // ADDv16i8
8628 776U, // ADDv1i64
8629 2056U, // ADDv2i32
8630 2056U, // ADDv2i64
8631 2056U, // ADDv4i16
8632 2056U, // ADDv4i32
8633 2056U, // ADDv8i16
8634 2056U, // ADDv8i8
8635 6U, // ADR
8636 0U, // ADRP
8637 4872U, // ADR_LSL_ZZZ_D_0
8638 5128U, // ADR_LSL_ZZZ_D_1
8639 5384U, // ADR_LSL_ZZZ_D_2
8640 5640U, // ADR_LSL_ZZZ_D_3
8641 5896U, // ADR_LSL_ZZZ_S_0
8642 6152U, // ADR_LSL_ZZZ_S_1
8643 6408U, // ADR_LSL_ZZZ_S_2
8644 6664U, // ADR_LSL_ZZZ_S_3
8645 6920U, // ADR_SXTW_ZZZ_D_0
8646 7176U, // ADR_SXTW_ZZZ_D_1
8647 7432U, // ADR_SXTW_ZZZ_D_2
8648 7688U, // ADR_SXTW_ZZZ_D_3
8649 7944U, // ADR_UXTW_ZZZ_D_0
8650 8200U, // ADR_UXTW_ZZZ_D_1
8651 8456U, // ADR_UXTW_ZZZ_D_2
8652 8712U, // ADR_UXTW_ZZZ_D_3
8653 2568U, // AESD_ZZZ_B
8654 6U, // AESDrr
8655 2568U, // AESE_ZZZ_B
8656 6U, // AESErr
8657 6U, // AESIMC_ZZ_B
8658 6U, // AESIMCrr
8659 6U, // AESMC_ZZ_B
8660 6U, // AESMCrr
8661 8968U, // ANDSWri
8662 3592U, // ANDSWrs
8663 9224U, // ANDSXri
8664 3592U, // ANDSXrs
8665 1083922U, // ANDS_PPzPP
8666 0U, // ANDV_VPZ_B
8667 0U, // ANDV_VPZ_D
8668 0U, // ANDV_VPZ_H
8669 0U, // ANDV_VPZ_S
8670 8968U, // ANDWri
8671 3592U, // ANDWrs
8672 9224U, // ANDXri
8673 3592U, // ANDXrs
8674 1083922U, // AND_PPzPP
8675 9224U, // AND_ZI
8676 1083916U, // AND_ZPmZ_B
8677 2131468U, // AND_ZPmZ_D
8678 3214094U, // AND_ZPmZ_H
8679 4230156U, // AND_ZPmZ_S
8680 1544U, // AND_ZZZ
8681 2056U, // ANDv16i8
8682 2056U, // ANDv8i8
8683 35340U, // ASRD_ZPmI_B
8684 34316U, // ASRD_ZPmI_D
8685 133902U, // ASRD_ZPmI_H
8686 35852U, // ASRD_ZPmI_S
8687 1083916U, // ASRR_ZPmZ_B
8688 2131468U, // ASRR_ZPmZ_D
8689 3214094U, // ASRR_ZPmZ_H
8690 4230156U, // ASRR_ZPmZ_S
8691 776U, // ASRVWr
8692 776U, // ASRVXr
8693 2132492U, // ASR_WIDE_ZPmZ_B
8694 166670U, // ASR_WIDE_ZPmZ_H
8695 2133004U, // ASR_WIDE_ZPmZ_S
8696 1544U, // ASR_WIDE_ZZZ_B
8697 20U, // ASR_WIDE_ZZZ_H
8698 1544U, // ASR_WIDE_ZZZ_S
8699 35340U, // ASR_ZPmI_B
8700 34316U, // ASR_ZPmI_D
8701 133902U, // ASR_ZPmI_H
8702 35852U, // ASR_ZPmI_S
8703 1083916U, // ASR_ZPmZ_B
8704 2131468U, // ASR_ZPmZ_D
8705 3214094U, // ASR_ZPmZ_H
8706 4230156U, // ASR_ZPmZ_S
8707 776U, // ASR_ZZI_B
8708 776U, // ASR_ZZI_D
8709 22U, // ASR_ZZI_H
8710 776U, // ASR_ZZI_S
8711 6U, // AUTDA
8712 6U, // AUTDB
8713 0U, // AUTDZA
8714 0U, // AUTDZB
8715 6U, // AUTIA
8716 0U, // AUTIA1716
8717 0U, // AUTIASP
8718 0U, // AUTIAZ
8719 6U, // AUTIB
8720 0U, // AUTIB1716
8721 0U, // AUTIBSP
8722 0U, // AUTIBZ
8723 0U, // AUTIZA
8724 0U, // AUTIZB
8725 0U, // AXFLAG
8726 0U, // B
8727 5277704U, // BCAX
8728 2131464U, // BCAX_ZZZZ
8729 2568U, // BDEP_ZZZ_B
8730 1544U, // BDEP_ZZZ_D
8731 14U, // BDEP_ZZZ_H
8732 3080U, // BDEP_ZZZ_S
8733 2568U, // BEXT_ZZZ_B
8734 1544U, // BEXT_ZZZ_D
8735 14U, // BEXT_ZZZ_H
8736 3080U, // BEXT_ZZZ_S
8737 3344648U, // BF16DOTlanev4bf16
8738 3344648U, // BF16DOTlanev8bf16
8739 6U, // BFCVT
8740 6U, // BFCVTN
8741 6U, // BFCVTN2
8742 0U, // BFCVTNT_ZPmZ
8743 0U, // BFCVT_ZPmZ
8744 3344136U, // BFDOT_ZZI
8745 1800U, // BFDOT_ZZZ
8746 0U, // BFDOTv4bf16
8747 0U, // BFDOTv8bf16
8748 0U, // BFMLALB
8749 0U, // BFMLALBIdx
8750 0U, // BFMLALT
8751 0U, // BFMLALTIdx
8752 0U, // BFMMLA
8753 3344136U, // BFMMLA_B_ZZI
8754 1800U, // BFMMLA_B_ZZZ
8755 3344136U, // BFMMLA_T_ZZI
8756 1800U, // BFMMLA_T_ZZZ
8757 1800U, // BFMMLA_ZZZ
8758 6333704U, // BFMWri
8759 6333704U, // BFMXri
8760 2568U, // BGRP_ZZZ_B
8761 1544U, // BGRP_ZZZ_D
8762 14U, // BGRP_ZZZ_H
8763 3080U, // BGRP_ZZZ_S
8764 3592U, // BICSWrs
8765 3592U, // BICSXrs
8766 1083922U, // BICS_PPzPP
8767 3592U, // BICWrs
8768 3592U, // BICXrs
8769 1083922U, // BIC_PPzPP
8770 1083916U, // BIC_ZPmZ_B
8771 2131468U, // BIC_ZPmZ_D
8772 3214094U, // BIC_ZPmZ_H
8773 4230156U, // BIC_ZPmZ_S
8774 1544U, // BIC_ZZZ
8775 2056U, // BICv16i8
8776 0U, // BICv2i32
8777 0U, // BICv4i16
8778 0U, // BICv4i32
8779 0U, // BICv8i16
8780 2056U, // BICv8i8
8781 2312U, // BIFv16i8
8782 2312U, // BIFv8i8
8783 2312U, // BITv16i8
8784 2312U, // BITv8i8
8785 0U, // BL
8786 0U, // BLR
8787 6U, // BLRAA
8788 0U, // BLRAAZ
8789 6U, // BLRAB
8790 0U, // BLRABZ
8791 0U, // BR
8792 6U, // BRAA
8793 0U, // BRAAZ
8794 6U, // BRAB
8795 0U, // BRABZ
8796 0U, // BRB_IALL
8797 0U, // BRB_INJ
8798 0U, // BRK
8799 2578U, // BRKAS_PPzP
8800 0U, // BRKA_PPmP
8801 2578U, // BRKA_PPzP
8802 2578U, // BRKBS_PPzP
8803 0U, // BRKB_PPmP
8804 2578U, // BRKB_PPzP
8805 1083922U, // BRKNS_PPzP
8806 1083922U, // BRKN_PPzP
8807 1083922U, // BRKPAS_PPzPP
8808 1083922U, // BRKPA_PPzPP
8809 1083922U, // BRKPBS_PPzPP
8810 1083922U, // BRKPB_PPzPP
8811 2131464U, // BSL1N_ZZZZ
8812 2131464U, // BSL2N_ZZZZ
8813 2131464U, // BSL_ZZZZ
8814 2312U, // BSLv16i8
8815 2312U, // BSLv8i8
8816 0U, // Bcc
8817 7375368U, // CADD_ZZI_B
8818 7374344U, // CADD_ZZI_D
8819 232206U, // CADD_ZZI_H
8820 7375880U, // CADD_ZZI_S
8821 271640U, // CASAB
8822 271640U, // CASAH
8823 271640U, // CASALB
8824 271640U, // CASALH
8825 271640U, // CASALW
8826 271640U, // CASALX
8827 271640U, // CASAW
8828 271640U, // CASAX
8829 271640U, // CASB
8830 271640U, // CASH
8831 271640U, // CASLB
8832 271640U, // CASLH
8833 271640U, // CASLW
8834 271640U, // CASLX
8835 0U, // CASPALW
8836 0U, // CASPALX
8837 0U, // CASPAW
8838 0U, // CASPAX
8839 0U, // CASPLW
8840 0U, // CASPLX
8841 0U, // CASPW
8842 0U, // CASPX
8843 271640U, // CASW
8844 271640U, // CASX
8845 0U, // CBNZW
8846 0U, // CBNZX
8847 0U, // CBZW
8848 0U, // CBZX
8849 8422152U, // CCMNWi
8850 8422152U, // CCMNWr
8851 8422152U, // CCMNXi
8852 8422152U, // CCMNXr
8853 8422152U, // CCMPWi
8854 8422152U, // CCMPWr
8855 8422152U, // CCMPXi
8856 8422152U, // CCMPXr
8857 76744456U, // CDOT_ZZZI_D
8858 10528256U, // CDOT_ZZZI_S
8859 11568904U, // CDOT_ZZZ_D
8860 297728U, // CDOT_ZZZ_S
8861 0U, // CFINV
8862 1082120U, // CLASTA_RPZ_B
8863 2130696U, // CLASTA_RPZ_D
8864 12616456U, // CLASTA_RPZ_H
8865 4227848U, // CLASTA_RPZ_S
8866 1082120U, // CLASTA_VPZ_B
8867 2130696U, // CLASTA_VPZ_D
8868 12616456U, // CLASTA_VPZ_H
8869 4227848U, // CLASTA_VPZ_S
8870 1083912U, // CLASTA_ZPZ_B
8871 2131464U, // CLASTA_ZPZ_D
8872 3214094U, // CLASTA_ZPZ_H
8873 4230152U, // CLASTA_ZPZ_S
8874 1082120U, // CLASTB_RPZ_B
8875 2130696U, // CLASTB_RPZ_D
8876 12616456U, // CLASTB_RPZ_H
8877 4227848U, // CLASTB_RPZ_S
8878 1082120U, // CLASTB_VPZ_B
8879 2130696U, // CLASTB_VPZ_D
8880 12616456U, // CLASTB_VPZ_H
8881 4227848U, // CLASTB_VPZ_S
8882 1083912U, // CLASTB_ZPZ_B
8883 2131464U, // CLASTB_ZPZ_D
8884 3214094U, // CLASTB_ZPZ_H
8885 4230152U, // CLASTB_ZPZ_S
8886 0U, // CLREX
8887 6U, // CLSWr
8888 6U, // CLSXr
8889 0U, // CLS_ZPmZ_B
8890 2U, // CLS_ZPmZ_D
8891 0U, // CLS_ZPmZ_H
8892 4U, // CLS_ZPmZ_S
8893 6U, // CLSv16i8
8894 6U, // CLSv2i32
8895 6U, // CLSv4i16
8896 6U, // CLSv4i32
8897 6U, // CLSv8i16
8898 6U, // CLSv8i8
8899 6U, // CLZWr
8900 6U, // CLZXr
8901 0U, // CLZ_ZPmZ_B
8902 2U, // CLZ_ZPmZ_D
8903 0U, // CLZ_ZPmZ_H
8904 4U, // CLZ_ZPmZ_S
8905 6U, // CLZv16i8
8906 6U, // CLZv2i32
8907 6U, // CLZv4i16
8908 6U, // CLZv4i32
8909 6U, // CLZv8i16
8910 6U, // CLZv8i8
8911 2056U, // CMEQv16i8
8912 26U, // CMEQv16i8rz
8913 776U, // CMEQv1i64
8914 26U, // CMEQv1i64rz
8915 2056U, // CMEQv2i32
8916 26U, // CMEQv2i32rz
8917 2056U, // CMEQv2i64
8918 26U, // CMEQv2i64rz
8919 2056U, // CMEQv4i16
8920 26U, // CMEQv4i16rz
8921 2056U, // CMEQv4i32
8922 26U, // CMEQv4i32rz
8923 2056U, // CMEQv8i16
8924 26U, // CMEQv8i16rz
8925 2056U, // CMEQv8i8
8926 26U, // CMEQv8i8rz
8927 2056U, // CMGEv16i8
8928 26U, // CMGEv16i8rz
8929 776U, // CMGEv1i64
8930 26U, // CMGEv1i64rz
8931 2056U, // CMGEv2i32
8932 26U, // CMGEv2i32rz
8933 2056U, // CMGEv2i64
8934 26U, // CMGEv2i64rz
8935 2056U, // CMGEv4i16
8936 26U, // CMGEv4i16rz
8937 2056U, // CMGEv4i32
8938 26U, // CMGEv4i32rz
8939 2056U, // CMGEv8i16
8940 26U, // CMGEv8i16rz
8941 2056U, // CMGEv8i8
8942 26U, // CMGEv8i8rz
8943 2056U, // CMGTv16i8
8944 26U, // CMGTv16i8rz
8945 776U, // CMGTv1i64
8946 26U, // CMGTv1i64rz
8947 2056U, // CMGTv2i32
8948 26U, // CMGTv2i32rz
8949 2056U, // CMGTv2i64
8950 26U, // CMGTv2i64rz
8951 2056U, // CMGTv4i16
8952 26U, // CMGTv4i16rz
8953 2056U, // CMGTv4i32
8954 26U, // CMGTv4i32rz
8955 2056U, // CMGTv8i16
8956 26U, // CMGTv8i16rz
8957 2056U, // CMGTv8i8
8958 26U, // CMGTv8i8rz
8959 2056U, // CMHIv16i8
8960 776U, // CMHIv1i64
8961 2056U, // CMHIv2i32
8962 2056U, // CMHIv2i64
8963 2056U, // CMHIv4i16
8964 2056U, // CMHIv4i32
8965 2056U, // CMHIv8i16
8966 2056U, // CMHIv8i8
8967 2056U, // CMHSv16i8
8968 776U, // CMHSv1i64
8969 2056U, // CMHSv2i32
8970 2056U, // CMHSv2i64
8971 2056U, // CMHSv4i16
8972 2056U, // CMHSv4i32
8973 2056U, // CMHSv8i16
8974 2056U, // CMHSv8i8
8975 10528284U, // CMLA_ZZZI_H
8976 76743176U, // CMLA_ZZZI_S
8977 297728U, // CMLA_ZZZ_B
8978 11567368U, // CMLA_ZZZ_D
8979 297756U, // CMLA_ZZZ_H
8980 11567624U, // CMLA_ZZZ_S
8981 26U, // CMLEv16i8rz
8982 26U, // CMLEv1i64rz
8983 26U, // CMLEv2i32rz
8984 26U, // CMLEv2i64rz
8985 26U, // CMLEv4i16rz
8986 26U, // CMLEv4i32rz
8987 26U, // CMLEv8i16rz
8988 26U, // CMLEv8i8rz
8989 26U, // CMLTv16i8rz
8990 26U, // CMLTv1i64rz
8991 26U, // CMLTv2i32rz
8992 26U, // CMLTv2i64rz
8993 26U, // CMLTv4i16rz
8994 26U, // CMLTv4i32rz
8995 26U, // CMLTv8i16rz
8996 26U, // CMLTv8i8rz
8997 35346U, // CMPEQ_PPzZI_B
8998 34322U, // CMPEQ_PPzZI_D
8999 133902U, // CMPEQ_PPzZI_H
9000 35858U, // CMPEQ_PPzZI_S
9001 1083922U, // CMPEQ_PPzZZ_B
9002 2131474U, // CMPEQ_PPzZZ_D
9003 3214094U, // CMPEQ_PPzZZ_H
9004 4230162U, // CMPEQ_PPzZZ_S
9005 2132498U, // CMPEQ_WIDE_PPzZZ_B
9006 166670U, // CMPEQ_WIDE_PPzZZ_H
9007 2133010U, // CMPEQ_WIDE_PPzZZ_S
9008 35346U, // CMPGE_PPzZI_B
9009 34322U, // CMPGE_PPzZI_D
9010 133902U, // CMPGE_PPzZI_H
9011 35858U, // CMPGE_PPzZI_S
9012 1083922U, // CMPGE_PPzZZ_B
9013 2131474U, // CMPGE_PPzZZ_D
9014 3214094U, // CMPGE_PPzZZ_H
9015 4230162U, // CMPGE_PPzZZ_S
9016 2132498U, // CMPGE_WIDE_PPzZZ_B
9017 166670U, // CMPGE_WIDE_PPzZZ_H
9018 2133010U, // CMPGE_WIDE_PPzZZ_S
9019 35346U, // CMPGT_PPzZI_B
9020 34322U, // CMPGT_PPzZI_D
9021 133902U, // CMPGT_PPzZI_H
9022 35858U, // CMPGT_PPzZI_S
9023 1083922U, // CMPGT_PPzZZ_B
9024 2131474U, // CMPGT_PPzZZ_D
9025 3214094U, // CMPGT_PPzZZ_H
9026 4230162U, // CMPGT_PPzZZ_S
9027 2132498U, // CMPGT_WIDE_PPzZZ_B
9028 166670U, // CMPGT_WIDE_PPzZZ_H
9029 2133010U, // CMPGT_WIDE_PPzZZ_S
9030 13666834U, // CMPHI_PPzZI_B
9031 13665810U, // CMPHI_PPzZI_D
9032 330510U, // CMPHI_PPzZI_H
9033 13667346U, // CMPHI_PPzZI_S
9034 1083922U, // CMPHI_PPzZZ_B
9035 2131474U, // CMPHI_PPzZZ_D
9036 3214094U, // CMPHI_PPzZZ_H
9037 4230162U, // CMPHI_PPzZZ_S
9038 2132498U, // CMPHI_WIDE_PPzZZ_B
9039 166670U, // CMPHI_WIDE_PPzZZ_H
9040 2133010U, // CMPHI_WIDE_PPzZZ_S
9041 13666834U, // CMPHS_PPzZI_B
9042 13665810U, // CMPHS_PPzZI_D
9043 330510U, // CMPHS_PPzZI_H
9044 13667346U, // CMPHS_PPzZI_S
9045 1083922U, // CMPHS_PPzZZ_B
9046 2131474U, // CMPHS_PPzZZ_D
9047 3214094U, // CMPHS_PPzZZ_H
9048 4230162U, // CMPHS_PPzZZ_S
9049 2132498U, // CMPHS_WIDE_PPzZZ_B
9050 166670U, // CMPHS_WIDE_PPzZZ_H
9051 2133010U, // CMPHS_WIDE_PPzZZ_S
9052 35346U, // CMPLE_PPzZI_B
9053 34322U, // CMPLE_PPzZI_D
9054 133902U, // CMPLE_PPzZI_H
9055 35858U, // CMPLE_PPzZI_S
9056 2132498U, // CMPLE_WIDE_PPzZZ_B
9057 166670U, // CMPLE_WIDE_PPzZZ_H
9058 2133010U, // CMPLE_WIDE_PPzZZ_S
9059 13666834U, // CMPLO_PPzZI_B
9060 13665810U, // CMPLO_PPzZI_D
9061 330510U, // CMPLO_PPzZI_H
9062 13667346U, // CMPLO_PPzZI_S
9063 2132498U, // CMPLO_WIDE_PPzZZ_B
9064 166670U, // CMPLO_WIDE_PPzZZ_H
9065 2133010U, // CMPLO_WIDE_PPzZZ_S
9066 13666834U, // CMPLS_PPzZI_B
9067 13665810U, // CMPLS_PPzZI_D
9068 330510U, // CMPLS_PPzZI_H
9069 13667346U, // CMPLS_PPzZI_S
9070 2132498U, // CMPLS_WIDE_PPzZZ_B
9071 166670U, // CMPLS_WIDE_PPzZZ_H
9072 2133010U, // CMPLS_WIDE_PPzZZ_S
9073 35346U, // CMPLT_PPzZI_B
9074 34322U, // CMPLT_PPzZI_D
9075 133902U, // CMPLT_PPzZI_H
9076 35858U, // CMPLT_PPzZI_S
9077 2132498U, // CMPLT_WIDE_PPzZZ_B
9078 166670U, // CMPLT_WIDE_PPzZZ_H
9079 2133010U, // CMPLT_WIDE_PPzZZ_S
9080 35346U, // CMPNE_PPzZI_B
9081 34322U, // CMPNE_PPzZI_D
9082 133902U, // CMPNE_PPzZI_H
9083 35858U, // CMPNE_PPzZI_S
9084 1083922U, // CMPNE_PPzZZ_B
9085 2131474U, // CMPNE_PPzZZ_D
9086 3214094U, // CMPNE_PPzZZ_H
9087 4230162U, // CMPNE_PPzZZ_S
9088 2132498U, // CMPNE_WIDE_PPzZZ_B
9089 166670U, // CMPNE_WIDE_PPzZZ_H
9090 2133010U, // CMPNE_WIDE_PPzZZ_S
9091 2056U, // CMTSTv16i8
9092 776U, // CMTSTv1i64
9093 2056U, // CMTSTv2i32
9094 2056U, // CMTSTv2i64
9095 2056U, // CMTSTv4i16
9096 2056U, // CMTSTv4i32
9097 2056U, // CMTSTv8i16
9098 2056U, // CMTSTv8i8
9099 0U, // CNOT_ZPmZ_B
9100 2U, // CNOT_ZPmZ_D
9101 0U, // CNOT_ZPmZ_H
9102 4U, // CNOT_ZPmZ_S
9103 30U, // CNTB_XPiI
9104 30U, // CNTD_XPiI
9105 30U, // CNTH_XPiI
9106 2568U, // CNTP_XPP_B
9107 1544U, // CNTP_XPP_D
9108 1288U, // CNTP_XPP_H
9109 3080U, // CNTP_XPP_S
9110 30U, // CNTW_XPiI
9111 0U, // CNT_ZPmZ_B
9112 2U, // CNT_ZPmZ_D
9113 0U, // CNT_ZPmZ_H
9114 4U, // CNT_ZPmZ_S
9115 6U, // CNTv16i8
9116 6U, // CNTv8i8
9117 1544U, // COMPACT_ZPZ_D
9118 3080U, // COMPACT_ZPZ_S
9119 32U, // CPY_ZPmI_B
9120 34U, // CPY_ZPmI_D
9121 0U, // CPY_ZPmI_H
9122 36U, // CPY_ZPmI_S
9123 38U, // CPY_ZPmR_B
9124 38U, // CPY_ZPmR_D
9125 0U, // CPY_ZPmR_H
9126 38U, // CPY_ZPmR_S
9127 38U, // CPY_ZPmV_B
9128 38U, // CPY_ZPmV_D
9129 0U, // CPY_ZPmV_H
9130 38U, // CPY_ZPmV_S
9131 10002U, // CPY_ZPzI_B
9132 10258U, // CPY_ZPzI_D
9133 40U, // CPY_ZPzI_H
9134 10514U, // CPY_ZPzI_S
9135 42U, // CPYi16
9136 42U, // CPYi32
9137 42U, // CPYi64
9138 42U, // CPYi8
9139 776U, // CRC32Brr
9140 776U, // CRC32CBrr
9141 776U, // CRC32CHrr
9142 776U, // CRC32CWrr
9143 776U, // CRC32CXrr
9144 776U, // CRC32Hrr
9145 776U, // CRC32Wrr
9146 776U, // CRC32Xrr
9147 8422152U, // CSELWr
9148 8422152U, // CSELXr
9149 8422152U, // CSINCWr
9150 8422152U, // CSINCXr
9151 8422152U, // CSINVWr
9152 8422152U, // CSINVXr
9153 8422152U, // CSNEGWr
9154 8422152U, // CSNEGXr
9155 6U, // CTERMEQ_WW
9156 6U, // CTERMEQ_XX
9157 6U, // CTERMNE_WW
9158 6U, // CTERMNE_XX
9159 0U, // DCPS1
9160 0U, // DCPS2
9161 0U, // DCPS3
9162 0U, // DECB_XPiI
9163 0U, // DECD_XPiI
9164 0U, // DECD_ZPiI
9165 0U, // DECH_XPiI
9166 0U, // DECH_ZPiI
9167 6U, // DECP_XP_B
9168 6U, // DECP_XP_D
9169 6U, // DECP_XP_H
9170 6U, // DECP_XP_S
9171 6U, // DECP_ZP_D
9172 0U, // DECP_ZP_H
9173 6U, // DECP_ZP_S
9174 0U, // DECW_XPiI
9175 0U, // DECW_ZPiI
9176 0U, // DMB
9177 0U, // DRPS
9178 0U, // DSB
9179 0U, // DSBnXS
9180 0U, // DUPM_ZI
9181 0U, // DUP_ZI_B
9182 0U, // DUP_ZI_D
9183 0U, // DUP_ZI_H
9184 0U, // DUP_ZI_S
9185 6U, // DUP_ZR_B
9186 6U, // DUP_ZR_D
9187 0U, // DUP_ZR_H
9188 6U, // DUP_ZR_S
9189 42U, // DUP_ZZI_B
9190 42U, // DUP_ZZI_D
9191 0U, // DUP_ZZI_H
9192 0U, // DUP_ZZI_Q
9193 42U, // DUP_ZZI_S
9194 6U, // DUPv16i8gpr
9195 42U, // DUPv16i8lane
9196 6U, // DUPv2i32gpr
9197 42U, // DUPv2i32lane
9198 6U, // DUPv2i64gpr
9199 42U, // DUPv2i64lane
9200 6U, // DUPv4i16gpr
9201 42U, // DUPv4i16lane
9202 6U, // DUPv4i32gpr
9203 42U, // DUPv4i32lane
9204 6U, // DUPv8i16gpr
9205 42U, // DUPv8i16lane
9206 6U, // DUPv8i8gpr
9207 42U, // DUPv8i8lane
9208 3592U, // EONWrs
9209 3592U, // EONXrs
9210 5277704U, // EOR3
9211 2131464U, // EOR3_ZZZZ
9212 0U, // EORBT_ZZZ_B
9213 264U, // EORBT_ZZZ_D
9214 28U, // EORBT_ZZZ_H
9215 520U, // EORBT_ZZZ_S
9216 1083922U, // EORS_PPzPP
9217 0U, // EORTB_ZZZ_B
9218 264U, // EORTB_ZZZ_D
9219 28U, // EORTB_ZZZ_H
9220 520U, // EORTB_ZZZ_S
9221 0U, // EORV_VPZ_B
9222 0U, // EORV_VPZ_D
9223 0U, // EORV_VPZ_H
9224 0U, // EORV_VPZ_S
9225 8968U, // EORWri
9226 3592U, // EORWrs
9227 9224U, // EORXri
9228 3592U, // EORXrs
9229 1083922U, // EOR_PPzPP
9230 9224U, // EOR_ZI
9231 1083916U, // EOR_ZPmZ_B
9232 2131468U, // EOR_ZPmZ_D
9233 3214094U, // EOR_ZPmZ_H
9234 4230156U, // EOR_ZPmZ_S
9235 1544U, // EOR_ZZZ
9236 2056U, // EORv16i8
9237 2056U, // EORv8i8
9238 0U, // ERET
9239 0U, // ERETAA
9240 0U, // ERETAB
9241 33544U, // EXTRWrri
9242 33544U, // EXTRXrri
9243 13666824U, // EXT_ZZI
9244 45U, // EXT_ZZI_B
9245 34824U, // EXTv16i8
9246 34824U, // EXTv8i8
9247 776U, // FABD16
9248 776U, // FABD32
9249 776U, // FABD64
9250 2131468U, // FABD_ZPmZ_D
9251 3214094U, // FABD_ZPmZ_H
9252 4230156U, // FABD_ZPmZ_S
9253 2056U, // FABDv2f32
9254 2056U, // FABDv2f64
9255 2056U, // FABDv4f16
9256 2056U, // FABDv4f32
9257 2056U, // FABDv8f16
9258 6U, // FABSDr
9259 6U, // FABSHr
9260 6U, // FABSSr
9261 2U, // FABS_ZPmZ_D
9262 0U, // FABS_ZPmZ_H
9263 4U, // FABS_ZPmZ_S
9264 6U, // FABSv2f32
9265 6U, // FABSv2f64
9266 6U, // FABSv4f16
9267 6U, // FABSv4f32
9268 6U, // FABSv8f16
9269 776U, // FACGE16
9270 776U, // FACGE32
9271 776U, // FACGE64
9272 2131474U, // FACGE_PPzZZ_D
9273 3214094U, // FACGE_PPzZZ_H
9274 4230162U, // FACGE_PPzZZ_S
9275 2056U, // FACGEv2f32
9276 2056U, // FACGEv2f64
9277 2056U, // FACGEv4f16
9278 2056U, // FACGEv4f32
9279 2056U, // FACGEv8f16
9280 776U, // FACGT16
9281 776U, // FACGT32
9282 776U, // FACGT64
9283 2131474U, // FACGT_PPzZZ_D
9284 3214094U, // FACGT_PPzZZ_H
9285 4230162U, // FACGT_PPzZZ_S
9286 2056U, // FACGTv2f32
9287 2056U, // FACGTv2f64
9288 2056U, // FACGTv4f16
9289 2056U, // FACGTv4f32
9290 2056U, // FACGTv8f16
9291 0U, // FADDA_VPZ_D
9292 0U, // FADDA_VPZ_H
9293 0U, // FADDA_VPZ_S
9294 776U, // FADDDrr
9295 776U, // FADDHrr
9296 2131468U, // FADDP_ZPmZZ_D
9297 3214094U, // FADDP_ZPmZZ_H
9298 4230156U, // FADDP_ZPmZZ_S
9299 2056U, // FADDPv2f32
9300 2056U, // FADDPv2f64
9301 6U, // FADDPv2i16p
9302 6U, // FADDPv2i32p
9303 6U, // FADDPv2i64p
9304 2056U, // FADDPv4f16
9305 2056U, // FADDPv4f32
9306 2056U, // FADDPv8f16
9307 776U, // FADDSrr
9308 0U, // FADDV_VPZ_D
9309 0U, // FADDV_VPZ_H
9310 0U, // FADDV_VPZ_S
9311 14714380U, // FADD_ZPmI_D
9312 363278U, // FADD_ZPmI_H
9313 14715916U, // FADD_ZPmI_S
9314 2131468U, // FADD_ZPmZ_D
9315 3214094U, // FADD_ZPmZ_H
9316 4230156U, // FADD_ZPmZ_S
9317 1544U, // FADD_ZZZ_D
9318 14U, // FADD_ZZZ_H
9319 3080U, // FADD_ZZZ_S
9320 2056U, // FADDv2f32
9321 2056U, // FADDv2f64
9322 2056U, // FADDv4f16
9323 2056U, // FADDv4f32
9324 2056U, // FADDv8f16
9325 136349196U, // FCADD_ZPmZ_D
9326 210832142U, // FCADD_ZPmZ_H
9327 138447884U, // FCADD_ZPmZ_S
9328 7374856U, // FCADDv2f32
9329 7374856U, // FCADDv2f64
9330 7374856U, // FCADDv4f16
9331 7374856U, // FCADDv4f32
9332 7374856U, // FCADDv8f16
9333 8422152U, // FCCMPDrr
9334 8422152U, // FCCMPEDrr
9335 8422152U, // FCCMPEHrr
9336 8422152U, // FCCMPESrr
9337 8422152U, // FCCMPHrr
9338 8422152U, // FCCMPSrr
9339 776U, // FCMEQ16
9340 776U, // FCMEQ32
9341 776U, // FCMEQ64
9342 394770U, // FCMEQ_PPzZ0_D
9343 10766U, // FCMEQ_PPzZ0_H
9344 396306U, // FCMEQ_PPzZ0_S
9345 2131474U, // FCMEQ_PPzZZ_D
9346 3214094U, // FCMEQ_PPzZZ_H
9347 4230162U, // FCMEQ_PPzZZ_S
9348 46U, // FCMEQv1i16rz
9349 46U, // FCMEQv1i32rz
9350 46U, // FCMEQv1i64rz
9351 2056U, // FCMEQv2f32
9352 2056U, // FCMEQv2f64
9353 46U, // FCMEQv2i32rz
9354 46U, // FCMEQv2i64rz
9355 2056U, // FCMEQv4f16
9356 2056U, // FCMEQv4f32
9357 46U, // FCMEQv4i16rz
9358 46U, // FCMEQv4i32rz
9359 2056U, // FCMEQv8f16
9360 46U, // FCMEQv8i16rz
9361 776U, // FCMGE16
9362 776U, // FCMGE32
9363 776U, // FCMGE64
9364 394770U, // FCMGE_PPzZ0_D
9365 10766U, // FCMGE_PPzZ0_H
9366 396306U, // FCMGE_PPzZ0_S
9367 2131474U, // FCMGE_PPzZZ_D
9368 3214094U, // FCMGE_PPzZZ_H
9369 4230162U, // FCMGE_PPzZZ_S
9370 46U, // FCMGEv1i16rz
9371 46U, // FCMGEv1i32rz
9372 46U, // FCMGEv1i64rz
9373 2056U, // FCMGEv2f32
9374 2056U, // FCMGEv2f64
9375 46U, // FCMGEv2i32rz
9376 46U, // FCMGEv2i64rz
9377 2056U, // FCMGEv4f16
9378 2056U, // FCMGEv4f32
9379 46U, // FCMGEv4i16rz
9380 46U, // FCMGEv4i32rz
9381 2056U, // FCMGEv8f16
9382 46U, // FCMGEv8i16rz
9383 776U, // FCMGT16
9384 776U, // FCMGT32
9385 776U, // FCMGT64
9386 394770U, // FCMGT_PPzZ0_D
9387 10766U, // FCMGT_PPzZ0_H
9388 396306U, // FCMGT_PPzZ0_S
9389 2131474U, // FCMGT_PPzZZ_D
9390 3214094U, // FCMGT_PPzZZ_H
9391 4230162U, // FCMGT_PPzZZ_S
9392 46U, // FCMGTv1i16rz
9393 46U, // FCMGTv1i32rz
9394 46U, // FCMGTv1i64rz
9395 2056U, // FCMGTv2f32
9396 2056U, // FCMGTv2f64
9397 46U, // FCMGTv2i32rz
9398 46U, // FCMGTv2i64rz
9399 2056U, // FCMGTv4f16
9400 2056U, // FCMGTv4f32
9401 46U, // FCMGTv4i16rz
9402 46U, // FCMGTv4i32rz
9403 2056U, // FCMGTv8f16
9404 46U, // FCMGTv8i16rz
9405 686850316U, // FCMLA_ZPmZZ_D
9406 76974876U, // FCMLA_ZPmZZ_H
9407 687899148U, // FCMLA_ZPmZZ_S
9408 10528284U, // FCMLA_ZZZI_H
9409 76743176U, // FCMLA_ZZZI_S
9410 11569416U, // FCMLAv2f32
9411 11569416U, // FCMLAv2f64
9412 11569416U, // FCMLAv4f16
9413 76744968U, // FCMLAv4f16_indexed
9414 11569416U, // FCMLAv4f32
9415 76744968U, // FCMLAv4f32_indexed
9416 11569416U, // FCMLAv8f16
9417 76744968U, // FCMLAv8f16_indexed
9418 394770U, // FCMLE_PPzZ0_D
9419 10766U, // FCMLE_PPzZ0_H
9420 396306U, // FCMLE_PPzZ0_S
9421 46U, // FCMLEv1i16rz
9422 46U, // FCMLEv1i32rz
9423 46U, // FCMLEv1i64rz
9424 46U, // FCMLEv2i32rz
9425 46U, // FCMLEv2i64rz
9426 46U, // FCMLEv4i16rz
9427 46U, // FCMLEv4i32rz
9428 46U, // FCMLEv8i16rz
9429 394770U, // FCMLT_PPzZ0_D
9430 10766U, // FCMLT_PPzZ0_H
9431 396306U, // FCMLT_PPzZ0_S
9432 46U, // FCMLTv1i16rz
9433 46U, // FCMLTv1i32rz
9434 46U, // FCMLTv1i64rz
9435 46U, // FCMLTv2i32rz
9436 46U, // FCMLTv2i64rz
9437 46U, // FCMLTv4i16rz
9438 46U, // FCMLTv4i32rz
9439 46U, // FCMLTv8i16rz
9440 394770U, // FCMNE_PPzZ0_D
9441 10766U, // FCMNE_PPzZ0_H
9442 396306U, // FCMNE_PPzZ0_S
9443 2131474U, // FCMNE_PPzZZ_D
9444 3214094U, // FCMNE_PPzZZ_H
9445 4230162U, // FCMNE_PPzZZ_S
9446 0U, // FCMPDri
9447 6U, // FCMPDrr
9448 0U, // FCMPEDri
9449 6U, // FCMPEDrr
9450 0U, // FCMPEHri
9451 6U, // FCMPEHrr
9452 0U, // FCMPESri
9453 6U, // FCMPESrr
9454 0U, // FCMPHri
9455 6U, // FCMPHrr
9456 0U, // FCMPSri
9457 6U, // FCMPSrr
9458 2131474U, // FCMUO_PPzZZ_D
9459 3214094U, // FCMUO_PPzZZ_H
9460 4230162U, // FCMUO_PPzZZ_S
9461 48U, // FCPY_ZPmI_D
9462 1U, // FCPY_ZPmI_H
9463 48U, // FCPY_ZPmI_S
9464 8422152U, // FCSELDrrr
9465 8422152U, // FCSELHrrr
9466 8422152U, // FCSELSrrr
9467 6U, // FCVTASUWDr
9468 6U, // FCVTASUWHr
9469 6U, // FCVTASUWSr
9470 6U, // FCVTASUXDr
9471 6U, // FCVTASUXHr
9472 6U, // FCVTASUXSr
9473 6U, // FCVTASv1f16
9474 6U, // FCVTASv1i32
9475 6U, // FCVTASv1i64
9476 6U, // FCVTASv2f32
9477 6U, // FCVTASv2f64
9478 6U, // FCVTASv4f16
9479 6U, // FCVTASv4f32
9480 6U, // FCVTASv8f16
9481 6U, // FCVTAUUWDr
9482 6U, // FCVTAUUWHr
9483 6U, // FCVTAUUWSr
9484 6U, // FCVTAUUXDr
9485 6U, // FCVTAUUXHr
9486 6U, // FCVTAUUXSr
9487 6U, // FCVTAUv1f16
9488 6U, // FCVTAUv1i32
9489 6U, // FCVTAUv1i64
9490 6U, // FCVTAUv2f32
9491 6U, // FCVTAUv2f64
9492 6U, // FCVTAUv4f16
9493 6U, // FCVTAUv4f32
9494 6U, // FCVTAUv8f16
9495 6U, // FCVTDHr
9496 6U, // FCVTDSr
9497 6U, // FCVTHDr
9498 6U, // FCVTHSr
9499 28U, // FCVTLT_ZPmZ_HtoS
9500 4U, // FCVTLT_ZPmZ_StoD
9501 1U, // FCVTLv2i32
9502 50U, // FCVTLv4i16
9503 1U, // FCVTLv4i32
9504 52U, // FCVTLv8i16
9505 6U, // FCVTMSUWDr
9506 6U, // FCVTMSUWHr
9507 6U, // FCVTMSUWSr
9508 6U, // FCVTMSUXDr
9509 6U, // FCVTMSUXHr
9510 6U, // FCVTMSUXSr
9511 6U, // FCVTMSv1f16
9512 6U, // FCVTMSv1i32
9513 6U, // FCVTMSv1i64
9514 6U, // FCVTMSv2f32
9515 6U, // FCVTMSv2f64
9516 6U, // FCVTMSv4f16
9517 6U, // FCVTMSv4f32
9518 6U, // FCVTMSv8f16
9519 6U, // FCVTMUUWDr
9520 6U, // FCVTMUUWHr
9521 6U, // FCVTMUUWSr
9522 6U, // FCVTMUUXDr
9523 6U, // FCVTMUUXHr
9524 6U, // FCVTMUUXSr
9525 6U, // FCVTMUv1f16
9526 6U, // FCVTMUv1i32
9527 6U, // FCVTMUv1i64
9528 6U, // FCVTMUv2f32
9529 6U, // FCVTMUv2f64
9530 6U, // FCVTMUv4f16
9531 6U, // FCVTMUv4f32
9532 6U, // FCVTMUv8f16
9533 6U, // FCVTNSUWDr
9534 6U, // FCVTNSUWHr
9535 6U, // FCVTNSUWSr
9536 6U, // FCVTNSUXDr
9537 6U, // FCVTNSUXHr
9538 6U, // FCVTNSUXSr
9539 6U, // FCVTNSv1f16
9540 6U, // FCVTNSv1i32
9541 6U, // FCVTNSv1i64
9542 6U, // FCVTNSv2f32
9543 6U, // FCVTNSv2f64
9544 6U, // FCVTNSv4f16
9545 6U, // FCVTNSv4f32
9546 6U, // FCVTNSv8f16
9547 2U, // FCVTNT_ZPmZ_DtoS
9548 0U, // FCVTNT_ZPmZ_StoH
9549 6U, // FCVTNUUWDr
9550 6U, // FCVTNUUWHr
9551 6U, // FCVTNUUWSr
9552 6U, // FCVTNUUXDr
9553 6U, // FCVTNUUXHr
9554 6U, // FCVTNUUXSr
9555 6U, // FCVTNUv1f16
9556 6U, // FCVTNUv1i32
9557 6U, // FCVTNUv1i64
9558 6U, // FCVTNUv2f32
9559 6U, // FCVTNUv2f64
9560 6U, // FCVTNUv4f16
9561 6U, // FCVTNUv4f32
9562 6U, // FCVTNUv8f16
9563 0U, // FCVTNv2i32
9564 0U, // FCVTNv4i16
9565 54U, // FCVTNv4i32
9566 0U, // FCVTNv8i16
9567 6U, // FCVTPSUWDr
9568 6U, // FCVTPSUWHr
9569 6U, // FCVTPSUWSr
9570 6U, // FCVTPSUXDr
9571 6U, // FCVTPSUXHr
9572 6U, // FCVTPSUXSr
9573 6U, // FCVTPSv1f16
9574 6U, // FCVTPSv1i32
9575 6U, // FCVTPSv1i64
9576 6U, // FCVTPSv2f32
9577 6U, // FCVTPSv2f64
9578 6U, // FCVTPSv4f16
9579 6U, // FCVTPSv4f32
9580 6U, // FCVTPSv8f16
9581 6U, // FCVTPUUWDr
9582 6U, // FCVTPUUWHr
9583 6U, // FCVTPUUWSr
9584 6U, // FCVTPUUXDr
9585 6U, // FCVTPUUXHr
9586 6U, // FCVTPUUXSr
9587 6U, // FCVTPUv1f16
9588 6U, // FCVTPUv1i32
9589 6U, // FCVTPUv1i64
9590 6U, // FCVTPUv2f32
9591 6U, // FCVTPUv2f64
9592 6U, // FCVTPUv4f16
9593 6U, // FCVTPUv4f32
9594 6U, // FCVTPUv8f16
9595 6U, // FCVTSDr
9596 6U, // FCVTSHr
9597 2U, // FCVTXNT_ZPmZ_DtoS
9598 6U, // FCVTXNv1i64
9599 0U, // FCVTXNv2f32
9600 54U, // FCVTXNv4f32
9601 2U, // FCVTX_ZPmZ_DtoS
9602 776U, // FCVTZSSWDri
9603 776U, // FCVTZSSWHri
9604 776U, // FCVTZSSWSri
9605 776U, // FCVTZSSXDri
9606 776U, // FCVTZSSXHri
9607 776U, // FCVTZSSXSri
9608 6U, // FCVTZSUWDr
9609 6U, // FCVTZSUWHr
9610 6U, // FCVTZSUWSr
9611 6U, // FCVTZSUXDr
9612 6U, // FCVTZSUXHr
9613 6U, // FCVTZSUXSr
9614 2U, // FCVTZS_ZPmZ_DtoD
9615 2U, // FCVTZS_ZPmZ_DtoS
9616 28U, // FCVTZS_ZPmZ_HtoD
9617 0U, // FCVTZS_ZPmZ_HtoH
9618 28U, // FCVTZS_ZPmZ_HtoS
9619 4U, // FCVTZS_ZPmZ_StoD
9620 4U, // FCVTZS_ZPmZ_StoS
9621 776U, // FCVTZSd
9622 776U, // FCVTZSh
9623 776U, // FCVTZSs
9624 6U, // FCVTZSv1f16
9625 6U, // FCVTZSv1i32
9626 6U, // FCVTZSv1i64
9627 6U, // FCVTZSv2f32
9628 6U, // FCVTZSv2f64
9629 776U, // FCVTZSv2i32_shift
9630 776U, // FCVTZSv2i64_shift
9631 6U, // FCVTZSv4f16
9632 6U, // FCVTZSv4f32
9633 776U, // FCVTZSv4i16_shift
9634 776U, // FCVTZSv4i32_shift
9635 6U, // FCVTZSv8f16
9636 776U, // FCVTZSv8i16_shift
9637 776U, // FCVTZUSWDri
9638 776U, // FCVTZUSWHri
9639 776U, // FCVTZUSWSri
9640 776U, // FCVTZUSXDri
9641 776U, // FCVTZUSXHri
9642 776U, // FCVTZUSXSri
9643 6U, // FCVTZUUWDr
9644 6U, // FCVTZUUWHr
9645 6U, // FCVTZUUWSr
9646 6U, // FCVTZUUXDr
9647 6U, // FCVTZUUXHr
9648 6U, // FCVTZUUXSr
9649 2U, // FCVTZU_ZPmZ_DtoD
9650 2U, // FCVTZU_ZPmZ_DtoS
9651 28U, // FCVTZU_ZPmZ_HtoD
9652 0U, // FCVTZU_ZPmZ_HtoH
9653 28U, // FCVTZU_ZPmZ_HtoS
9654 4U, // FCVTZU_ZPmZ_StoD
9655 4U, // FCVTZU_ZPmZ_StoS
9656 776U, // FCVTZUd
9657 776U, // FCVTZUh
9658 776U, // FCVTZUs
9659 6U, // FCVTZUv1f16
9660 6U, // FCVTZUv1i32
9661 6U, // FCVTZUv1i64
9662 6U, // FCVTZUv2f32
9663 6U, // FCVTZUv2f64
9664 776U, // FCVTZUv2i32_shift
9665 776U, // FCVTZUv2i64_shift
9666 6U, // FCVTZUv4f16
9667 6U, // FCVTZUv4f32
9668 776U, // FCVTZUv4i16_shift
9669 776U, // FCVTZUv4i32_shift
9670 6U, // FCVTZUv8f16
9671 776U, // FCVTZUv8i16_shift
9672 1U, // FCVT_ZPmZ_DtoH
9673 2U, // FCVT_ZPmZ_DtoS
9674 28U, // FCVT_ZPmZ_HtoD
9675 28U, // FCVT_ZPmZ_HtoS
9676 4U, // FCVT_ZPmZ_StoD
9677 0U, // FCVT_ZPmZ_StoH
9678 776U, // FDIVDrr
9679 776U, // FDIVHrr
9680 2131468U, // FDIVR_ZPmZ_D
9681 3214094U, // FDIVR_ZPmZ_H
9682 4230156U, // FDIVR_ZPmZ_S
9683 776U, // FDIVSrr
9684 2131468U, // FDIV_ZPmZ_D
9685 3214094U, // FDIV_ZPmZ_H
9686 4230156U, // FDIV_ZPmZ_S
9687 2056U, // FDIVv2f32
9688 2056U, // FDIVv2f64
9689 2056U, // FDIVv4f16
9690 2056U, // FDIVv4f32
9691 2056U, // FDIVv8f16
9692 1U, // FDUP_ZI_D
9693 0U, // FDUP_ZI_H
9694 1U, // FDUP_ZI_S
9695 6U, // FEXPA_ZZ_D
9696 0U, // FEXPA_ZZ_H
9697 6U, // FEXPA_ZZ_S
9698 6U, // FJCVTZS
9699 2U, // FLOGB_ZPmZ_D
9700 0U, // FLOGB_ZPmZ_H
9701 4U, // FLOGB_ZPmZ_S
9702 33544U, // FMADDDrrr
9703 33544U, // FMADDHrrr
9704 33544U, // FMADDSrrr
9705 15761676U, // FMAD_ZPmZZ_D
9706 3574556U, // FMAD_ZPmZZ_H
9707 16810508U, // FMAD_ZPmZZ_S
9708 776U, // FMAXDrr
9709 776U, // FMAXHrr
9710 776U, // FMAXNMDrr
9711 776U, // FMAXNMHrr
9712 2131468U, // FMAXNMP_ZPmZZ_D
9713 3214094U, // FMAXNMP_ZPmZZ_H
9714 4230156U, // FMAXNMP_ZPmZZ_S
9715 2056U, // FMAXNMPv2f32
9716 2056U, // FMAXNMPv2f64
9717 6U, // FMAXNMPv2i16p
9718 6U, // FMAXNMPv2i32p
9719 6U, // FMAXNMPv2i64p
9720 2056U, // FMAXNMPv4f16
9721 2056U, // FMAXNMPv4f32
9722 2056U, // FMAXNMPv8f16
9723 776U, // FMAXNMSrr
9724 0U, // FMAXNMV_VPZ_D
9725 0U, // FMAXNMV_VPZ_H
9726 0U, // FMAXNMV_VPZ_S
9727 6U, // FMAXNMVv4i16v
9728 6U, // FMAXNMVv4i32v
9729 6U, // FMAXNMVv8i16v
9730 17860108U, // FMAXNM_ZPmI_D
9731 461582U, // FMAXNM_ZPmI_H
9732 17861644U, // FMAXNM_ZPmI_S
9733 2131468U, // FMAXNM_ZPmZ_D
9734 3214094U, // FMAXNM_ZPmZ_H
9735 4230156U, // FMAXNM_ZPmZ_S
9736 2056U, // FMAXNMv2f32
9737 2056U, // FMAXNMv2f64
9738 2056U, // FMAXNMv4f16
9739 2056U, // FMAXNMv4f32
9740 2056U, // FMAXNMv8f16
9741 2131468U, // FMAXP_ZPmZZ_D
9742 3214094U, // FMAXP_ZPmZZ_H
9743 4230156U, // FMAXP_ZPmZZ_S
9744 2056U, // FMAXPv2f32
9745 2056U, // FMAXPv2f64
9746 6U, // FMAXPv2i16p
9747 6U, // FMAXPv2i32p
9748 6U, // FMAXPv2i64p
9749 2056U, // FMAXPv4f16
9750 2056U, // FMAXPv4f32
9751 2056U, // FMAXPv8f16
9752 776U, // FMAXSrr
9753 0U, // FMAXV_VPZ_D
9754 0U, // FMAXV_VPZ_H
9755 0U, // FMAXV_VPZ_S
9756 6U, // FMAXVv4i16v
9757 6U, // FMAXVv4i32v
9758 6U, // FMAXVv8i16v
9759 17860108U, // FMAX_ZPmI_D
9760 461582U, // FMAX_ZPmI_H
9761 17861644U, // FMAX_ZPmI_S
9762 2131468U, // FMAX_ZPmZ_D
9763 3214094U, // FMAX_ZPmZ_H
9764 4230156U, // FMAX_ZPmZ_S
9765 2056U, // FMAXv2f32
9766 2056U, // FMAXv2f64
9767 2056U, // FMAXv4f16
9768 2056U, // FMAXv4f32
9769 2056U, // FMAXv8f16
9770 776U, // FMINDrr
9771 776U, // FMINHrr
9772 776U, // FMINNMDrr
9773 776U, // FMINNMHrr
9774 2131468U, // FMINNMP_ZPmZZ_D
9775 3214094U, // FMINNMP_ZPmZZ_H
9776 4230156U, // FMINNMP_ZPmZZ_S
9777 2056U, // FMINNMPv2f32
9778 2056U, // FMINNMPv2f64
9779 6U, // FMINNMPv2i16p
9780 6U, // FMINNMPv2i32p
9781 6U, // FMINNMPv2i64p
9782 2056U, // FMINNMPv4f16
9783 2056U, // FMINNMPv4f32
9784 2056U, // FMINNMPv8f16
9785 776U, // FMINNMSrr
9786 0U, // FMINNMV_VPZ_D
9787 0U, // FMINNMV_VPZ_H
9788 0U, // FMINNMV_VPZ_S
9789 6U, // FMINNMVv4i16v
9790 6U, // FMINNMVv4i32v
9791 6U, // FMINNMVv8i16v
9792 17860108U, // FMINNM_ZPmI_D
9793 461582U, // FMINNM_ZPmI_H
9794 17861644U, // FMINNM_ZPmI_S
9795 2131468U, // FMINNM_ZPmZ_D
9796 3214094U, // FMINNM_ZPmZ_H
9797 4230156U, // FMINNM_ZPmZ_S
9798 2056U, // FMINNMv2f32
9799 2056U, // FMINNMv2f64
9800 2056U, // FMINNMv4f16
9801 2056U, // FMINNMv4f32
9802 2056U, // FMINNMv8f16
9803 2131468U, // FMINP_ZPmZZ_D
9804 3214094U, // FMINP_ZPmZZ_H
9805 4230156U, // FMINP_ZPmZZ_S
9806 2056U, // FMINPv2f32
9807 2056U, // FMINPv2f64
9808 6U, // FMINPv2i16p
9809 6U, // FMINPv2i32p
9810 6U, // FMINPv2i64p
9811 2056U, // FMINPv4f16
9812 2056U, // FMINPv4f32
9813 2056U, // FMINPv8f16
9814 776U, // FMINSrr
9815 0U, // FMINV_VPZ_D
9816 0U, // FMINV_VPZ_H
9817 0U, // FMINV_VPZ_S
9818 6U, // FMINVv4i16v
9819 6U, // FMINVv4i32v
9820 6U, // FMINVv8i16v
9821 17860108U, // FMIN_ZPmI_D
9822 461582U, // FMIN_ZPmI_H
9823 17861644U, // FMIN_ZPmI_S
9824 2131468U, // FMIN_ZPmZ_D
9825 3214094U, // FMIN_ZPmZ_H
9826 4230156U, // FMIN_ZPmZ_S
9827 2056U, // FMINv2f32
9828 2056U, // FMINv2f64
9829 2056U, // FMINv4f16
9830 2056U, // FMINv4f32
9831 2056U, // FMINv8f16
9832 3344648U, // FMLAL2lanev4f16
9833 3344648U, // FMLAL2lanev8f16
9834 0U, // FMLAL2v4f16
9835 0U, // FMLAL2v8f16
9836 3344136U, // FMLALB_ZZZI_SHH
9837 1800U, // FMLALB_ZZZ_SHH
9838 3344136U, // FMLALT_ZZZI_SHH
9839 1800U, // FMLALT_ZZZ_SHH
9840 3344648U, // FMLALlanev4f16
9841 3344648U, // FMLALlanev8f16
9842 0U, // FMLALv4f16
9843 0U, // FMLALv8f16
9844 15761676U, // FMLA_ZPmZZ_D
9845 3574556U, // FMLA_ZPmZZ_H
9846 16810508U, // FMLA_ZPmZZ_S
9847 3342600U, // FMLA_ZZZI_D
9848 9756U, // FMLA_ZZZI_H
9849 3342856U, // FMLA_ZZZI_S
9850 3344648U, // FMLAv1i16_indexed
9851 3344648U, // FMLAv1i32_indexed
9852 3344648U, // FMLAv1i64_indexed
9853 2312U, // FMLAv2f32
9854 2312U, // FMLAv2f64
9855 3344648U, // FMLAv2i32_indexed
9856 3344648U, // FMLAv2i64_indexed
9857 2312U, // FMLAv4f16
9858 2312U, // FMLAv4f32
9859 3344648U, // FMLAv4i16_indexed
9860 3344648U, // FMLAv4i32_indexed
9861 2312U, // FMLAv8f16
9862 3344648U, // FMLAv8i16_indexed
9863 3344648U, // FMLSL2lanev4f16
9864 3344648U, // FMLSL2lanev8f16
9865 0U, // FMLSL2v4f16
9866 0U, // FMLSL2v8f16
9867 3344136U, // FMLSLB_ZZZI_SHH
9868 1800U, // FMLSLB_ZZZ_SHH
9869 3344136U, // FMLSLT_ZZZI_SHH
9870 1800U, // FMLSLT_ZZZ_SHH
9871 3344648U, // FMLSLlanev4f16
9872 3344648U, // FMLSLlanev8f16
9873 0U, // FMLSLv4f16
9874 0U, // FMLSLv8f16
9875 15761676U, // FMLS_ZPmZZ_D
9876 3574556U, // FMLS_ZPmZZ_H
9877 16810508U, // FMLS_ZPmZZ_S
9878 3342600U, // FMLS_ZZZI_D
9879 9756U, // FMLS_ZZZI_H
9880 3342856U, // FMLS_ZZZI_S
9881 3344648U, // FMLSv1i16_indexed
9882 3344648U, // FMLSv1i32_indexed
9883 3344648U, // FMLSv1i64_indexed
9884 2312U, // FMLSv2f32
9885 2312U, // FMLSv2f64
9886 3344648U, // FMLSv2i32_indexed
9887 3344648U, // FMLSv2i64_indexed
9888 2312U, // FMLSv4f16
9889 2312U, // FMLSv4f32
9890 3344648U, // FMLSv4i16_indexed
9891 3344648U, // FMLSv4i32_indexed
9892 2312U, // FMLSv8f16
9893 3344648U, // FMLSv8i16_indexed
9894 264U, // FMMLA_ZZZ_D
9895 520U, // FMMLA_ZZZ_S
9896 42U, // FMOVDXHighr
9897 6U, // FMOVDXr
9898 1U, // FMOVDi
9899 6U, // FMOVDr
9900 6U, // FMOVHWr
9901 6U, // FMOVHXr
9902 1U, // FMOVHi
9903 6U, // FMOVHr
9904 6U, // FMOVSWr
9905 1U, // FMOVSi
9906 6U, // FMOVSr
9907 6U, // FMOVWHr
9908 6U, // FMOVWSr
9909 6U, // FMOVXDHighr
9910 6U, // FMOVXDr
9911 6U, // FMOVXHr
9912 1U, // FMOVv2f32_ns
9913 1U, // FMOVv2f64_ns
9914 1U, // FMOVv4f16_ns
9915 1U, // FMOVv4f32_ns
9916 1U, // FMOVv8f16_ns
9917 15761676U, // FMSB_ZPmZZ_D
9918 3574556U, // FMSB_ZPmZZ_H
9919 16810508U, // FMSB_ZPmZZ_S
9920 33544U, // FMSUBDrrr
9921 33544U, // FMSUBHrrr
9922 33544U, // FMSUBSrrr
9923 776U, // FMULDrr
9924 776U, // FMULHrr
9925 776U, // FMULSrr
9926 776U, // FMULX16
9927 776U, // FMULX32
9928 776U, // FMULX64
9929 2131468U, // FMULX_ZPmZ_D
9930 3214094U, // FMULX_ZPmZ_H
9931 4230156U, // FMULX_ZPmZ_S
9932 493576U, // FMULXv1i16_indexed
9933 493576U, // FMULXv1i32_indexed
9934 493576U, // FMULXv1i64_indexed
9935 2056U, // FMULXv2f32
9936 2056U, // FMULXv2f64
9937 493576U, // FMULXv2i32_indexed
9938 493576U, // FMULXv2i64_indexed
9939 2056U, // FMULXv4f16
9940 2056U, // FMULXv4f32
9941 493576U, // FMULXv4i16_indexed
9942 493576U, // FMULXv4i32_indexed
9943 2056U, // FMULXv8f16
9944 493576U, // FMULXv8i16_indexed
9945 18908684U, // FMUL_ZPmI_D
9946 527118U, // FMUL_ZPmI_H
9947 18910220U, // FMUL_ZPmI_S
9948 2131468U, // FMUL_ZPmZ_D
9949 3214094U, // FMUL_ZPmZ_H
9950 4230156U, // FMUL_ZPmZ_S
9951 493064U, // FMUL_ZZZI_D
9952 11022U, // FMUL_ZZZI_H
9953 494600U, // FMUL_ZZZI_S
9954 1544U, // FMUL_ZZZ_D
9955 14U, // FMUL_ZZZ_H
9956 3080U, // FMUL_ZZZ_S
9957 493576U, // FMULv1i16_indexed
9958 493576U, // FMULv1i32_indexed
9959 493576U, // FMULv1i64_indexed
9960 2056U, // FMULv2f32
9961 2056U, // FMULv2f64
9962 493576U, // FMULv2i32_indexed
9963 493576U, // FMULv2i64_indexed
9964 2056U, // FMULv4f16
9965 2056U, // FMULv4f32
9966 493576U, // FMULv4i16_indexed
9967 493576U, // FMULv4i32_indexed
9968 2056U, // FMULv8f16
9969 493576U, // FMULv8i16_indexed
9970 6U, // FNEGDr
9971 6U, // FNEGHr
9972 6U, // FNEGSr
9973 2U, // FNEG_ZPmZ_D
9974 0U, // FNEG_ZPmZ_H
9975 4U, // FNEG_ZPmZ_S
9976 6U, // FNEGv2f32
9977 6U, // FNEGv2f64
9978 6U, // FNEGv4f16
9979 6U, // FNEGv4f32
9980 6U, // FNEGv8f16
9981 33544U, // FNMADDDrrr
9982 33544U, // FNMADDHrrr
9983 33544U, // FNMADDSrrr
9984 15761676U, // FNMAD_ZPmZZ_D
9985 3574556U, // FNMAD_ZPmZZ_H
9986 16810508U, // FNMAD_ZPmZZ_S
9987 15761676U, // FNMLA_ZPmZZ_D
9988 3574556U, // FNMLA_ZPmZZ_H
9989 16810508U, // FNMLA_ZPmZZ_S
9990 15761676U, // FNMLS_ZPmZZ_D
9991 3574556U, // FNMLS_ZPmZZ_H
9992 16810508U, // FNMLS_ZPmZZ_S
9993 15761676U, // FNMSB_ZPmZZ_D
9994 3574556U, // FNMSB_ZPmZZ_H
9995 16810508U, // FNMSB_ZPmZZ_S
9996 33544U, // FNMSUBDrrr
9997 33544U, // FNMSUBHrrr
9998 33544U, // FNMSUBSrrr
9999 776U, // FNMULDrr
10000 776U, // FNMULHrr
10001 776U, // FNMULSrr
10002 6U, // FRECPE_ZZ_D
10003 0U, // FRECPE_ZZ_H
10004 6U, // FRECPE_ZZ_S
10005 6U, // FRECPEv1f16
10006 6U, // FRECPEv1i32
10007 6U, // FRECPEv1i64
10008 6U, // FRECPEv2f32
10009 6U, // FRECPEv2f64
10010 6U, // FRECPEv4f16
10011 6U, // FRECPEv4f32
10012 6U, // FRECPEv8f16
10013 776U, // FRECPS16
10014 776U, // FRECPS32
10015 776U, // FRECPS64
10016 1544U, // FRECPS_ZZZ_D
10017 14U, // FRECPS_ZZZ_H
10018 3080U, // FRECPS_ZZZ_S
10019 2056U, // FRECPSv2f32
10020 2056U, // FRECPSv2f64
10021 2056U, // FRECPSv4f16
10022 2056U, // FRECPSv4f32
10023 2056U, // FRECPSv8f16
10024 2U, // FRECPX_ZPmZ_D
10025 0U, // FRECPX_ZPmZ_H
10026 4U, // FRECPX_ZPmZ_S
10027 6U, // FRECPXv1f16
10028 6U, // FRECPXv1i32
10029 6U, // FRECPXv1i64
10030 6U, // FRINT32XDr
10031 6U, // FRINT32XSr
10032 6U, // FRINT32Xv2f32
10033 6U, // FRINT32Xv2f64
10034 6U, // FRINT32Xv4f32
10035 6U, // FRINT32ZDr
10036 6U, // FRINT32ZSr
10037 6U, // FRINT32Zv2f32
10038 6U, // FRINT32Zv2f64
10039 6U, // FRINT32Zv4f32
10040 6U, // FRINT64XDr
10041 6U, // FRINT64XSr
10042 6U, // FRINT64Xv2f32
10043 6U, // FRINT64Xv2f64
10044 6U, // FRINT64Xv4f32
10045 6U, // FRINT64ZDr
10046 6U, // FRINT64ZSr
10047 6U, // FRINT64Zv2f32
10048 6U, // FRINT64Zv2f64
10049 6U, // FRINT64Zv4f32
10050 6U, // FRINTADr
10051 6U, // FRINTAHr
10052 6U, // FRINTASr
10053 2U, // FRINTA_ZPmZ_D
10054 0U, // FRINTA_ZPmZ_H
10055 4U, // FRINTA_ZPmZ_S
10056 6U, // FRINTAv2f32
10057 6U, // FRINTAv2f64
10058 6U, // FRINTAv4f16
10059 6U, // FRINTAv4f32
10060 6U, // FRINTAv8f16
10061 6U, // FRINTIDr
10062 6U, // FRINTIHr
10063 6U, // FRINTISr
10064 2U, // FRINTI_ZPmZ_D
10065 0U, // FRINTI_ZPmZ_H
10066 4U, // FRINTI_ZPmZ_S
10067 6U, // FRINTIv2f32
10068 6U, // FRINTIv2f64
10069 6U, // FRINTIv4f16
10070 6U, // FRINTIv4f32
10071 6U, // FRINTIv8f16
10072 6U, // FRINTMDr
10073 6U, // FRINTMHr
10074 6U, // FRINTMSr
10075 2U, // FRINTM_ZPmZ_D
10076 0U, // FRINTM_ZPmZ_H
10077 4U, // FRINTM_ZPmZ_S
10078 6U, // FRINTMv2f32
10079 6U, // FRINTMv2f64
10080 6U, // FRINTMv4f16
10081 6U, // FRINTMv4f32
10082 6U, // FRINTMv8f16
10083 6U, // FRINTNDr
10084 6U, // FRINTNHr
10085 6U, // FRINTNSr
10086 2U, // FRINTN_ZPmZ_D
10087 0U, // FRINTN_ZPmZ_H
10088 4U, // FRINTN_ZPmZ_S
10089 6U, // FRINTNv2f32
10090 6U, // FRINTNv2f64
10091 6U, // FRINTNv4f16
10092 6U, // FRINTNv4f32
10093 6U, // FRINTNv8f16
10094 6U, // FRINTPDr
10095 6U, // FRINTPHr
10096 6U, // FRINTPSr
10097 2U, // FRINTP_ZPmZ_D
10098 0U, // FRINTP_ZPmZ_H
10099 4U, // FRINTP_ZPmZ_S
10100 6U, // FRINTPv2f32
10101 6U, // FRINTPv2f64
10102 6U, // FRINTPv4f16
10103 6U, // FRINTPv4f32
10104 6U, // FRINTPv8f16
10105 6U, // FRINTXDr
10106 6U, // FRINTXHr
10107 6U, // FRINTXSr
10108 2U, // FRINTX_ZPmZ_D
10109 0U, // FRINTX_ZPmZ_H
10110 4U, // FRINTX_ZPmZ_S
10111 6U, // FRINTXv2f32
10112 6U, // FRINTXv2f64
10113 6U, // FRINTXv4f16
10114 6U, // FRINTXv4f32
10115 6U, // FRINTXv8f16
10116 6U, // FRINTZDr
10117 6U, // FRINTZHr
10118 6U, // FRINTZSr
10119 2U, // FRINTZ_ZPmZ_D
10120 0U, // FRINTZ_ZPmZ_H
10121 4U, // FRINTZ_ZPmZ_S
10122 6U, // FRINTZv2f32
10123 6U, // FRINTZv2f64
10124 6U, // FRINTZv4f16
10125 6U, // FRINTZv4f32
10126 6U, // FRINTZv8f16
10127 6U, // FRSQRTE_ZZ_D
10128 0U, // FRSQRTE_ZZ_H
10129 6U, // FRSQRTE_ZZ_S
10130 6U, // FRSQRTEv1f16
10131 6U, // FRSQRTEv1i32
10132 6U, // FRSQRTEv1i64
10133 6U, // FRSQRTEv2f32
10134 6U, // FRSQRTEv2f64
10135 6U, // FRSQRTEv4f16
10136 6U, // FRSQRTEv4f32
10137 6U, // FRSQRTEv8f16
10138 776U, // FRSQRTS16
10139 776U, // FRSQRTS32
10140 776U, // FRSQRTS64
10141 1544U, // FRSQRTS_ZZZ_D
10142 14U, // FRSQRTS_ZZZ_H
10143 3080U, // FRSQRTS_ZZZ_S
10144 2056U, // FRSQRTSv2f32
10145 2056U, // FRSQRTSv2f64
10146 2056U, // FRSQRTSv4f16
10147 2056U, // FRSQRTSv4f32
10148 2056U, // FRSQRTSv8f16
10149 2131468U, // FSCALE_ZPmZ_D
10150 3214094U, // FSCALE_ZPmZ_H
10151 4230156U, // FSCALE_ZPmZ_S
10152 6U, // FSQRTDr
10153 6U, // FSQRTHr
10154 6U, // FSQRTSr
10155 2U, // FSQRT_ZPmZ_D
10156 0U, // FSQRT_ZPmZ_H
10157 4U, // FSQRT_ZPmZ_S
10158 6U, // FSQRTv2f32
10159 6U, // FSQRTv2f64
10160 6U, // FSQRTv4f16
10161 6U, // FSQRTv4f32
10162 6U, // FSQRTv8f16
10163 776U, // FSUBDrr
10164 776U, // FSUBHrr
10165 14714380U, // FSUBR_ZPmI_D
10166 363278U, // FSUBR_ZPmI_H
10167 14715916U, // FSUBR_ZPmI_S
10168 2131468U, // FSUBR_ZPmZ_D
10169 3214094U, // FSUBR_ZPmZ_H
10170 4230156U, // FSUBR_ZPmZ_S
10171 776U, // FSUBSrr
10172 14714380U, // FSUB_ZPmI_D
10173 363278U, // FSUB_ZPmI_H
10174 14715916U, // FSUB_ZPmI_S
10175 2131468U, // FSUB_ZPmZ_D
10176 3214094U, // FSUB_ZPmZ_H
10177 4230156U, // FSUB_ZPmZ_S
10178 1544U, // FSUB_ZZZ_D
10179 14U, // FSUB_ZZZ_H
10180 3080U, // FSUB_ZZZ_S
10181 2056U, // FSUBv2f32
10182 2056U, // FSUBv2f64
10183 2056U, // FSUBv4f16
10184 2056U, // FSUBv4f32
10185 2056U, // FSUBv8f16
10186 34312U, // FTMAD_ZZI_D
10187 133902U, // FTMAD_ZZI_H
10188 35848U, // FTMAD_ZZI_S
10189 1544U, // FTSMUL_ZZZ_D
10190 14U, // FTSMUL_ZZZ_H
10191 3080U, // FTSMUL_ZZZ_S
10192 1544U, // FTSSEL_ZZZ_D
10193 14U, // FTSSEL_ZZZ_H
10194 3080U, // FTSSEL_ZZZ_S
10195 271624U, // GLD1B_D_IMM_REAL
10196 11272U, // GLD1B_D_REAL
10197 11528U, // GLD1B_D_SXTW_REAL
10198 11784U, // GLD1B_D_UXTW_REAL
10199 271624U, // GLD1B_S_IMM_REAL
10200 12040U, // GLD1B_S_SXTW_REAL
10201 12296U, // GLD1B_S_UXTW_REAL
10202 274696U, // GLD1D_IMM_REAL
10203 11272U, // GLD1D_REAL
10204 12808U, // GLD1D_SCALED_REAL
10205 11528U, // GLD1D_SXTW_REAL
10206 13064U, // GLD1D_SXTW_SCALED_REAL
10207 11784U, // GLD1D_UXTW_REAL
10208 13320U, // GLD1D_UXTW_SCALED_REAL
10209 275720U, // GLD1H_D_IMM_REAL
10210 11272U, // GLD1H_D_REAL
10211 13832U, // GLD1H_D_SCALED_REAL
10212 11528U, // GLD1H_D_SXTW_REAL
10213 14088U, // GLD1H_D_SXTW_SCALED_REAL
10214 11784U, // GLD1H_D_UXTW_REAL
10215 14344U, // GLD1H_D_UXTW_SCALED_REAL
10216 275720U, // GLD1H_S_IMM_REAL
10217 12040U, // GLD1H_S_SXTW_REAL
10218 14600U, // GLD1H_S_SXTW_SCALED_REAL
10219 12296U, // GLD1H_S_UXTW_REAL
10220 14856U, // GLD1H_S_UXTW_SCALED_REAL
10221 271624U, // GLD1SB_D_IMM_REAL
10222 11272U, // GLD1SB_D_REAL
10223 11528U, // GLD1SB_D_SXTW_REAL
10224 11784U, // GLD1SB_D_UXTW_REAL
10225 271624U, // GLD1SB_S_IMM_REAL
10226 12040U, // GLD1SB_S_SXTW_REAL
10227 12296U, // GLD1SB_S_UXTW_REAL
10228 275720U, // GLD1SH_D_IMM_REAL
10229 11272U, // GLD1SH_D_REAL
10230 13832U, // GLD1SH_D_SCALED_REAL
10231 11528U, // GLD1SH_D_SXTW_REAL
10232 14088U, // GLD1SH_D_SXTW_SCALED_REAL
10233 11784U, // GLD1SH_D_UXTW_REAL
10234 14344U, // GLD1SH_D_UXTW_SCALED_REAL
10235 275720U, // GLD1SH_S_IMM_REAL
10236 12040U, // GLD1SH_S_SXTW_REAL
10237 14600U, // GLD1SH_S_SXTW_SCALED_REAL
10238 12296U, // GLD1SH_S_UXTW_REAL
10239 14856U, // GLD1SH_S_UXTW_SCALED_REAL
10240 277256U, // GLD1SW_D_IMM_REAL
10241 11272U, // GLD1SW_D_REAL
10242 15368U, // GLD1SW_D_SCALED_REAL
10243 11528U, // GLD1SW_D_SXTW_REAL
10244 15624U, // GLD1SW_D_SXTW_SCALED_REAL
10245 11784U, // GLD1SW_D_UXTW_REAL
10246 15880U, // GLD1SW_D_UXTW_SCALED_REAL
10247 277256U, // GLD1W_D_IMM_REAL
10248 11272U, // GLD1W_D_REAL
10249 15368U, // GLD1W_D_SCALED_REAL
10250 11528U, // GLD1W_D_SXTW_REAL
10251 15624U, // GLD1W_D_SXTW_SCALED_REAL
10252 11784U, // GLD1W_D_UXTW_REAL
10253 15880U, // GLD1W_D_UXTW_SCALED_REAL
10254 277256U, // GLD1W_IMM_REAL
10255 12040U, // GLD1W_SXTW_REAL
10256 16136U, // GLD1W_SXTW_SCALED_REAL
10257 12296U, // GLD1W_UXTW_REAL
10258 16392U, // GLD1W_UXTW_SCALED_REAL
10259 271624U, // GLDFF1B_D_IMM_REAL
10260 11272U, // GLDFF1B_D_REAL
10261 11528U, // GLDFF1B_D_SXTW_REAL
10262 11784U, // GLDFF1B_D_UXTW_REAL
10263 271624U, // GLDFF1B_S_IMM_REAL
10264 12040U, // GLDFF1B_S_SXTW_REAL
10265 12296U, // GLDFF1B_S_UXTW_REAL
10266 274696U, // GLDFF1D_IMM_REAL
10267 11272U, // GLDFF1D_REAL
10268 12808U, // GLDFF1D_SCALED_REAL
10269 11528U, // GLDFF1D_SXTW_REAL
10270 13064U, // GLDFF1D_SXTW_SCALED_REAL
10271 11784U, // GLDFF1D_UXTW_REAL
10272 13320U, // GLDFF1D_UXTW_SCALED_REAL
10273 275720U, // GLDFF1H_D_IMM_REAL
10274 11272U, // GLDFF1H_D_REAL
10275 13832U, // GLDFF1H_D_SCALED_REAL
10276 11528U, // GLDFF1H_D_SXTW_REAL
10277 14088U, // GLDFF1H_D_SXTW_SCALED_REAL
10278 11784U, // GLDFF1H_D_UXTW_REAL
10279 14344U, // GLDFF1H_D_UXTW_SCALED_REAL
10280 275720U, // GLDFF1H_S_IMM_REAL
10281 12040U, // GLDFF1H_S_SXTW_REAL
10282 14600U, // GLDFF1H_S_SXTW_SCALED_REAL
10283 12296U, // GLDFF1H_S_UXTW_REAL
10284 14856U, // GLDFF1H_S_UXTW_SCALED_REAL
10285 271624U, // GLDFF1SB_D_IMM_REAL
10286 11272U, // GLDFF1SB_D_REAL
10287 11528U, // GLDFF1SB_D_SXTW_REAL
10288 11784U, // GLDFF1SB_D_UXTW_REAL
10289 271624U, // GLDFF1SB_S_IMM_REAL
10290 12040U, // GLDFF1SB_S_SXTW_REAL
10291 12296U, // GLDFF1SB_S_UXTW_REAL
10292 275720U, // GLDFF1SH_D_IMM_REAL
10293 11272U, // GLDFF1SH_D_REAL
10294 13832U, // GLDFF1SH_D_SCALED_REAL
10295 11528U, // GLDFF1SH_D_SXTW_REAL
10296 14088U, // GLDFF1SH_D_SXTW_SCALED_REAL
10297 11784U, // GLDFF1SH_D_UXTW_REAL
10298 14344U, // GLDFF1SH_D_UXTW_SCALED_REAL
10299 275720U, // GLDFF1SH_S_IMM_REAL
10300 12040U, // GLDFF1SH_S_SXTW_REAL
10301 14600U, // GLDFF1SH_S_SXTW_SCALED_REAL
10302 12296U, // GLDFF1SH_S_UXTW_REAL
10303 14856U, // GLDFF1SH_S_UXTW_SCALED_REAL
10304 277256U, // GLDFF1SW_D_IMM_REAL
10305 11272U, // GLDFF1SW_D_REAL
10306 15368U, // GLDFF1SW_D_SCALED_REAL
10307 11528U, // GLDFF1SW_D_SXTW_REAL
10308 15624U, // GLDFF1SW_D_SXTW_SCALED_REAL
10309 11784U, // GLDFF1SW_D_UXTW_REAL
10310 15880U, // GLDFF1SW_D_UXTW_SCALED_REAL
10311 277256U, // GLDFF1W_D_IMM_REAL
10312 11272U, // GLDFF1W_D_REAL
10313 15368U, // GLDFF1W_D_SCALED_REAL
10314 11528U, // GLDFF1W_D_SXTW_REAL
10315 15624U, // GLDFF1W_D_SXTW_SCALED_REAL
10316 11784U, // GLDFF1W_D_UXTW_REAL
10317 15880U, // GLDFF1W_D_UXTW_SCALED_REAL
10318 277256U, // GLDFF1W_IMM_REAL
10319 12040U, // GLDFF1W_SXTW_REAL
10320 16136U, // GLDFF1W_SXTW_SCALED_REAL
10321 12296U, // GLDFF1W_UXTW_REAL
10322 16392U, // GLDFF1W_UXTW_SCALED_REAL
10323 776U, // GMI
10324 0U, // HINT
10325 2131474U, // HISTCNT_ZPzZZ_D
10326 4230162U, // HISTCNT_ZPzZZ_S
10327 2568U, // HISTSEG_ZZZ
10328 0U, // HLT
10329 0U, // HVC
10330 0U, // INCB_XPiI
10331 0U, // INCD_XPiI
10332 0U, // INCD_ZPiI
10333 0U, // INCH_XPiI
10334 0U, // INCH_ZPiI
10335 6U, // INCP_XP_B
10336 6U, // INCP_XP_D
10337 6U, // INCP_XP_H
10338 6U, // INCP_XP_S
10339 6U, // INCP_ZP_D
10340 0U, // INCP_ZP_H
10341 6U, // INCP_ZP_S
10342 0U, // INCW_XPiI
10343 0U, // INCW_ZPiI
10344 57U, // INDEX_II_B
10345 776U, // INDEX_II_D
10346 1U, // INDEX_II_H
10347 776U, // INDEX_II_S
10348 23U, // INDEX_IR_B
10349 776U, // INDEX_IR_D
10350 6U, // INDEX_IR_H
10351 776U, // INDEX_IR_S
10352 16648U, // INDEX_RI_B
10353 776U, // INDEX_RI_D
10354 58U, // INDEX_RI_H
10355 776U, // INDEX_RI_S
10356 776U, // INDEX_RR_B
10357 776U, // INDEX_RR_D
10358 22U, // INDEX_RR_H
10359 776U, // INDEX_RR_S
10360 6U, // INSR_ZR_B
10361 6U, // INSR_ZR_D
10362 0U, // INSR_ZR_H
10363 6U, // INSR_ZR_S
10364 6U, // INSR_ZV_B
10365 6U, // INSR_ZV_D
10366 0U, // INSR_ZV_H
10367 6U, // INSR_ZV_S
10368 0U, // INSvi16gpr
10369 1U, // INSvi16lane
10370 0U, // INSvi32gpr
10371 1U, // INSvi32lane
10372 0U, // INSvi64gpr
10373 1U, // INSvi64lane
10374 0U, // INSvi8gpr
10375 1U, // INSvi8lane
10376 776U, // IRG
10377 0U, // ISB
10378 2568U, // LASTA_RPZ_B
10379 1544U, // LASTA_RPZ_D
10380 1288U, // LASTA_RPZ_H
10381 3080U, // LASTA_RPZ_S
10382 2568U, // LASTA_VPZ_B
10383 1544U, // LASTA_VPZ_D
10384 1288U, // LASTA_VPZ_H
10385 3080U, // LASTA_VPZ_S
10386 2568U, // LASTB_RPZ_B
10387 1544U, // LASTB_RPZ_D
10388 1288U, // LASTB_RPZ_H
10389 3080U, // LASTB_RPZ_S
10390 2568U, // LASTB_VPZ_B
10391 1544U, // LASTB_VPZ_D
10392 1288U, // LASTB_VPZ_H
10393 3080U, // LASTB_VPZ_S
10394 16904U, // LD1B
10395 16904U, // LD1B_D
10396 566536U, // LD1B_D_IMM_REAL
10397 16904U, // LD1B_H
10398 566536U, // LD1B_H_IMM_REAL
10399 566536U, // LD1B_IMM_REAL
10400 16904U, // LD1B_S
10401 566536U, // LD1B_S_IMM_REAL
10402 17160U, // LD1D
10403 566536U, // LD1D_IMM_REAL
10404 0U, // LD1Fourv16b
10405 0U, // LD1Fourv16b_POST
10406 0U, // LD1Fourv1d
10407 0U, // LD1Fourv1d_POST
10408 0U, // LD1Fourv2d
10409 0U, // LD1Fourv2d_POST
10410 0U, // LD1Fourv2s
10411 0U, // LD1Fourv2s_POST
10412 0U, // LD1Fourv4h
10413 0U, // LD1Fourv4h_POST
10414 0U, // LD1Fourv4s
10415 0U, // LD1Fourv4s_POST
10416 0U, // LD1Fourv8b
10417 0U, // LD1Fourv8b_POST
10418 0U, // LD1Fourv8h
10419 0U, // LD1Fourv8h_POST
10420 17416U, // LD1H
10421 17416U, // LD1H_D
10422 566536U, // LD1H_D_IMM_REAL
10423 566536U, // LD1H_IMM_REAL
10424 17416U, // LD1H_S
10425 566536U, // LD1H_S_IMM_REAL
10426 0U, // LD1Onev16b
10427 0U, // LD1Onev16b_POST
10428 0U, // LD1Onev1d
10429 0U, // LD1Onev1d_POST
10430 0U, // LD1Onev2d
10431 0U, // LD1Onev2d_POST
10432 0U, // LD1Onev2s
10433 0U, // LD1Onev2s_POST
10434 0U, // LD1Onev4h
10435 0U, // LD1Onev4h_POST
10436 0U, // LD1Onev4s
10437 0U, // LD1Onev4s_POST
10438 0U, // LD1Onev8b
10439 0U, // LD1Onev8b_POST
10440 0U, // LD1Onev8h
10441 0U, // LD1Onev8h_POST
10442 271624U, // LD1RB_D_IMM
10443 271624U, // LD1RB_H_IMM
10444 271624U, // LD1RB_IMM
10445 271624U, // LD1RB_S_IMM
10446 274696U, // LD1RD_IMM
10447 275720U, // LD1RH_D_IMM
10448 275720U, // LD1RH_IMM
10449 275720U, // LD1RH_S_IMM
10450 16904U, // LD1RO_B
10451 17672U, // LD1RO_B_IMM
10452 17160U, // LD1RO_D
10453 17672U, // LD1RO_D_IMM
10454 17416U, // LD1RO_H
10455 17672U, // LD1RO_H_IMM
10456 17928U, // LD1RO_W
10457 17672U, // LD1RO_W_IMM
10458 16904U, // LD1RQ_B
10459 280328U, // LD1RQ_B_IMM
10460 17160U, // LD1RQ_D
10461 280328U, // LD1RQ_D_IMM
10462 17416U, // LD1RQ_H
10463 280328U, // LD1RQ_H_IMM
10464 17928U, // LD1RQ_W
10465 280328U, // LD1RQ_W_IMM
10466 271624U, // LD1RSB_D_IMM
10467 271624U, // LD1RSB_H_IMM
10468 271624U, // LD1RSB_S_IMM
10469 275720U, // LD1RSH_D_IMM
10470 275720U, // LD1RSH_S_IMM
10471 277256U, // LD1RSW_IMM
10472 277256U, // LD1RW_D_IMM
10473 277256U, // LD1RW_IMM
10474 0U, // LD1Rv16b
10475 0U, // LD1Rv16b_POST
10476 0U, // LD1Rv1d
10477 0U, // LD1Rv1d_POST
10478 0U, // LD1Rv2d
10479 0U, // LD1Rv2d_POST
10480 0U, // LD1Rv2s
10481 0U, // LD1Rv2s_POST
10482 0U, // LD1Rv4h
10483 0U, // LD1Rv4h_POST
10484 0U, // LD1Rv4s
10485 0U, // LD1Rv4s_POST
10486 0U, // LD1Rv8b
10487 0U, // LD1Rv8b_POST
10488 0U, // LD1Rv8h
10489 0U, // LD1Rv8h_POST
10490 16904U, // LD1SB_D
10491 566536U, // LD1SB_D_IMM_REAL
10492 16904U, // LD1SB_H
10493 566536U, // LD1SB_H_IMM_REAL
10494 16904U, // LD1SB_S
10495 566536U, // LD1SB_S_IMM_REAL
10496 17416U, // LD1SH_D
10497 566536U, // LD1SH_D_IMM_REAL
10498 17416U, // LD1SH_S
10499 566536U, // LD1SH_S_IMM_REAL
10500 17928U, // LD1SW_D
10501 566536U, // LD1SW_D_IMM_REAL
10502 0U, // LD1Threev16b
10503 0U, // LD1Threev16b_POST
10504 0U, // LD1Threev1d
10505 0U, // LD1Threev1d_POST
10506 0U, // LD1Threev2d
10507 0U, // LD1Threev2d_POST
10508 0U, // LD1Threev2s
10509 0U, // LD1Threev2s_POST
10510 0U, // LD1Threev4h
10511 0U, // LD1Threev4h_POST
10512 0U, // LD1Threev4s
10513 0U, // LD1Threev4s_POST
10514 0U, // LD1Threev8b
10515 0U, // LD1Threev8b_POST
10516 0U, // LD1Threev8h
10517 0U, // LD1Threev8h_POST
10518 0U, // LD1Twov16b
10519 0U, // LD1Twov16b_POST
10520 0U, // LD1Twov1d
10521 0U, // LD1Twov1d_POST
10522 0U, // LD1Twov2d
10523 0U, // LD1Twov2d_POST
10524 0U, // LD1Twov2s
10525 0U, // LD1Twov2s_POST
10526 0U, // LD1Twov4h
10527 0U, // LD1Twov4h_POST
10528 0U, // LD1Twov4s
10529 0U, // LD1Twov4s_POST
10530 0U, // LD1Twov8b
10531 0U, // LD1Twov8b_POST
10532 0U, // LD1Twov8h
10533 0U, // LD1Twov8h_POST
10534 17928U, // LD1W
10535 17928U, // LD1W_D
10536 566536U, // LD1W_D_IMM_REAL
10537 566536U, // LD1W_IMM_REAL
10538 0U, // LD1i16
10539 0U, // LD1i16_POST
10540 0U, // LD1i32
10541 0U, // LD1i32_POST
10542 0U, // LD1i64
10543 0U, // LD1i64_POST
10544 0U, // LD1i8
10545 0U, // LD1i8_POST
10546 16904U, // LD2B
10547 570632U, // LD2B_IMM
10548 17160U, // LD2D
10549 570632U, // LD2D_IMM
10550 17416U, // LD2H
10551 570632U, // LD2H_IMM
10552 0U, // LD2Rv16b
10553 0U, // LD2Rv16b_POST
10554 0U, // LD2Rv1d
10555 0U, // LD2Rv1d_POST
10556 0U, // LD2Rv2d
10557 0U, // LD2Rv2d_POST
10558 0U, // LD2Rv2s
10559 0U, // LD2Rv2s_POST
10560 0U, // LD2Rv4h
10561 0U, // LD2Rv4h_POST
10562 0U, // LD2Rv4s
10563 0U, // LD2Rv4s_POST
10564 0U, // LD2Rv8b
10565 0U, // LD2Rv8b_POST
10566 0U, // LD2Rv8h
10567 0U, // LD2Rv8h_POST
10568 0U, // LD2Twov16b
10569 0U, // LD2Twov16b_POST
10570 0U, // LD2Twov2d
10571 0U, // LD2Twov2d_POST
10572 0U, // LD2Twov2s
10573 0U, // LD2Twov2s_POST
10574 0U, // LD2Twov4h
10575 0U, // LD2Twov4h_POST
10576 0U, // LD2Twov4s
10577 0U, // LD2Twov4s_POST
10578 0U, // LD2Twov8b
10579 0U, // LD2Twov8b_POST
10580 0U, // LD2Twov8h
10581 0U, // LD2Twov8h_POST
10582 17928U, // LD2W
10583 570632U, // LD2W_IMM
10584 0U, // LD2i16
10585 0U, // LD2i16_POST
10586 0U, // LD2i32
10587 0U, // LD2i32_POST
10588 0U, // LD2i64
10589 0U, // LD2i64_POST
10590 0U, // LD2i8
10591 0U, // LD2i8_POST
10592 16904U, // LD3B
10593 18440U, // LD3B_IMM
10594 17160U, // LD3D
10595 18440U, // LD3D_IMM
10596 17416U, // LD3H
10597 18440U, // LD3H_IMM
10598 0U, // LD3Rv16b
10599 0U, // LD3Rv16b_POST
10600 0U, // LD3Rv1d
10601 0U, // LD3Rv1d_POST
10602 0U, // LD3Rv2d
10603 0U, // LD3Rv2d_POST
10604 0U, // LD3Rv2s
10605 0U, // LD3Rv2s_POST
10606 0U, // LD3Rv4h
10607 0U, // LD3Rv4h_POST
10608 0U, // LD3Rv4s
10609 0U, // LD3Rv4s_POST
10610 0U, // LD3Rv8b
10611 0U, // LD3Rv8b_POST
10612 0U, // LD3Rv8h
10613 0U, // LD3Rv8h_POST
10614 0U, // LD3Threev16b
10615 0U, // LD3Threev16b_POST
10616 0U, // LD3Threev2d
10617 0U, // LD3Threev2d_POST
10618 0U, // LD3Threev2s
10619 0U, // LD3Threev2s_POST
10620 0U, // LD3Threev4h
10621 0U, // LD3Threev4h_POST
10622 0U, // LD3Threev4s
10623 0U, // LD3Threev4s_POST
10624 0U, // LD3Threev8b
10625 0U, // LD3Threev8b_POST
10626 0U, // LD3Threev8h
10627 0U, // LD3Threev8h_POST
10628 17928U, // LD3W
10629 18440U, // LD3W_IMM
10630 0U, // LD3i16
10631 0U, // LD3i16_POST
10632 0U, // LD3i32
10633 0U, // LD3i32_POST
10634 0U, // LD3i64
10635 0U, // LD3i64_POST
10636 0U, // LD3i8
10637 0U, // LD3i8_POST
10638 16904U, // LD4B
10639 572168U, // LD4B_IMM
10640 17160U, // LD4D
10641 572168U, // LD4D_IMM
10642 0U, // LD4Fourv16b
10643 0U, // LD4Fourv16b_POST
10644 0U, // LD4Fourv2d
10645 0U, // LD4Fourv2d_POST
10646 0U, // LD4Fourv2s
10647 0U, // LD4Fourv2s_POST
10648 0U, // LD4Fourv4h
10649 0U, // LD4Fourv4h_POST
10650 0U, // LD4Fourv4s
10651 0U, // LD4Fourv4s_POST
10652 0U, // LD4Fourv8b
10653 0U, // LD4Fourv8b_POST
10654 0U, // LD4Fourv8h
10655 0U, // LD4Fourv8h_POST
10656 17416U, // LD4H
10657 572168U, // LD4H_IMM
10658 0U, // LD4Rv16b
10659 0U, // LD4Rv16b_POST
10660 0U, // LD4Rv1d
10661 0U, // LD4Rv1d_POST
10662 0U, // LD4Rv2d
10663 0U, // LD4Rv2d_POST
10664 0U, // LD4Rv2s
10665 0U, // LD4Rv2s_POST
10666 0U, // LD4Rv4h
10667 0U, // LD4Rv4h_POST
10668 0U, // LD4Rv4s
10669 0U, // LD4Rv4s_POST
10670 0U, // LD4Rv8b
10671 0U, // LD4Rv8b_POST
10672 0U, // LD4Rv8h
10673 0U, // LD4Rv8h_POST
10674 17928U, // LD4W
10675 572168U, // LD4W_IMM
10676 0U, // LD4i16
10677 0U, // LD4i16_POST
10678 0U, // LD4i32
10679 0U, // LD4i32_POST
10680 0U, // LD4i64
10681 0U, // LD4i64_POST
10682 0U, // LD4i8
10683 0U, // LD4i8_POST
10684 0U, // LD64B
10685 1U, // LDADDAB
10686 1U, // LDADDAH
10687 1U, // LDADDALB
10688 1U, // LDADDALH
10689 1U, // LDADDALW
10690 1U, // LDADDALX
10691 1U, // LDADDAW
10692 1U, // LDADDAX
10693 1U, // LDADDB
10694 1U, // LDADDH
10695 1U, // LDADDLB
10696 1U, // LDADDLH
10697 1U, // LDADDLW
10698 1U, // LDADDLX
10699 1U, // LDADDW
10700 1U, // LDADDX
10701 60U, // LDAPRB
10702 60U, // LDAPRH
10703 60U, // LDAPRW
10704 60U, // LDAPRX
10705 262920U, // LDAPURBi
10706 262920U, // LDAPURHi
10707 262920U, // LDAPURSBWi
10708 262920U, // LDAPURSBXi
10709 262920U, // LDAPURSHWi
10710 262920U, // LDAPURSHXi
10711 262920U, // LDAPURSWi
10712 262920U, // LDAPURXi
10713 262920U, // LDAPURi
10714 60U, // LDARB
10715 60U, // LDARH
10716 60U, // LDARW
10717 60U, // LDARX
10718 262936U, // LDAXPW
10719 262936U, // LDAXPX
10720 60U, // LDAXRB
10721 60U, // LDAXRH
10722 60U, // LDAXRW
10723 60U, // LDAXRX
10724 1U, // LDCLRAB
10725 1U, // LDCLRAH
10726 1U, // LDCLRALB
10727 1U, // LDCLRALH
10728 1U, // LDCLRALW
10729 1U, // LDCLRALX
10730 1U, // LDCLRAW
10731 1U, // LDCLRAX
10732 1U, // LDCLRB
10733 1U, // LDCLRH
10734 1U, // LDCLRLB
10735 1U, // LDCLRLH
10736 1U, // LDCLRLW
10737 1U, // LDCLRLX
10738 1U, // LDCLRW
10739 1U, // LDCLRX
10740 1U, // LDEORAB
10741 1U, // LDEORAH
10742 1U, // LDEORALB
10743 1U, // LDEORALH
10744 1U, // LDEORALW
10745 1U, // LDEORALX
10746 1U, // LDEORAW
10747 1U, // LDEORAX
10748 1U, // LDEORB
10749 1U, // LDEORH
10750 1U, // LDEORLB
10751 1U, // LDEORLH
10752 1U, // LDEORLW
10753 1U, // LDEORLX
10754 1U, // LDEORW
10755 1U, // LDEORX
10756 16904U, // LDFF1B_D_REAL
10757 16904U, // LDFF1B_H_REAL
10758 16904U, // LDFF1B_REAL
10759 16904U, // LDFF1B_S_REAL
10760 17160U, // LDFF1D_REAL
10761 17416U, // LDFF1H_D_REAL
10762 17416U, // LDFF1H_REAL
10763 17416U, // LDFF1H_S_REAL
10764 16904U, // LDFF1SB_D_REAL
10765 16904U, // LDFF1SB_H_REAL
10766 16904U, // LDFF1SB_S_REAL
10767 17416U, // LDFF1SH_D_REAL
10768 17416U, // LDFF1SH_S_REAL
10769 17928U, // LDFF1SW_D_REAL
10770 17928U, // LDFF1W_D_REAL
10771 17928U, // LDFF1W_REAL
10772 280328U, // LDG
10773 60U, // LDGM
10774 60U, // LDLARB
10775 60U, // LDLARH
10776 60U, // LDLARW
10777 60U, // LDLARX
10778 566536U, // LDNF1B_D_IMM_REAL
10779 566536U, // LDNF1B_H_IMM_REAL
10780 566536U, // LDNF1B_IMM_REAL
10781 566536U, // LDNF1B_S_IMM_REAL
10782 566536U, // LDNF1D_IMM_REAL
10783 566536U, // LDNF1H_D_IMM_REAL
10784 566536U, // LDNF1H_IMM_REAL
10785 566536U, // LDNF1H_S_IMM_REAL
10786 566536U, // LDNF1SB_D_IMM_REAL
10787 566536U, // LDNF1SB_H_IMM_REAL
10788 566536U, // LDNF1SB_S_IMM_REAL
10789 566536U, // LDNF1SH_D_IMM_REAL
10790 566536U, // LDNF1SH_S_IMM_REAL
10791 566536U, // LDNF1SW_D_IMM_REAL
10792 566536U, // LDNF1W_D_IMM_REAL
10793 566536U, // LDNF1W_IMM_REAL
10794 19956504U, // LDNPDi
10795 21005080U, // LDNPQi
10796 22053656U, // LDNPSi
10797 22053656U, // LDNPWi
10798 19956504U, // LDNPXi
10799 566536U, // LDNT1B_ZRI
10800 16904U, // LDNT1B_ZRR
10801 271624U, // LDNT1B_ZZR_D_REAL
10802 271624U, // LDNT1B_ZZR_S_REAL
10803 566536U, // LDNT1D_ZRI
10804 17160U, // LDNT1D_ZRR
10805 271624U, // LDNT1D_ZZR_D_REAL
10806 566536U, // LDNT1H_ZRI
10807 17416U, // LDNT1H_ZRR
10808 271624U, // LDNT1H_ZZR_D_REAL
10809 271624U, // LDNT1H_ZZR_S_REAL
10810 271624U, // LDNT1SB_ZZR_D_REAL
10811 271624U, // LDNT1SB_ZZR_S_REAL
10812 271624U, // LDNT1SH_ZZR_D_REAL
10813 271624U, // LDNT1SH_ZZR_S_REAL
10814 271624U, // LDNT1SW_ZZR_D_REAL
10815 566536U, // LDNT1W_ZRI
10816 17928U, // LDNT1W_ZRR
10817 271624U, // LDNT1W_ZZR_D_REAL
10818 271624U, // LDNT1W_ZZR_S_REAL
10819 19956504U, // LDPDi
10820 23667992U, // LDPDpost
10821 291546392U, // LDPDpre
10822 21005080U, // LDPQi
10823 24716568U, // LDPQpost
10824 292594968U, // LDPQpre
10825 22053656U, // LDPSWi
10826 25765144U, // LDPSWpost
10827 293643544U, // LDPSWpre
10828 22053656U, // LDPSi
10829 25765144U, // LDPSpost
10830 293643544U, // LDPSpre
10831 22053656U, // LDPWi
10832 25765144U, // LDPWpost
10833 293643544U, // LDPWpre
10834 19956504U, // LDPXi
10835 23667992U, // LDPXpost
10836 291546392U, // LDPXpre
10837 18696U, // LDRAAindexed
10838 635144U, // LDRAAwriteback
10839 18696U, // LDRABindexed
10840 635144U, // LDRABwriteback
10841 9534U, // LDRBBpost
10842 632072U, // LDRBBpre
10843 26247944U, // LDRBBroW
10844 27296520U, // LDRBBroX
10845 18952U, // LDRBBui
10846 9534U, // LDRBpost
10847 632072U, // LDRBpre
10848 26247944U, // LDRBroW
10849 27296520U, // LDRBroX
10850 18952U, // LDRBui
10851 0U, // LDRDl
10852 9534U, // LDRDpost
10853 632072U, // LDRDpre
10854 28345096U, // LDRDroW
10855 29393672U, // LDRDroX
10856 19208U, // LDRDui
10857 9534U, // LDRHHpost
10858 632072U, // LDRHHpre
10859 30442248U, // LDRHHroW
10860 31490824U, // LDRHHroX
10861 19464U, // LDRHHui
10862 9534U, // LDRHpost
10863 632072U, // LDRHpre
10864 30442248U, // LDRHroW
10865 31490824U, // LDRHroX
10866 19464U, // LDRHui
10867 0U, // LDRQl
10868 9534U, // LDRQpost
10869 632072U, // LDRQpre
10870 32539400U, // LDRQroW
10871 33587976U, // LDRQroX
10872 19720U, // LDRQui
10873 9534U, // LDRSBWpost
10874 632072U, // LDRSBWpre
10875 26247944U, // LDRSBWroW
10876 27296520U, // LDRSBWroX
10877 18952U, // LDRSBWui
10878 9534U, // LDRSBXpost
10879 632072U, // LDRSBXpre
10880 26247944U, // LDRSBXroW
10881 27296520U, // LDRSBXroX
10882 18952U, // LDRSBXui
10883 9534U, // LDRSHWpost
10884 632072U, // LDRSHWpre
10885 30442248U, // LDRSHWroW
10886 31490824U, // LDRSHWroX
10887 19464U, // LDRSHWui
10888 9534U, // LDRSHXpost
10889 632072U, // LDRSHXpre
10890 30442248U, // LDRSHXroW
10891 31490824U, // LDRSHXroX
10892 19464U, // LDRSHXui
10893 0U, // LDRSWl
10894 9534U, // LDRSWpost
10895 632072U, // LDRSWpre
10896 34636552U, // LDRSWroW
10897 35685128U, // LDRSWroX
10898 19976U, // LDRSWui
10899 0U, // LDRSl
10900 9534U, // LDRSpost
10901 632072U, // LDRSpre
10902 34636552U, // LDRSroW
10903 35685128U, // LDRSroX
10904 19976U, // LDRSui
10905 0U, // LDRWl
10906 9534U, // LDRWpost
10907 632072U, // LDRWpre
10908 34636552U, // LDRWroW
10909 35685128U, // LDRWroX
10910 19976U, // LDRWui
10911 0U, // LDRXl
10912 9534U, // LDRXpost
10913 632072U, // LDRXpre
10914 28345096U, // LDRXroW
10915 29393672U, // LDRXroX
10916 19208U, // LDRXui
10917 557832U, // LDR_PXI
10918 557832U, // LDR_ZXI
10919 1U, // LDSETAB
10920 1U, // LDSETAH
10921 1U, // LDSETALB
10922 1U, // LDSETALH
10923 1U, // LDSETALW
10924 1U, // LDSETALX
10925 1U, // LDSETAW
10926 1U, // LDSETAX
10927 1U, // LDSETB
10928 1U, // LDSETH
10929 1U, // LDSETLB
10930 1U, // LDSETLH
10931 1U, // LDSETLW
10932 1U, // LDSETLX
10933 1U, // LDSETW
10934 1U, // LDSETX
10935 1U, // LDSMAXAB
10936 1U, // LDSMAXAH
10937 1U, // LDSMAXALB
10938 1U, // LDSMAXALH
10939 1U, // LDSMAXALW
10940 1U, // LDSMAXALX
10941 1U, // LDSMAXAW
10942 1U, // LDSMAXAX
10943 1U, // LDSMAXB
10944 1U, // LDSMAXH
10945 1U, // LDSMAXLB
10946 1U, // LDSMAXLH
10947 1U, // LDSMAXLW
10948 1U, // LDSMAXLX
10949 1U, // LDSMAXW
10950 1U, // LDSMAXX
10951 1U, // LDSMINAB
10952 1U, // LDSMINAH
10953 1U, // LDSMINALB
10954 1U, // LDSMINALH
10955 1U, // LDSMINALW
10956 1U, // LDSMINALX
10957 1U, // LDSMINAW
10958 1U, // LDSMINAX
10959 1U, // LDSMINB
10960 1U, // LDSMINH
10961 1U, // LDSMINLB
10962 1U, // LDSMINLH
10963 1U, // LDSMINLW
10964 1U, // LDSMINLX
10965 1U, // LDSMINW
10966 1U, // LDSMINX
10967 262920U, // LDTRBi
10968 262920U, // LDTRHi
10969 262920U, // LDTRSBWi
10970 262920U, // LDTRSBXi
10971 262920U, // LDTRSHWi
10972 262920U, // LDTRSHXi
10973 262920U, // LDTRSWi
10974 262920U, // LDTRWi
10975 262920U, // LDTRXi
10976 1U, // LDUMAXAB
10977 1U, // LDUMAXAH
10978 1U, // LDUMAXALB
10979 1U, // LDUMAXALH
10980 1U, // LDUMAXALW
10981 1U, // LDUMAXALX
10982 1U, // LDUMAXAW
10983 1U, // LDUMAXAX
10984 1U, // LDUMAXB
10985 1U, // LDUMAXH
10986 1U, // LDUMAXLB
10987 1U, // LDUMAXLH
10988 1U, // LDUMAXLW
10989 1U, // LDUMAXLX
10990 1U, // LDUMAXW
10991 1U, // LDUMAXX
10992 1U, // LDUMINAB
10993 1U, // LDUMINAH
10994 1U, // LDUMINALB
10995 1U, // LDUMINALH
10996 1U, // LDUMINALW
10997 1U, // LDUMINALX
10998 1U, // LDUMINAW
10999 1U, // LDUMINAX
11000 1U, // LDUMINB
11001 1U, // LDUMINH
11002 1U, // LDUMINLB
11003 1U, // LDUMINLH
11004 1U, // LDUMINLW
11005 1U, // LDUMINLX
11006 1U, // LDUMINW
11007 1U, // LDUMINX
11008 262920U, // LDURBBi
11009 262920U, // LDURBi
11010 262920U, // LDURDi
11011 262920U, // LDURHHi
11012 262920U, // LDURHi
11013 262920U, // LDURQi
11014 262920U, // LDURSBWi
11015 262920U, // LDURSBXi
11016 262920U, // LDURSHWi
11017 262920U, // LDURSHXi
11018 262920U, // LDURSWi
11019 262920U, // LDURSi
11020 262920U, // LDURWi
11021 262920U, // LDURXi
11022 262936U, // LDXPW
11023 262936U, // LDXPX
11024 60U, // LDXRB
11025 60U, // LDXRH
11026 60U, // LDXRW
11027 60U, // LDXRX
11028 1083916U, // LSLR_ZPmZ_B
11029 2131468U, // LSLR_ZPmZ_D
11030 3214094U, // LSLR_ZPmZ_H
11031 4230156U, // LSLR_ZPmZ_S
11032 776U, // LSLVWr
11033 776U, // LSLVXr
11034 2132492U, // LSL_WIDE_ZPmZ_B
11035 166670U, // LSL_WIDE_ZPmZ_H
11036 2133004U, // LSL_WIDE_ZPmZ_S
11037 1544U, // LSL_WIDE_ZZZ_B
11038 20U, // LSL_WIDE_ZZZ_H
11039 1544U, // LSL_WIDE_ZZZ_S
11040 35340U, // LSL_ZPmI_B
11041 34316U, // LSL_ZPmI_D
11042 133902U, // LSL_ZPmI_H
11043 35852U, // LSL_ZPmI_S
11044 1083916U, // LSL_ZPmZ_B
11045 2131468U, // LSL_ZPmZ_D
11046 3214094U, // LSL_ZPmZ_H
11047 4230156U, // LSL_ZPmZ_S
11048 776U, // LSL_ZZI_B
11049 776U, // LSL_ZZI_D
11050 22U, // LSL_ZZI_H
11051 776U, // LSL_ZZI_S
11052 1083916U, // LSRR_ZPmZ_B
11053 2131468U, // LSRR_ZPmZ_D
11054 3214094U, // LSRR_ZPmZ_H
11055 4230156U, // LSRR_ZPmZ_S
11056 776U, // LSRVWr
11057 776U, // LSRVXr
11058 2132492U, // LSR_WIDE_ZPmZ_B
11059 166670U, // LSR_WIDE_ZPmZ_H
11060 2133004U, // LSR_WIDE_ZPmZ_S
11061 1544U, // LSR_WIDE_ZZZ_B
11062 20U, // LSR_WIDE_ZZZ_H
11063 1544U, // LSR_WIDE_ZZZ_S
11064 35340U, // LSR_ZPmI_B
11065 34316U, // LSR_ZPmI_D
11066 133902U, // LSR_ZPmI_H
11067 35852U, // LSR_ZPmI_S
11068 1083916U, // LSR_ZPmZ_B
11069 2131468U, // LSR_ZPmZ_D
11070 3214094U, // LSR_ZPmZ_H
11071 4230156U, // LSR_ZPmZ_S
11072 776U, // LSR_ZZI_B
11073 776U, // LSR_ZZI_D
11074 22U, // LSR_ZZI_H
11075 776U, // LSR_ZZI_S
11076 33544U, // MADDWrrr
11077 33544U, // MADDXrrr
11078 20236U, // MAD_ZPmZZ_B
11079 15761676U, // MAD_ZPmZZ_D
11080 3574556U, // MAD_ZPmZZ_H
11081 16810508U, // MAD_ZPmZZ_S
11082 1083922U, // MATCH_PPzZZ_B
11083 3214094U, // MATCH_PPzZZ_H
11084 20236U, // MLA_ZPmZZ_B
11085 15761676U, // MLA_ZPmZZ_D
11086 3574556U, // MLA_ZPmZZ_H
11087 16810508U, // MLA_ZPmZZ_S
11088 3342600U, // MLA_ZZZI_D
11089 9756U, // MLA_ZZZI_H
11090 3342856U, // MLA_ZZZI_S
11091 2312U, // MLAv16i8
11092 2312U, // MLAv2i32
11093 3344648U, // MLAv2i32_indexed
11094 2312U, // MLAv4i16
11095 3344648U, // MLAv4i16_indexed
11096 2312U, // MLAv4i32
11097 3344648U, // MLAv4i32_indexed
11098 2312U, // MLAv8i16
11099 3344648U, // MLAv8i16_indexed
11100 2312U, // MLAv8i8
11101 20236U, // MLS_ZPmZZ_B
11102 15761676U, // MLS_ZPmZZ_D
11103 3574556U, // MLS_ZPmZZ_H
11104 16810508U, // MLS_ZPmZZ_S
11105 3342600U, // MLS_ZZZI_D
11106 9756U, // MLS_ZZZI_H
11107 3342856U, // MLS_ZZZI_S
11108 2312U, // MLSv16i8
11109 2312U, // MLSv2i32
11110 3344648U, // MLSv2i32_indexed
11111 2312U, // MLSv4i16
11112 3344648U, // MLSv4i16_indexed
11113 2312U, // MLSv4i32
11114 3344648U, // MLSv4i32_indexed
11115 2312U, // MLSv8i16
11116 3344648U, // MLSv8i16_indexed
11117 2312U, // MLSv8i8
11118 1U, // MOVID
11119 7U, // MOVIv16b_ns
11120 1U, // MOVIv2d_ns
11121 65U, // MOVIv2i32
11122 65U, // MOVIv2s_msl
11123 65U, // MOVIv4i16
11124 65U, // MOVIv4i32
11125 65U, // MOVIv4s_msl
11126 7U, // MOVIv8b_ns
11127 65U, // MOVIv8i16
11128 0U, // MOVKWi
11129 0U, // MOVKXi
11130 65U, // MOVNWi
11131 65U, // MOVNXi
11132 0U, // MOVPRFX_ZPmZ_B
11133 2U, // MOVPRFX_ZPmZ_D
11134 0U, // MOVPRFX_ZPmZ_H
11135 4U, // MOVPRFX_ZPmZ_S
11136 2578U, // MOVPRFX_ZPzZ_B
11137 1554U, // MOVPRFX_ZPzZ_D
11138 14U, // MOVPRFX_ZPzZ_H
11139 3090U, // MOVPRFX_ZPzZ_S
11140 6U, // MOVPRFX_ZZ
11141 65U, // MOVZWi
11142 65U, // MOVZXi
11143 1U, // MRS
11144 20236U, // MSB_ZPmZZ_B
11145 15761676U, // MSB_ZPmZZ_D
11146 3574556U, // MSB_ZPmZZ_H
11147 16810508U, // MSB_ZPmZZ_S
11148 0U, // MSR
11149 0U, // MSRpstateImm1
11150 0U, // MSRpstateImm4
11151 33544U, // MSUBWrrr
11152 33544U, // MSUBXrrr
11153 776U, // MUL_ZI_B
11154 776U, // MUL_ZI_D
11155 22U, // MUL_ZI_H
11156 776U, // MUL_ZI_S
11157 1083916U, // MUL_ZPmZ_B
11158 2131468U, // MUL_ZPmZ_D
11159 3214094U, // MUL_ZPmZ_H
11160 4230156U, // MUL_ZPmZ_S
11161 493064U, // MUL_ZZZI_D
11162 11022U, // MUL_ZZZI_H
11163 494600U, // MUL_ZZZI_S
11164 2568U, // MUL_ZZZ_B
11165 1544U, // MUL_ZZZ_D
11166 14U, // MUL_ZZZ_H
11167 3080U, // MUL_ZZZ_S
11168 2056U, // MULv16i8
11169 2056U, // MULv2i32
11170 493576U, // MULv2i32_indexed
11171 2056U, // MULv4i16
11172 493576U, // MULv4i16_indexed
11173 2056U, // MULv4i32
11174 493576U, // MULv4i32_indexed
11175 2056U, // MULv8i16
11176 493576U, // MULv8i16_indexed
11177 2056U, // MULv8i8
11178 65U, // MVNIv2i32
11179 65U, // MVNIv2s_msl
11180 65U, // MVNIv4i16
11181 65U, // MVNIv4i32
11182 65U, // MVNIv4s_msl
11183 65U, // MVNIv8i16
11184 1083922U, // NANDS_PPzPP
11185 1083922U, // NAND_PPzPP
11186 2131464U, // NBSL_ZZZZ
11187 0U, // NEG_ZPmZ_B
11188 2U, // NEG_ZPmZ_D
11189 0U, // NEG_ZPmZ_H
11190 4U, // NEG_ZPmZ_S
11191 6U, // NEGv16i8
11192 6U, // NEGv1i64
11193 6U, // NEGv2i32
11194 6U, // NEGv2i64
11195 6U, // NEGv4i16
11196 6U, // NEGv4i32
11197 6U, // NEGv8i16
11198 6U, // NEGv8i8
11199 1083922U, // NMATCH_PPzZZ_B
11200 3214094U, // NMATCH_PPzZZ_H
11201 1083922U, // NORS_PPzPP
11202 1083922U, // NOR_PPzPP
11203 0U, // NOT_ZPmZ_B
11204 2U, // NOT_ZPmZ_D
11205 0U, // NOT_ZPmZ_H
11206 4U, // NOT_ZPmZ_S
11207 6U, // NOTv16i8
11208 6U, // NOTv8i8
11209 1083922U, // ORNS_PPzPP
11210 3592U, // ORNWrs
11211 3592U, // ORNXrs
11212 1083922U, // ORN_PPzPP
11213 2056U, // ORNv16i8
11214 2056U, // ORNv8i8
11215 1083922U, // ORRS_PPzPP
11216 8968U, // ORRWri
11217 3592U, // ORRWrs
11218 9224U, // ORRXri
11219 3592U, // ORRXrs
11220 1083922U, // ORR_PPzPP
11221 9224U, // ORR_ZI
11222 1083916U, // ORR_ZPmZ_B
11223 2131468U, // ORR_ZPmZ_D
11224 3214094U, // ORR_ZPmZ_H
11225 4230156U, // ORR_ZPmZ_S
11226 1544U, // ORR_ZZZ
11227 2056U, // ORRv16i8
11228 0U, // ORRv2i32
11229 0U, // ORRv4i16
11230 0U, // ORRv4i32
11231 0U, // ORRv8i16
11232 2056U, // ORRv8i8
11233 0U, // ORV_VPZ_B
11234 0U, // ORV_VPZ_D
11235 0U, // ORV_VPZ_H
11236 0U, // ORV_VPZ_S
11237 6U, // PACDA
11238 6U, // PACDB
11239 0U, // PACDZA
11240 0U, // PACDZB
11241 776U, // PACGA
11242 6U, // PACIA
11243 0U, // PACIA1716
11244 0U, // PACIASP
11245 0U, // PACIAZ
11246 6U, // PACIB
11247 0U, // PACIB1716
11248 0U, // PACIBSP
11249 0U, // PACIBZ
11250 0U, // PACIZA
11251 0U, // PACIZB
11252 0U, // PFALSE
11253 2568U, // PFIRST_B
11254 3080U, // PMULLB_ZZZ_D
11255 66U, // PMULLB_ZZZ_H
11256 0U, // PMULLB_ZZZ_Q
11257 3080U, // PMULLT_ZZZ_D
11258 66U, // PMULLT_ZZZ_H
11259 0U, // PMULLT_ZZZ_Q
11260 2056U, // PMULLv16i8
11261 2056U, // PMULLv1i64
11262 2056U, // PMULLv2i64
11263 2056U, // PMULLv8i8
11264 2568U, // PMUL_ZZZ_B
11265 2056U, // PMULv16i8
11266 2056U, // PMULv8i8
11267 2568U, // PNEXT_B
11268 1544U, // PNEXT_D
11269 14U, // PNEXT_H
11270 3080U, // PNEXT_S
11271 20518U, // PRFB_D_PZI
11272 68U, // PRFB_D_SCALED
11273 70U, // PRFB_D_SXTW_SCALED
11274 72U, // PRFB_D_UXTW_SCALED
11275 20774U, // PRFB_PRI
11276 74U, // PRFB_PRR
11277 20518U, // PRFB_S_PZI
11278 76U, // PRFB_S_SXTW_SCALED
11279 78U, // PRFB_S_UXTW_SCALED
11280 80U, // PRFD_D_PZI
11281 82U, // PRFD_D_SCALED
11282 84U, // PRFD_D_SXTW_SCALED
11283 86U, // PRFD_D_UXTW_SCALED
11284 20774U, // PRFD_PRI
11285 88U, // PRFD_PRR
11286 80U, // PRFD_S_PZI
11287 90U, // PRFD_S_SXTW_SCALED
11288 92U, // PRFD_S_UXTW_SCALED
11289 94U, // PRFH_D_PZI
11290 96U, // PRFH_D_SCALED
11291 98U, // PRFH_D_SXTW_SCALED
11292 100U, // PRFH_D_UXTW_SCALED
11293 20774U, // PRFH_PRI
11294 102U, // PRFH_PRR
11295 94U, // PRFH_S_PZI
11296 104U, // PRFH_S_SXTW_SCALED
11297 106U, // PRFH_S_UXTW_SCALED
11298 0U, // PRFMl
11299 28345096U, // PRFMroW
11300 29393672U, // PRFMroX
11301 19208U, // PRFMui
11302 108U, // PRFS_PRR
11303 262920U, // PRFUMi
11304 110U, // PRFW_D_PZI
11305 112U, // PRFW_D_SCALED
11306 114U, // PRFW_D_SXTW_SCALED
11307 116U, // PRFW_D_UXTW_SCALED
11308 20774U, // PRFW_PRI
11309 110U, // PRFW_S_PZI
11310 118U, // PRFW_S_SXTW_SCALED
11311 120U, // PRFW_S_UXTW_SCALED
11312 6U, // PTEST_PP
11313 6U, // PTRUES_B
11314 6U, // PTRUES_D
11315 0U, // PTRUES_H
11316 6U, // PTRUES_S
11317 6U, // PTRUE_B
11318 6U, // PTRUE_D
11319 0U, // PTRUE_H
11320 6U, // PTRUE_S
11321 0U, // PUNPKHI_PP
11322 0U, // PUNPKLO_PP
11323 1288U, // RADDHNB_ZZZ_B
11324 10U, // RADDHNB_ZZZ_H
11325 1544U, // RADDHNB_ZZZ_S
11326 1800U, // RADDHNT_ZZZ_B
11327 4U, // RADDHNT_ZZZ_H
11328 264U, // RADDHNT_ZZZ_S
11329 2056U, // RADDHNv2i64_v2i32
11330 2312U, // RADDHNv2i64_v4i32
11331 2056U, // RADDHNv4i32_v4i16
11332 2312U, // RADDHNv4i32_v8i16
11333 2312U, // RADDHNv8i16_v16i8
11334 2056U, // RADDHNv8i16_v8i8
11335 2056U, // RAX1
11336 1544U, // RAX1_ZZZ_D
11337 6U, // RBITWr
11338 6U, // RBITXr
11339 0U, // RBIT_ZPmZ_B
11340 2U, // RBIT_ZPmZ_D
11341 0U, // RBIT_ZPmZ_H
11342 4U, // RBIT_ZPmZ_S
11343 6U, // RBITv16i8
11344 6U, // RBITv8i8
11345 122U, // RDFFRS_PPz
11346 122U, // RDFFR_PPz_REAL
11347 0U, // RDFFR_P_REAL
11348 6U, // RDVLI_XI
11349 0U, // RET
11350 0U, // RETAA
11351 0U, // RETAB
11352 6U, // REV16Wr
11353 6U, // REV16Xr
11354 6U, // REV16v16i8
11355 6U, // REV16v8i8
11356 6U, // REV32Xr
11357 6U, // REV32v16i8
11358 6U, // REV32v4i16
11359 6U, // REV32v8i16
11360 6U, // REV32v8i8
11361 6U, // REV64v16i8
11362 6U, // REV64v2i32
11363 6U, // REV64v4i16
11364 6U, // REV64v4i32
11365 6U, // REV64v8i16
11366 6U, // REV64v8i8
11367 2U, // REVB_ZPmZ_D
11368 0U, // REVB_ZPmZ_H
11369 4U, // REVB_ZPmZ_S
11370 2U, // REVH_ZPmZ_D
11371 4U, // REVH_ZPmZ_S
11372 2U, // REVW_ZPmZ_D
11373 6U, // REVWr
11374 6U, // REVXr
11375 6U, // REV_PP_B
11376 6U, // REV_PP_D
11377 0U, // REV_PP_H
11378 6U, // REV_PP_S
11379 6U, // REV_ZZ_B
11380 6U, // REV_ZZ_D
11381 0U, // REV_ZZ_H
11382 6U, // REV_ZZ_S
11383 0U, // RMIF
11384 776U, // RORVWr
11385 776U, // RORVXr
11386 776U, // RSHRNB_ZZI_B
11387 22U, // RSHRNB_ZZI_H
11388 776U, // RSHRNB_ZZI_S
11389 9480U, // RSHRNT_ZZI_B
11390 38U, // RSHRNT_ZZI_H
11391 9480U, // RSHRNT_ZZI_S
11392 9480U, // RSHRNv16i8_shift
11393 776U, // RSHRNv2i32_shift
11394 776U, // RSHRNv4i16_shift
11395 9480U, // RSHRNv4i32_shift
11396 9480U, // RSHRNv8i16_shift
11397 776U, // RSHRNv8i8_shift
11398 1288U, // RSUBHNB_ZZZ_B
11399 10U, // RSUBHNB_ZZZ_H
11400 1544U, // RSUBHNB_ZZZ_S
11401 1800U, // RSUBHNT_ZZZ_B
11402 4U, // RSUBHNT_ZZZ_H
11403 264U, // RSUBHNT_ZZZ_S
11404 2056U, // RSUBHNv2i64_v2i32
11405 2312U, // RSUBHNv2i64_v4i32
11406 2056U, // RSUBHNv4i32_v4i16
11407 2312U, // RSUBHNv4i32_v8i16
11408 2312U, // RSUBHNv8i16_v16i8
11409 2056U, // RSUBHNv8i16_v8i8
11410 520U, // SABALB_ZZZ_D
11411 0U, // SABALB_ZZZ_H
11412 1800U, // SABALB_ZZZ_S
11413 520U, // SABALT_ZZZ_D
11414 0U, // SABALT_ZZZ_H
11415 1800U, // SABALT_ZZZ_S
11416 2312U, // SABALv16i8_v8i16
11417 2312U, // SABALv2i32_v2i64
11418 2312U, // SABALv4i16_v4i32
11419 2312U, // SABALv4i32_v2i64
11420 2312U, // SABALv8i16_v4i32
11421 2312U, // SABALv8i8_v8i16
11422 0U, // SABA_ZZZ_B
11423 264U, // SABA_ZZZ_D
11424 28U, // SABA_ZZZ_H
11425 520U, // SABA_ZZZ_S
11426 2312U, // SABAv16i8
11427 2312U, // SABAv2i32
11428 2312U, // SABAv4i16
11429 2312U, // SABAv4i32
11430 2312U, // SABAv8i16
11431 2312U, // SABAv8i8
11432 3080U, // SABDLB_ZZZ_D
11433 66U, // SABDLB_ZZZ_H
11434 1288U, // SABDLB_ZZZ_S
11435 3080U, // SABDLT_ZZZ_D
11436 66U, // SABDLT_ZZZ_H
11437 1288U, // SABDLT_ZZZ_S
11438 2056U, // SABDLv16i8_v8i16
11439 2056U, // SABDLv2i32_v2i64
11440 2056U, // SABDLv4i16_v4i32
11441 2056U, // SABDLv4i32_v2i64
11442 2056U, // SABDLv8i16_v4i32
11443 2056U, // SABDLv8i8_v8i16
11444 1083916U, // SABD_ZPmZ_B
11445 2131468U, // SABD_ZPmZ_D
11446 3214094U, // SABD_ZPmZ_H
11447 4230156U, // SABD_ZPmZ_S
11448 2056U, // SABDv16i8
11449 2056U, // SABDv2i32
11450 2056U, // SABDv4i16
11451 2056U, // SABDv4i32
11452 2056U, // SABDv8i16
11453 2056U, // SABDv8i8
11454 524U, // SADALP_ZPmZ_D
11455 0U, // SADALP_ZPmZ_H
11456 1804U, // SADALP_ZPmZ_S
11457 6U, // SADALPv16i8_v8i16
11458 6U, // SADALPv2i32_v1i64
11459 6U, // SADALPv4i16_v2i32
11460 6U, // SADALPv4i32_v2i64
11461 6U, // SADALPv8i16_v4i32
11462 6U, // SADALPv8i8_v4i16
11463 3080U, // SADDLBT_ZZZ_D
11464 66U, // SADDLBT_ZZZ_H
11465 1288U, // SADDLBT_ZZZ_S
11466 3080U, // SADDLB_ZZZ_D
11467 66U, // SADDLB_ZZZ_H
11468 1288U, // SADDLB_ZZZ_S
11469 6U, // SADDLPv16i8_v8i16
11470 6U, // SADDLPv2i32_v1i64
11471 6U, // SADDLPv4i16_v2i32
11472 6U, // SADDLPv4i32_v2i64
11473 6U, // SADDLPv8i16_v4i32
11474 6U, // SADDLPv8i8_v4i16
11475 3080U, // SADDLT_ZZZ_D
11476 66U, // SADDLT_ZZZ_H
11477 1288U, // SADDLT_ZZZ_S
11478 6U, // SADDLVv16i8v
11479 6U, // SADDLVv4i16v
11480 6U, // SADDLVv4i32v
11481 6U, // SADDLVv8i16v
11482 6U, // SADDLVv8i8v
11483 2056U, // SADDLv16i8_v8i16
11484 2056U, // SADDLv2i32_v2i64
11485 2056U, // SADDLv4i16_v4i32
11486 2056U, // SADDLv4i32_v2i64
11487 2056U, // SADDLv8i16_v4i32
11488 2056U, // SADDLv8i8_v8i16
11489 0U, // SADDV_VPZ_B
11490 0U, // SADDV_VPZ_H
11491 0U, // SADDV_VPZ_S
11492 3080U, // SADDWB_ZZZ_D
11493 66U, // SADDWB_ZZZ_H
11494 1288U, // SADDWB_ZZZ_S
11495 3080U, // SADDWT_ZZZ_D
11496 66U, // SADDWT_ZZZ_H
11497 1288U, // SADDWT_ZZZ_S
11498 2056U, // SADDWv16i8_v8i16
11499 2056U, // SADDWv2i32_v2i64
11500 2056U, // SADDWv4i16_v4i32
11501 2056U, // SADDWv4i32_v2i64
11502 2056U, // SADDWv8i16_v4i32
11503 2056U, // SADDWv8i8_v8i16
11504 0U, // SB
11505 264U, // SBCLB_ZZZ_D
11506 520U, // SBCLB_ZZZ_S
11507 264U, // SBCLT_ZZZ_D
11508 520U, // SBCLT_ZZZ_S
11509 776U, // SBCSWr
11510 776U, // SBCSXr
11511 776U, // SBCWr
11512 776U, // SBCXr
11513 33544U, // SBFMWri
11514 33544U, // SBFMXri
11515 776U, // SCVTFSWDri
11516 776U, // SCVTFSWHri
11517 776U, // SCVTFSWSri
11518 776U, // SCVTFSXDri
11519 776U, // SCVTFSXHri
11520 776U, // SCVTFSXSri
11521 6U, // SCVTFUWDri
11522 6U, // SCVTFUWHri
11523 6U, // SCVTFUWSri
11524 6U, // SCVTFUXDri
11525 6U, // SCVTFUXHri
11526 6U, // SCVTFUXSri
11527 2U, // SCVTF_ZPmZ_DtoD
11528 1U, // SCVTF_ZPmZ_DtoH
11529 2U, // SCVTF_ZPmZ_DtoS
11530 0U, // SCVTF_ZPmZ_HtoH
11531 4U, // SCVTF_ZPmZ_StoD
11532 0U, // SCVTF_ZPmZ_StoH
11533 4U, // SCVTF_ZPmZ_StoS
11534 776U, // SCVTFd
11535 776U, // SCVTFh
11536 776U, // SCVTFs
11537 6U, // SCVTFv1i16
11538 6U, // SCVTFv1i32
11539 6U, // SCVTFv1i64
11540 6U, // SCVTFv2f32
11541 6U, // SCVTFv2f64
11542 776U, // SCVTFv2i32_shift
11543 776U, // SCVTFv2i64_shift
11544 6U, // SCVTFv4f16
11545 6U, // SCVTFv4f32
11546 776U, // SCVTFv4i16_shift
11547 776U, // SCVTFv4i32_shift
11548 6U, // SCVTFv8f16
11549 776U, // SCVTFv8i16_shift
11550 2131468U, // SDIVR_ZPmZ_D
11551 4230156U, // SDIVR_ZPmZ_S
11552 776U, // SDIVWr
11553 776U, // SDIVXr
11554 2131468U, // SDIV_ZPmZ_D
11555 4230156U, // SDIV_ZPmZ_S
11556 3344136U, // SDOT_ZZZI_D
11557 9728U, // SDOT_ZZZI_S
11558 1800U, // SDOT_ZZZ_D
11559 0U, // SDOT_ZZZ_S
11560 3344648U, // SDOTlanev16i8
11561 3344648U, // SDOTlanev8i8
11562 0U, // SDOTv16i8
11563 0U, // SDOTv8i8
11564 1083912U, // SEL_PPPP
11565 1083912U, // SEL_ZPZZ_B
11566 2131464U, // SEL_ZPZZ_D
11567 3214094U, // SEL_ZPZZ_H
11568 4230152U, // SEL_ZPZZ_S
11569 0U, // SETF16
11570 0U, // SETF8
11571 0U, // SETFFR
11572 2312U, // SHA1Crrr
11573 6U, // SHA1Hrr
11574 2312U, // SHA1Mrrr
11575 2312U, // SHA1Prrr
11576 2312U, // SHA1SU0rrr
11577 6U, // SHA1SU1rr
11578 2312U, // SHA256H2rrr
11579 2312U, // SHA256Hrrr
11580 6U, // SHA256SU0rr
11581 2312U, // SHA256SU1rrr
11582 2312U, // SHA512H
11583 2312U, // SHA512H2
11584 6U, // SHA512SU0
11585 2312U, // SHA512SU1
11586 1083916U, // SHADD_ZPmZ_B
11587 2131468U, // SHADD_ZPmZ_D
11588 3214094U, // SHADD_ZPmZ_H
11589 4230156U, // SHADD_ZPmZ_S
11590 2056U, // SHADDv16i8
11591 2056U, // SHADDv2i32
11592 2056U, // SHADDv4i16
11593 2056U, // SHADDv4i32
11594 2056U, // SHADDv8i16
11595 2056U, // SHADDv8i8
11596 124U, // SHLLv16i8
11597 126U, // SHLLv2i32
11598 128U, // SHLLv4i16
11599 126U, // SHLLv4i32
11600 128U, // SHLLv8i16
11601 124U, // SHLLv8i8
11602 776U, // SHLd
11603 776U, // SHLv16i8_shift
11604 776U, // SHLv2i32_shift
11605 776U, // SHLv2i64_shift
11606 776U, // SHLv4i16_shift
11607 776U, // SHLv4i32_shift
11608 776U, // SHLv8i16_shift
11609 776U, // SHLv8i8_shift
11610 776U, // SHRNB_ZZI_B
11611 22U, // SHRNB_ZZI_H
11612 776U, // SHRNB_ZZI_S
11613 9480U, // SHRNT_ZZI_B
11614 38U, // SHRNT_ZZI_H
11615 9480U, // SHRNT_ZZI_S
11616 9480U, // SHRNv16i8_shift
11617 776U, // SHRNv2i32_shift
11618 776U, // SHRNv4i16_shift
11619 9480U, // SHRNv4i32_shift
11620 9480U, // SHRNv8i16_shift
11621 776U, // SHRNv8i8_shift
11622 1083916U, // SHSUBR_ZPmZ_B
11623 2131468U, // SHSUBR_ZPmZ_D
11624 3214094U, // SHSUBR_ZPmZ_H
11625 4230156U, // SHSUBR_ZPmZ_S
11626 1083916U, // SHSUB_ZPmZ_B
11627 2131468U, // SHSUB_ZPmZ_D
11628 3214094U, // SHSUB_ZPmZ_H
11629 4230156U, // SHSUB_ZPmZ_S
11630 2056U, // SHSUBv16i8
11631 2056U, // SHSUBv2i32
11632 2056U, // SHSUBv4i16
11633 2056U, // SHSUBv4i32
11634 2056U, // SHSUBv8i16
11635 2056U, // SHSUBv8i8
11636 38U, // SLI_ZZI_B
11637 9480U, // SLI_ZZI_D
11638 38U, // SLI_ZZI_H
11639 9480U, // SLI_ZZI_S
11640 9480U, // SLId
11641 9480U, // SLIv16i8_shift
11642 9480U, // SLIv2i32_shift
11643 9480U, // SLIv2i64_shift
11644 9480U, // SLIv4i16_shift
11645 9480U, // SLIv4i32_shift
11646 9480U, // SLIv8i16_shift
11647 9480U, // SLIv8i8_shift
11648 2312U, // SM3PARTW1
11649 2312U, // SM3PARTW2
11650 5277704U, // SM3SS1
11651 3344648U, // SM3TT1A
11652 3344648U, // SM3TT1B
11653 3344648U, // SM3TT2A
11654 3344648U, // SM3TT2B
11655 6U, // SM4E
11656 3080U, // SM4EKEY_ZZZ_S
11657 2056U, // SM4ENCKEY
11658 3080U, // SM4E_ZZZ_S
11659 33544U, // SMADDLrrr
11660 1083916U, // SMAXP_ZPmZ_B
11661 2131468U, // SMAXP_ZPmZ_D
11662 3214094U, // SMAXP_ZPmZ_H
11663 4230156U, // SMAXP_ZPmZ_S
11664 2056U, // SMAXPv16i8
11665 2056U, // SMAXPv2i32
11666 2056U, // SMAXPv4i16
11667 2056U, // SMAXPv4i32
11668 2056U, // SMAXPv8i16
11669 2056U, // SMAXPv8i8
11670 0U, // SMAXV_VPZ_B
11671 0U, // SMAXV_VPZ_D
11672 0U, // SMAXV_VPZ_H
11673 0U, // SMAXV_VPZ_S
11674 6U, // SMAXVv16i8v
11675 6U, // SMAXVv4i16v
11676 6U, // SMAXVv4i32v
11677 6U, // SMAXVv8i16v
11678 6U, // SMAXVv8i8v
11679 776U, // SMAX_ZI_B
11680 776U, // SMAX_ZI_D
11681 22U, // SMAX_ZI_H
11682 776U, // SMAX_ZI_S
11683 1083916U, // SMAX_ZPmZ_B
11684 2131468U, // SMAX_ZPmZ_D
11685 3214094U, // SMAX_ZPmZ_H
11686 4230156U, // SMAX_ZPmZ_S
11687 2056U, // SMAXv16i8
11688 2056U, // SMAXv2i32
11689 2056U, // SMAXv4i16
11690 2056U, // SMAXv4i32
11691 2056U, // SMAXv8i16
11692 2056U, // SMAXv8i8
11693 0U, // SMC
11694 1083916U, // SMINP_ZPmZ_B
11695 2131468U, // SMINP_ZPmZ_D
11696 3214094U, // SMINP_ZPmZ_H
11697 4230156U, // SMINP_ZPmZ_S
11698 2056U, // SMINPv16i8
11699 2056U, // SMINPv2i32
11700 2056U, // SMINPv4i16
11701 2056U, // SMINPv4i32
11702 2056U, // SMINPv8i16
11703 2056U, // SMINPv8i8
11704 0U, // SMINV_VPZ_B
11705 0U, // SMINV_VPZ_D
11706 0U, // SMINV_VPZ_H
11707 0U, // SMINV_VPZ_S
11708 6U, // SMINVv16i8v
11709 6U, // SMINVv4i16v
11710 6U, // SMINVv4i32v
11711 6U, // SMINVv8i16v
11712 6U, // SMINVv8i8v
11713 776U, // SMIN_ZI_B
11714 776U, // SMIN_ZI_D
11715 22U, // SMIN_ZI_H
11716 776U, // SMIN_ZI_S
11717 1083916U, // SMIN_ZPmZ_B
11718 2131468U, // SMIN_ZPmZ_D
11719 3214094U, // SMIN_ZPmZ_H
11720 4230156U, // SMIN_ZPmZ_S
11721 2056U, // SMINv16i8
11722 2056U, // SMINv2i32
11723 2056U, // SMINv4i16
11724 2056U, // SMINv4i32
11725 2056U, // SMINv8i16
11726 2056U, // SMINv8i8
11727 3342856U, // SMLALB_ZZZI_D
11728 3344136U, // SMLALB_ZZZI_S
11729 520U, // SMLALB_ZZZ_D
11730 0U, // SMLALB_ZZZ_H
11731 1800U, // SMLALB_ZZZ_S
11732 3342856U, // SMLALT_ZZZI_D
11733 3344136U, // SMLALT_ZZZI_S
11734 520U, // SMLALT_ZZZ_D
11735 0U, // SMLALT_ZZZ_H
11736 1800U, // SMLALT_ZZZ_S
11737 2312U, // SMLALv16i8_v8i16
11738 3344648U, // SMLALv2i32_indexed
11739 2312U, // SMLALv2i32_v2i64
11740 3344648U, // SMLALv4i16_indexed
11741 2312U, // SMLALv4i16_v4i32
11742 3344648U, // SMLALv4i32_indexed
11743 2312U, // SMLALv4i32_v2i64
11744 3344648U, // SMLALv8i16_indexed
11745 2312U, // SMLALv8i16_v4i32
11746 2312U, // SMLALv8i8_v8i16
11747 3342856U, // SMLSLB_ZZZI_D
11748 3344136U, // SMLSLB_ZZZI_S
11749 520U, // SMLSLB_ZZZ_D
11750 0U, // SMLSLB_ZZZ_H
11751 1800U, // SMLSLB_ZZZ_S
11752 3342856U, // SMLSLT_ZZZI_D
11753 3344136U, // SMLSLT_ZZZI_S
11754 520U, // SMLSLT_ZZZ_D
11755 0U, // SMLSLT_ZZZ_H
11756 1800U, // SMLSLT_ZZZ_S
11757 2312U, // SMLSLv16i8_v8i16
11758 3344648U, // SMLSLv2i32_indexed
11759 2312U, // SMLSLv2i32_v2i64
11760 3344648U, // SMLSLv4i16_indexed
11761 2312U, // SMLSLv4i16_v4i32
11762 3344648U, // SMLSLv4i32_indexed
11763 2312U, // SMLSLv4i32_v2i64
11764 3344648U, // SMLSLv8i16_indexed
11765 2312U, // SMLSLv8i16_v4i32
11766 2312U, // SMLSLv8i8_v8i16
11767 0U, // SMMLA
11768 0U, // SMMLA_ZZZ
11769 42U, // SMOVvi16to32
11770 42U, // SMOVvi16to64
11771 42U, // SMOVvi32to64
11772 42U, // SMOVvi8to32
11773 42U, // SMOVvi8to64
11774 33544U, // SMSUBLrrr
11775 1083916U, // SMULH_ZPmZ_B
11776 2131468U, // SMULH_ZPmZ_D
11777 3214094U, // SMULH_ZPmZ_H
11778 4230156U, // SMULH_ZPmZ_S
11779 2568U, // SMULH_ZZZ_B
11780 1544U, // SMULH_ZZZ_D
11781 14U, // SMULH_ZZZ_H
11782 3080U, // SMULH_ZZZ_S
11783 776U, // SMULHrr
11784 494600U, // SMULLB_ZZZI_D
11785 492808U, // SMULLB_ZZZI_S
11786 3080U, // SMULLB_ZZZ_D
11787 66U, // SMULLB_ZZZ_H
11788 1288U, // SMULLB_ZZZ_S
11789 494600U, // SMULLT_ZZZI_D
11790 492808U, // SMULLT_ZZZI_S
11791 3080U, // SMULLT_ZZZ_D
11792 66U, // SMULLT_ZZZ_H
11793 1288U, // SMULLT_ZZZ_S
11794 2056U, // SMULLv16i8_v8i16
11795 493576U, // SMULLv2i32_indexed
11796 2056U, // SMULLv2i32_v2i64
11797 493576U, // SMULLv4i16_indexed
11798 2056U, // SMULLv4i16_v4i32
11799 493576U, // SMULLv4i32_indexed
11800 2056U, // SMULLv4i32_v2i64
11801 493576U, // SMULLv8i16_indexed
11802 2056U, // SMULLv8i16_v4i32
11803 2056U, // SMULLv8i8_v8i16
11804 21000U, // SPLICE_ZPZZ_B
11805 21256U, // SPLICE_ZPZZ_D
11806 130U, // SPLICE_ZPZZ_H
11807 21512U, // SPLICE_ZPZZ_S
11808 1083912U, // SPLICE_ZPZ_B
11809 2131464U, // SPLICE_ZPZ_D
11810 3214094U, // SPLICE_ZPZ_H
11811 4230152U, // SPLICE_ZPZ_S
11812 0U, // SQABS_ZPmZ_B
11813 2U, // SQABS_ZPmZ_D
11814 0U, // SQABS_ZPmZ_H
11815 4U, // SQABS_ZPmZ_S
11816 6U, // SQABSv16i8
11817 6U, // SQABSv1i16
11818 6U, // SQABSv1i32
11819 6U, // SQABSv1i64
11820 6U, // SQABSv1i8
11821 6U, // SQABSv2i32
11822 6U, // SQABSv2i64
11823 6U, // SQABSv4i16
11824 6U, // SQABSv4i32
11825 6U, // SQABSv8i16
11826 6U, // SQABSv8i8
11827 4104U, // SQADD_ZI_B
11828 4360U, // SQADD_ZI_D
11829 16U, // SQADD_ZI_H
11830 4616U, // SQADD_ZI_S
11831 1083916U, // SQADD_ZPmZ_B
11832 2131468U, // SQADD_ZPmZ_D
11833 3214094U, // SQADD_ZPmZ_H
11834 4230156U, // SQADD_ZPmZ_S
11835 2568U, // SQADD_ZZZ_B
11836 1544U, // SQADD_ZZZ_D
11837 14U, // SQADD_ZZZ_H
11838 3080U, // SQADD_ZZZ_S
11839 2056U, // SQADDv16i8
11840 776U, // SQADDv1i16
11841 776U, // SQADDv1i32
11842 776U, // SQADDv1i64
11843 776U, // SQADDv1i8
11844 2056U, // SQADDv2i32
11845 2056U, // SQADDv2i64
11846 2056U, // SQADDv4i16
11847 2056U, // SQADDv4i32
11848 2056U, // SQADDv8i16
11849 2056U, // SQADDv8i8
11850 7375368U, // SQCADD_ZZI_B
11851 7374344U, // SQCADD_ZZI_D
11852 232206U, // SQCADD_ZZI_H
11853 7375880U, // SQCADD_ZZI_S
11854 0U, // SQDECB_XPiI
11855 1U, // SQDECB_XPiWdI
11856 0U, // SQDECD_XPiI
11857 1U, // SQDECD_XPiWdI
11858 0U, // SQDECD_ZPiI
11859 0U, // SQDECH_XPiI
11860 1U, // SQDECH_XPiWdI
11861 0U, // SQDECH_ZPiI
11862 21768U, // SQDECP_XPWd_B
11863 21768U, // SQDECP_XPWd_D
11864 21768U, // SQDECP_XPWd_H
11865 21768U, // SQDECP_XPWd_S
11866 6U, // SQDECP_XP_B
11867 6U, // SQDECP_XP_D
11868 6U, // SQDECP_XP_H
11869 6U, // SQDECP_XP_S
11870 6U, // SQDECP_ZP_D
11871 0U, // SQDECP_ZP_H
11872 6U, // SQDECP_ZP_S
11873 0U, // SQDECW_XPiI
11874 1U, // SQDECW_XPiWdI
11875 0U, // SQDECW_ZPiI
11876 520U, // SQDMLALBT_ZZZ_D
11877 0U, // SQDMLALBT_ZZZ_H
11878 1800U, // SQDMLALBT_ZZZ_S
11879 3342856U, // SQDMLALB_ZZZI_D
11880 3344136U, // SQDMLALB_ZZZI_S
11881 520U, // SQDMLALB_ZZZ_D
11882 0U, // SQDMLALB_ZZZ_H
11883 1800U, // SQDMLALB_ZZZ_S
11884 3342856U, // SQDMLALT_ZZZI_D
11885 3344136U, // SQDMLALT_ZZZI_S
11886 520U, // SQDMLALT_ZZZ_D
11887 0U, // SQDMLALT_ZZZ_H
11888 1800U, // SQDMLALT_ZZZ_S
11889 9480U, // SQDMLALi16
11890 9480U, // SQDMLALi32
11891 3344648U, // SQDMLALv1i32_indexed
11892 3344648U, // SQDMLALv1i64_indexed
11893 3344648U, // SQDMLALv2i32_indexed
11894 2312U, // SQDMLALv2i32_v2i64
11895 3344648U, // SQDMLALv4i16_indexed
11896 2312U, // SQDMLALv4i16_v4i32
11897 3344648U, // SQDMLALv4i32_indexed
11898 2312U, // SQDMLALv4i32_v2i64
11899 3344648U, // SQDMLALv8i16_indexed
11900 2312U, // SQDMLALv8i16_v4i32
11901 520U, // SQDMLSLBT_ZZZ_D
11902 0U, // SQDMLSLBT_ZZZ_H
11903 1800U, // SQDMLSLBT_ZZZ_S
11904 3342856U, // SQDMLSLB_ZZZI_D
11905 3344136U, // SQDMLSLB_ZZZI_S
11906 520U, // SQDMLSLB_ZZZ_D
11907 0U, // SQDMLSLB_ZZZ_H
11908 1800U, // SQDMLSLB_ZZZ_S
11909 3342856U, // SQDMLSLT_ZZZI_D
11910 3344136U, // SQDMLSLT_ZZZI_S
11911 520U, // SQDMLSLT_ZZZ_D
11912 0U, // SQDMLSLT_ZZZ_H
11913 1800U, // SQDMLSLT_ZZZ_S
11914 9480U, // SQDMLSLi16
11915 9480U, // SQDMLSLi32
11916 3344648U, // SQDMLSLv1i32_indexed
11917 3344648U, // SQDMLSLv1i64_indexed
11918 3344648U, // SQDMLSLv2i32_indexed
11919 2312U, // SQDMLSLv2i32_v2i64
11920 3344648U, // SQDMLSLv4i16_indexed
11921 2312U, // SQDMLSLv4i16_v4i32
11922 3344648U, // SQDMLSLv4i32_indexed
11923 2312U, // SQDMLSLv4i32_v2i64
11924 3344648U, // SQDMLSLv8i16_indexed
11925 2312U, // SQDMLSLv8i16_v4i32
11926 493064U, // SQDMULH_ZZZI_D
11927 11022U, // SQDMULH_ZZZI_H
11928 494600U, // SQDMULH_ZZZI_S
11929 2568U, // SQDMULH_ZZZ_B
11930 1544U, // SQDMULH_ZZZ_D
11931 14U, // SQDMULH_ZZZ_H
11932 3080U, // SQDMULH_ZZZ_S
11933 776U, // SQDMULHv1i16
11934 493576U, // SQDMULHv1i16_indexed
11935 776U, // SQDMULHv1i32
11936 493576U, // SQDMULHv1i32_indexed
11937 2056U, // SQDMULHv2i32
11938 493576U, // SQDMULHv2i32_indexed
11939 2056U, // SQDMULHv4i16
11940 493576U, // SQDMULHv4i16_indexed
11941 2056U, // SQDMULHv4i32
11942 493576U, // SQDMULHv4i32_indexed
11943 2056U, // SQDMULHv8i16
11944 493576U, // SQDMULHv8i16_indexed
11945 494600U, // SQDMULLB_ZZZI_D
11946 492808U, // SQDMULLB_ZZZI_S
11947 3080U, // SQDMULLB_ZZZ_D
11948 66U, // SQDMULLB_ZZZ_H
11949 1288U, // SQDMULLB_ZZZ_S
11950 494600U, // SQDMULLT_ZZZI_D
11951 492808U, // SQDMULLT_ZZZI_S
11952 3080U, // SQDMULLT_ZZZ_D
11953 66U, // SQDMULLT_ZZZ_H
11954 1288U, // SQDMULLT_ZZZ_S
11955 776U, // SQDMULLi16
11956 776U, // SQDMULLi32
11957 493576U, // SQDMULLv1i32_indexed
11958 493576U, // SQDMULLv1i64_indexed
11959 493576U, // SQDMULLv2i32_indexed
11960 2056U, // SQDMULLv2i32_v2i64
11961 493576U, // SQDMULLv4i16_indexed
11962 2056U, // SQDMULLv4i16_v4i32
11963 493576U, // SQDMULLv4i32_indexed
11964 2056U, // SQDMULLv4i32_v2i64
11965 493576U, // SQDMULLv8i16_indexed
11966 2056U, // SQDMULLv8i16_v4i32
11967 0U, // SQINCB_XPiI
11968 1U, // SQINCB_XPiWdI
11969 0U, // SQINCD_XPiI
11970 1U, // SQINCD_XPiWdI
11971 0U, // SQINCD_ZPiI
11972 0U, // SQINCH_XPiI
11973 1U, // SQINCH_XPiWdI
11974 0U, // SQINCH_ZPiI
11975 21768U, // SQINCP_XPWd_B
11976 21768U, // SQINCP_XPWd_D
11977 21768U, // SQINCP_XPWd_H
11978 21768U, // SQINCP_XPWd_S
11979 6U, // SQINCP_XP_B
11980 6U, // SQINCP_XP_D
11981 6U, // SQINCP_XP_H
11982 6U, // SQINCP_XP_S
11983 6U, // SQINCP_ZP_D
11984 0U, // SQINCP_ZP_H
11985 6U, // SQINCP_ZP_S
11986 0U, // SQINCW_XPiI
11987 1U, // SQINCW_XPiWdI
11988 0U, // SQINCW_ZPiI
11989 0U, // SQNEG_ZPmZ_B
11990 2U, // SQNEG_ZPmZ_D
11991 0U, // SQNEG_ZPmZ_H
11992 4U, // SQNEG_ZPmZ_S
11993 6U, // SQNEGv16i8
11994 6U, // SQNEGv1i16
11995 6U, // SQNEGv1i32
11996 6U, // SQNEGv1i64
11997 6U, // SQNEGv1i8
11998 6U, // SQNEGv2i32
11999 6U, // SQNEGv2i64
12000 6U, // SQNEGv4i16
12001 6U, // SQNEGv4i32
12002 6U, // SQNEGv8i16
12003 6U, // SQNEGv8i8
12004 10528284U, // SQRDCMLAH_ZZZI_H
12005 76743176U, // SQRDCMLAH_ZZZI_S
12006 297728U, // SQRDCMLAH_ZZZ_B
12007 11567368U, // SQRDCMLAH_ZZZ_D
12008 297756U, // SQRDCMLAH_ZZZ_H
12009 11567624U, // SQRDCMLAH_ZZZ_S
12010 3342600U, // SQRDMLAH_ZZZI_D
12011 9756U, // SQRDMLAH_ZZZI_H
12012 3342856U, // SQRDMLAH_ZZZI_S
12013 0U, // SQRDMLAH_ZZZ_B
12014 264U, // SQRDMLAH_ZZZ_D
12015 28U, // SQRDMLAH_ZZZ_H
12016 520U, // SQRDMLAH_ZZZ_S
12017 3344648U, // SQRDMLAHi16_indexed
12018 3344648U, // SQRDMLAHi32_indexed
12019 9480U, // SQRDMLAHv1i16
12020 9480U, // SQRDMLAHv1i32
12021 2312U, // SQRDMLAHv2i32
12022 3344648U, // SQRDMLAHv2i32_indexed
12023 2312U, // SQRDMLAHv4i16
12024 3344648U, // SQRDMLAHv4i16_indexed
12025 2312U, // SQRDMLAHv4i32
12026 3344648U, // SQRDMLAHv4i32_indexed
12027 2312U, // SQRDMLAHv8i16
12028 3344648U, // SQRDMLAHv8i16_indexed
12029 3342600U, // SQRDMLSH_ZZZI_D
12030 9756U, // SQRDMLSH_ZZZI_H
12031 3342856U, // SQRDMLSH_ZZZI_S
12032 0U, // SQRDMLSH_ZZZ_B
12033 264U, // SQRDMLSH_ZZZ_D
12034 28U, // SQRDMLSH_ZZZ_H
12035 520U, // SQRDMLSH_ZZZ_S
12036 3344648U, // SQRDMLSHi16_indexed
12037 3344648U, // SQRDMLSHi32_indexed
12038 9480U, // SQRDMLSHv1i16
12039 9480U, // SQRDMLSHv1i32
12040 2312U, // SQRDMLSHv2i32
12041 3344648U, // SQRDMLSHv2i32_indexed
12042 2312U, // SQRDMLSHv4i16
12043 3344648U, // SQRDMLSHv4i16_indexed
12044 2312U, // SQRDMLSHv4i32
12045 3344648U, // SQRDMLSHv4i32_indexed
12046 2312U, // SQRDMLSHv8i16
12047 3344648U, // SQRDMLSHv8i16_indexed
12048 493064U, // SQRDMULH_ZZZI_D
12049 11022U, // SQRDMULH_ZZZI_H
12050 494600U, // SQRDMULH_ZZZI_S
12051 2568U, // SQRDMULH_ZZZ_B
12052 1544U, // SQRDMULH_ZZZ_D
12053 14U, // SQRDMULH_ZZZ_H
12054 3080U, // SQRDMULH_ZZZ_S
12055 776U, // SQRDMULHv1i16
12056 493576U, // SQRDMULHv1i16_indexed
12057 776U, // SQRDMULHv1i32
12058 493576U, // SQRDMULHv1i32_indexed
12059 2056U, // SQRDMULHv2i32
12060 493576U, // SQRDMULHv2i32_indexed
12061 2056U, // SQRDMULHv4i16
12062 493576U, // SQRDMULHv4i16_indexed
12063 2056U, // SQRDMULHv4i32
12064 493576U, // SQRDMULHv4i32_indexed
12065 2056U, // SQRDMULHv8i16
12066 493576U, // SQRDMULHv8i16_indexed
12067 1083916U, // SQRSHLR_ZPmZ_B
12068 2131468U, // SQRSHLR_ZPmZ_D
12069 3214094U, // SQRSHLR_ZPmZ_H
12070 4230156U, // SQRSHLR_ZPmZ_S
12071 1083916U, // SQRSHL_ZPmZ_B
12072 2131468U, // SQRSHL_ZPmZ_D
12073 3214094U, // SQRSHL_ZPmZ_H
12074 4230156U, // SQRSHL_ZPmZ_S
12075 2056U, // SQRSHLv16i8
12076 776U, // SQRSHLv1i16
12077 776U, // SQRSHLv1i32
12078 776U, // SQRSHLv1i64
12079 776U, // SQRSHLv1i8
12080 2056U, // SQRSHLv2i32
12081 2056U, // SQRSHLv2i64
12082 2056U, // SQRSHLv4i16
12083 2056U, // SQRSHLv4i32
12084 2056U, // SQRSHLv8i16
12085 2056U, // SQRSHLv8i8
12086 776U, // SQRSHRNB_ZZI_B
12087 22U, // SQRSHRNB_ZZI_H
12088 776U, // SQRSHRNB_ZZI_S
12089 9480U, // SQRSHRNT_ZZI_B
12090 38U, // SQRSHRNT_ZZI_H
12091 9480U, // SQRSHRNT_ZZI_S
12092 776U, // SQRSHRNb
12093 776U, // SQRSHRNh
12094 776U, // SQRSHRNs
12095 9480U, // SQRSHRNv16i8_shift
12096 776U, // SQRSHRNv2i32_shift
12097 776U, // SQRSHRNv4i16_shift
12098 9480U, // SQRSHRNv4i32_shift
12099 9480U, // SQRSHRNv8i16_shift
12100 776U, // SQRSHRNv8i8_shift
12101 776U, // SQRSHRUNB_ZZI_B
12102 22U, // SQRSHRUNB_ZZI_H
12103 776U, // SQRSHRUNB_ZZI_S
12104 9480U, // SQRSHRUNT_ZZI_B
12105 38U, // SQRSHRUNT_ZZI_H
12106 9480U, // SQRSHRUNT_ZZI_S
12107 776U, // SQRSHRUNb
12108 776U, // SQRSHRUNh
12109 776U, // SQRSHRUNs
12110 9480U, // SQRSHRUNv16i8_shift
12111 776U, // SQRSHRUNv2i32_shift
12112 776U, // SQRSHRUNv4i16_shift
12113 9480U, // SQRSHRUNv4i32_shift
12114 9480U, // SQRSHRUNv8i16_shift
12115 776U, // SQRSHRUNv8i8_shift
12116 1083916U, // SQSHLR_ZPmZ_B
12117 2131468U, // SQSHLR_ZPmZ_D
12118 3214094U, // SQSHLR_ZPmZ_H
12119 4230156U, // SQSHLR_ZPmZ_S
12120 35340U, // SQSHLU_ZPmI_B
12121 34316U, // SQSHLU_ZPmI_D
12122 133902U, // SQSHLU_ZPmI_H
12123 35852U, // SQSHLU_ZPmI_S
12124 776U, // SQSHLUb
12125 776U, // SQSHLUd
12126 776U, // SQSHLUh
12127 776U, // SQSHLUs
12128 776U, // SQSHLUv16i8_shift
12129 776U, // SQSHLUv2i32_shift
12130 776U, // SQSHLUv2i64_shift
12131 776U, // SQSHLUv4i16_shift
12132 776U, // SQSHLUv4i32_shift
12133 776U, // SQSHLUv8i16_shift
12134 776U, // SQSHLUv8i8_shift
12135 35340U, // SQSHL_ZPmI_B
12136 34316U, // SQSHL_ZPmI_D
12137 133902U, // SQSHL_ZPmI_H
12138 35852U, // SQSHL_ZPmI_S
12139 1083916U, // SQSHL_ZPmZ_B
12140 2131468U, // SQSHL_ZPmZ_D
12141 3214094U, // SQSHL_ZPmZ_H
12142 4230156U, // SQSHL_ZPmZ_S
12143 776U, // SQSHLb
12144 776U, // SQSHLd
12145 776U, // SQSHLh
12146 776U, // SQSHLs
12147 2056U, // SQSHLv16i8
12148 776U, // SQSHLv16i8_shift
12149 776U, // SQSHLv1i16
12150 776U, // SQSHLv1i32
12151 776U, // SQSHLv1i64
12152 776U, // SQSHLv1i8
12153 2056U, // SQSHLv2i32
12154 776U, // SQSHLv2i32_shift
12155 2056U, // SQSHLv2i64
12156 776U, // SQSHLv2i64_shift
12157 2056U, // SQSHLv4i16
12158 776U, // SQSHLv4i16_shift
12159 2056U, // SQSHLv4i32
12160 776U, // SQSHLv4i32_shift
12161 2056U, // SQSHLv8i16
12162 776U, // SQSHLv8i16_shift
12163 2056U, // SQSHLv8i8
12164 776U, // SQSHLv8i8_shift
12165 776U, // SQSHRNB_ZZI_B
12166 22U, // SQSHRNB_ZZI_H
12167 776U, // SQSHRNB_ZZI_S
12168 9480U, // SQSHRNT_ZZI_B
12169 38U, // SQSHRNT_ZZI_H
12170 9480U, // SQSHRNT_ZZI_S
12171 776U, // SQSHRNb
12172 776U, // SQSHRNh
12173 776U, // SQSHRNs
12174 9480U, // SQSHRNv16i8_shift
12175 776U, // SQSHRNv2i32_shift
12176 776U, // SQSHRNv4i16_shift
12177 9480U, // SQSHRNv4i32_shift
12178 9480U, // SQSHRNv8i16_shift
12179 776U, // SQSHRNv8i8_shift
12180 776U, // SQSHRUNB_ZZI_B
12181 22U, // SQSHRUNB_ZZI_H
12182 776U, // SQSHRUNB_ZZI_S
12183 9480U, // SQSHRUNT_ZZI_B
12184 38U, // SQSHRUNT_ZZI_H
12185 9480U, // SQSHRUNT_ZZI_S
12186 776U, // SQSHRUNb
12187 776U, // SQSHRUNh
12188 776U, // SQSHRUNs
12189 9480U, // SQSHRUNv16i8_shift
12190 776U, // SQSHRUNv2i32_shift
12191 776U, // SQSHRUNv4i16_shift
12192 9480U, // SQSHRUNv4i32_shift
12193 9480U, // SQSHRUNv8i16_shift
12194 776U, // SQSHRUNv8i8_shift
12195 1083916U, // SQSUBR_ZPmZ_B
12196 2131468U, // SQSUBR_ZPmZ_D
12197 3214094U, // SQSUBR_ZPmZ_H
12198 4230156U, // SQSUBR_ZPmZ_S
12199 4104U, // SQSUB_ZI_B
12200 4360U, // SQSUB_ZI_D
12201 16U, // SQSUB_ZI_H
12202 4616U, // SQSUB_ZI_S
12203 1083916U, // SQSUB_ZPmZ_B
12204 2131468U, // SQSUB_ZPmZ_D
12205 3214094U, // SQSUB_ZPmZ_H
12206 4230156U, // SQSUB_ZPmZ_S
12207 2568U, // SQSUB_ZZZ_B
12208 1544U, // SQSUB_ZZZ_D
12209 14U, // SQSUB_ZZZ_H
12210 3080U, // SQSUB_ZZZ_S
12211 2056U, // SQSUBv16i8
12212 776U, // SQSUBv1i16
12213 776U, // SQSUBv1i32
12214 776U, // SQSUBv1i64
12215 776U, // SQSUBv1i8
12216 2056U, // SQSUBv2i32
12217 2056U, // SQSUBv2i64
12218 2056U, // SQSUBv4i16
12219 2056U, // SQSUBv4i32
12220 2056U, // SQSUBv8i16
12221 2056U, // SQSUBv8i8
12222 6U, // SQXTNB_ZZ_B
12223 0U, // SQXTNB_ZZ_H
12224 6U, // SQXTNB_ZZ_S
12225 6U, // SQXTNT_ZZ_B
12226 0U, // SQXTNT_ZZ_H
12227 6U, // SQXTNT_ZZ_S
12228 6U, // SQXTNv16i8
12229 6U, // SQXTNv1i16
12230 6U, // SQXTNv1i32
12231 6U, // SQXTNv1i8
12232 6U, // SQXTNv2i32
12233 6U, // SQXTNv4i16
12234 6U, // SQXTNv4i32
12235 6U, // SQXTNv8i16
12236 6U, // SQXTNv8i8
12237 6U, // SQXTUNB_ZZ_B
12238 0U, // SQXTUNB_ZZ_H
12239 6U, // SQXTUNB_ZZ_S
12240 6U, // SQXTUNT_ZZ_B
12241 0U, // SQXTUNT_ZZ_H
12242 6U, // SQXTUNT_ZZ_S
12243 6U, // SQXTUNv16i8
12244 6U, // SQXTUNv1i16
12245 6U, // SQXTUNv1i32
12246 6U, // SQXTUNv1i8
12247 6U, // SQXTUNv2i32
12248 6U, // SQXTUNv4i16
12249 6U, // SQXTUNv4i32
12250 6U, // SQXTUNv8i16
12251 6U, // SQXTUNv8i8
12252 1083916U, // SRHADD_ZPmZ_B
12253 2131468U, // SRHADD_ZPmZ_D
12254 3214094U, // SRHADD_ZPmZ_H
12255 4230156U, // SRHADD_ZPmZ_S
12256 2056U, // SRHADDv16i8
12257 2056U, // SRHADDv2i32
12258 2056U, // SRHADDv4i16
12259 2056U, // SRHADDv4i32
12260 2056U, // SRHADDv8i16
12261 2056U, // SRHADDv8i8
12262 38U, // SRI_ZZI_B
12263 9480U, // SRI_ZZI_D
12264 38U, // SRI_ZZI_H
12265 9480U, // SRI_ZZI_S
12266 9480U, // SRId
12267 9480U, // SRIv16i8_shift
12268 9480U, // SRIv2i32_shift
12269 9480U, // SRIv2i64_shift
12270 9480U, // SRIv4i16_shift
12271 9480U, // SRIv4i32_shift
12272 9480U, // SRIv8i16_shift
12273 9480U, // SRIv8i8_shift
12274 1083916U, // SRSHLR_ZPmZ_B
12275 2131468U, // SRSHLR_ZPmZ_D
12276 3214094U, // SRSHLR_ZPmZ_H
12277 4230156U, // SRSHLR_ZPmZ_S
12278 1083916U, // SRSHL_ZPmZ_B
12279 2131468U, // SRSHL_ZPmZ_D
12280 3214094U, // SRSHL_ZPmZ_H
12281 4230156U, // SRSHL_ZPmZ_S
12282 2056U, // SRSHLv16i8
12283 776U, // SRSHLv1i64
12284 2056U, // SRSHLv2i32
12285 2056U, // SRSHLv2i64
12286 2056U, // SRSHLv4i16
12287 2056U, // SRSHLv4i32
12288 2056U, // SRSHLv8i16
12289 2056U, // SRSHLv8i8
12290 35340U, // SRSHR_ZPmI_B
12291 34316U, // SRSHR_ZPmI_D
12292 133902U, // SRSHR_ZPmI_H
12293 35852U, // SRSHR_ZPmI_S
12294 776U, // SRSHRd
12295 776U, // SRSHRv16i8_shift
12296 776U, // SRSHRv2i32_shift
12297 776U, // SRSHRv2i64_shift
12298 776U, // SRSHRv4i16_shift
12299 776U, // SRSHRv4i32_shift
12300 776U, // SRSHRv8i16_shift
12301 776U, // SRSHRv8i8_shift
12302 38U, // SRSRA_ZZI_B
12303 9480U, // SRSRA_ZZI_D
12304 38U, // SRSRA_ZZI_H
12305 9480U, // SRSRA_ZZI_S
12306 9480U, // SRSRAd
12307 9480U, // SRSRAv16i8_shift
12308 9480U, // SRSRAv2i32_shift
12309 9480U, // SRSRAv2i64_shift
12310 9480U, // SRSRAv4i16_shift
12311 9480U, // SRSRAv4i32_shift
12312 9480U, // SRSRAv8i16_shift
12313 9480U, // SRSRAv8i8_shift
12314 776U, // SSHLLB_ZZI_D
12315 22U, // SSHLLB_ZZI_H
12316 776U, // SSHLLB_ZZI_S
12317 776U, // SSHLLT_ZZI_D
12318 22U, // SSHLLT_ZZI_H
12319 776U, // SSHLLT_ZZI_S
12320 776U, // SSHLLv16i8_shift
12321 776U, // SSHLLv2i32_shift
12322 776U, // SSHLLv4i16_shift
12323 776U, // SSHLLv4i32_shift
12324 776U, // SSHLLv8i16_shift
12325 776U, // SSHLLv8i8_shift
12326 2056U, // SSHLv16i8
12327 776U, // SSHLv1i64
12328 2056U, // SSHLv2i32
12329 2056U, // SSHLv2i64
12330 2056U, // SSHLv4i16
12331 2056U, // SSHLv4i32
12332 2056U, // SSHLv8i16
12333 2056U, // SSHLv8i8
12334 776U, // SSHRd
12335 776U, // SSHRv16i8_shift
12336 776U, // SSHRv2i32_shift
12337 776U, // SSHRv2i64_shift
12338 776U, // SSHRv4i16_shift
12339 776U, // SSHRv4i32_shift
12340 776U, // SSHRv8i16_shift
12341 776U, // SSHRv8i8_shift
12342 38U, // SSRA_ZZI_B
12343 9480U, // SSRA_ZZI_D
12344 38U, // SSRA_ZZI_H
12345 9480U, // SSRA_ZZI_S
12346 9480U, // SSRAd
12347 9480U, // SSRAv16i8_shift
12348 9480U, // SSRAv2i32_shift
12349 9480U, // SSRAv2i64_shift
12350 9480U, // SSRAv4i16_shift
12351 9480U, // SSRAv4i32_shift
12352 9480U, // SSRAv8i16_shift
12353 9480U, // SSRAv8i8_shift
12354 271624U, // SST1B_D_IMM
12355 11272U, // SST1B_D_REAL
12356 11528U, // SST1B_D_SXTW
12357 11784U, // SST1B_D_UXTW
12358 271624U, // SST1B_S_IMM
12359 12040U, // SST1B_S_SXTW
12360 12296U, // SST1B_S_UXTW
12361 274696U, // SST1D_IMM
12362 11272U, // SST1D_REAL
12363 12808U, // SST1D_SCALED_SCALED_REAL
12364 11528U, // SST1D_SXTW
12365 13064U, // SST1D_SXTW_SCALED
12366 11784U, // SST1D_UXTW
12367 13320U, // SST1D_UXTW_SCALED
12368 275720U, // SST1H_D_IMM
12369 11272U, // SST1H_D_REAL
12370 13832U, // SST1H_D_SCALED_SCALED_REAL
12371 11528U, // SST1H_D_SXTW
12372 14088U, // SST1H_D_SXTW_SCALED
12373 11784U, // SST1H_D_UXTW
12374 14344U, // SST1H_D_UXTW_SCALED
12375 275720U, // SST1H_S_IMM
12376 12040U, // SST1H_S_SXTW
12377 14600U, // SST1H_S_SXTW_SCALED
12378 12296U, // SST1H_S_UXTW
12379 14856U, // SST1H_S_UXTW_SCALED
12380 277256U, // SST1W_D_IMM
12381 11272U, // SST1W_D_REAL
12382 15368U, // SST1W_D_SCALED_SCALED_REAL
12383 11528U, // SST1W_D_SXTW
12384 15624U, // SST1W_D_SXTW_SCALED
12385 11784U, // SST1W_D_UXTW
12386 15880U, // SST1W_D_UXTW_SCALED
12387 277256U, // SST1W_IMM
12388 12040U, // SST1W_SXTW
12389 16136U, // SST1W_SXTW_SCALED
12390 12296U, // SST1W_UXTW
12391 16392U, // SST1W_UXTW_SCALED
12392 3080U, // SSUBLBT_ZZZ_D
12393 66U, // SSUBLBT_ZZZ_H
12394 1288U, // SSUBLBT_ZZZ_S
12395 3080U, // SSUBLB_ZZZ_D
12396 66U, // SSUBLB_ZZZ_H
12397 1288U, // SSUBLB_ZZZ_S
12398 3080U, // SSUBLTB_ZZZ_D
12399 66U, // SSUBLTB_ZZZ_H
12400 1288U, // SSUBLTB_ZZZ_S
12401 3080U, // SSUBLT_ZZZ_D
12402 66U, // SSUBLT_ZZZ_H
12403 1288U, // SSUBLT_ZZZ_S
12404 2056U, // SSUBLv16i8_v8i16
12405 2056U, // SSUBLv2i32_v2i64
12406 2056U, // SSUBLv4i16_v4i32
12407 2056U, // SSUBLv4i32_v2i64
12408 2056U, // SSUBLv8i16_v4i32
12409 2056U, // SSUBLv8i8_v8i16
12410 3080U, // SSUBWB_ZZZ_D
12411 66U, // SSUBWB_ZZZ_H
12412 1288U, // SSUBWB_ZZZ_S
12413 3080U, // SSUBWT_ZZZ_D
12414 66U, // SSUBWT_ZZZ_H
12415 1288U, // SSUBWT_ZZZ_S
12416 2056U, // SSUBWv16i8_v8i16
12417 2056U, // SSUBWv2i32_v2i64
12418 2056U, // SSUBWv4i16_v4i32
12419 2056U, // SSUBWv4i32_v2i64
12420 2056U, // SSUBWv8i16_v4i32
12421 2056U, // SSUBWv8i8_v8i16
12422 16904U, // ST1B
12423 16904U, // ST1B_D
12424 566536U, // ST1B_D_IMM
12425 16904U, // ST1B_H
12426 566536U, // ST1B_H_IMM
12427 566536U, // ST1B_IMM
12428 16904U, // ST1B_S
12429 566536U, // ST1B_S_IMM
12430 17160U, // ST1D
12431 566536U, // ST1D_IMM
12432 0U, // ST1Fourv16b
12433 0U, // ST1Fourv16b_POST
12434 0U, // ST1Fourv1d
12435 0U, // ST1Fourv1d_POST
12436 0U, // ST1Fourv2d
12437 0U, // ST1Fourv2d_POST
12438 0U, // ST1Fourv2s
12439 0U, // ST1Fourv2s_POST
12440 0U, // ST1Fourv4h
12441 0U, // ST1Fourv4h_POST
12442 0U, // ST1Fourv4s
12443 0U, // ST1Fourv4s_POST
12444 0U, // ST1Fourv8b
12445 0U, // ST1Fourv8b_POST
12446 0U, // ST1Fourv8h
12447 0U, // ST1Fourv8h_POST
12448 17416U, // ST1H
12449 17416U, // ST1H_D
12450 566536U, // ST1H_D_IMM
12451 566536U, // ST1H_IMM
12452 17416U, // ST1H_S
12453 566536U, // ST1H_S_IMM
12454 0U, // ST1Onev16b
12455 0U, // ST1Onev16b_POST
12456 0U, // ST1Onev1d
12457 0U, // ST1Onev1d_POST
12458 0U, // ST1Onev2d
12459 0U, // ST1Onev2d_POST
12460 0U, // ST1Onev2s
12461 0U, // ST1Onev2s_POST
12462 0U, // ST1Onev4h
12463 0U, // ST1Onev4h_POST
12464 0U, // ST1Onev4s
12465 0U, // ST1Onev4s_POST
12466 0U, // ST1Onev8b
12467 0U, // ST1Onev8b_POST
12468 0U, // ST1Onev8h
12469 0U, // ST1Onev8h_POST
12470 0U, // ST1Threev16b
12471 0U, // ST1Threev16b_POST
12472 0U, // ST1Threev1d
12473 0U, // ST1Threev1d_POST
12474 0U, // ST1Threev2d
12475 0U, // ST1Threev2d_POST
12476 0U, // ST1Threev2s
12477 0U, // ST1Threev2s_POST
12478 0U, // ST1Threev4h
12479 0U, // ST1Threev4h_POST
12480 0U, // ST1Threev4s
12481 0U, // ST1Threev4s_POST
12482 0U, // ST1Threev8b
12483 0U, // ST1Threev8b_POST
12484 0U, // ST1Threev8h
12485 0U, // ST1Threev8h_POST
12486 0U, // ST1Twov16b
12487 0U, // ST1Twov16b_POST
12488 0U, // ST1Twov1d
12489 0U, // ST1Twov1d_POST
12490 0U, // ST1Twov2d
12491 0U, // ST1Twov2d_POST
12492 0U, // ST1Twov2s
12493 0U, // ST1Twov2s_POST
12494 0U, // ST1Twov4h
12495 0U, // ST1Twov4h_POST
12496 0U, // ST1Twov4s
12497 0U, // ST1Twov4s_POST
12498 0U, // ST1Twov8b
12499 0U, // ST1Twov8b_POST
12500 0U, // ST1Twov8h
12501 0U, // ST1Twov8h_POST
12502 17928U, // ST1W
12503 17928U, // ST1W_D
12504 566536U, // ST1W_D_IMM
12505 566536U, // ST1W_IMM
12506 0U, // ST1i16
12507 1U, // ST1i16_POST
12508 0U, // ST1i32
12509 1U, // ST1i32_POST
12510 0U, // ST1i64
12511 1U, // ST1i64_POST
12512 0U, // ST1i8
12513 1U, // ST1i8_POST
12514 16904U, // ST2B
12515 570632U, // ST2B_IMM
12516 17160U, // ST2D
12517 570632U, // ST2D_IMM
12518 263176U, // ST2GOffset
12519 18238U, // ST2GPostIndex
12520 640776U, // ST2GPreIndex
12521 17416U, // ST2H
12522 570632U, // ST2H_IMM
12523 0U, // ST2Twov16b
12524 0U, // ST2Twov16b_POST
12525 0U, // ST2Twov2d
12526 0U, // ST2Twov2d_POST
12527 0U, // ST2Twov2s
12528 0U, // ST2Twov2s_POST
12529 0U, // ST2Twov4h
12530 0U, // ST2Twov4h_POST
12531 0U, // ST2Twov4s
12532 0U, // ST2Twov4s_POST
12533 0U, // ST2Twov8b
12534 0U, // ST2Twov8b_POST
12535 0U, // ST2Twov8h
12536 0U, // ST2Twov8h_POST
12537 17928U, // ST2W
12538 570632U, // ST2W_IMM
12539 0U, // ST2i16
12540 1U, // ST2i16_POST
12541 0U, // ST2i32
12542 1U, // ST2i32_POST
12543 0U, // ST2i64
12544 1U, // ST2i64_POST
12545 0U, // ST2i8
12546 1U, // ST2i8_POST
12547 16904U, // ST3B
12548 18440U, // ST3B_IMM
12549 17160U, // ST3D
12550 18440U, // ST3D_IMM
12551 17416U, // ST3H
12552 18440U, // ST3H_IMM
12553 0U, // ST3Threev16b
12554 0U, // ST3Threev16b_POST
12555 0U, // ST3Threev2d
12556 0U, // ST3Threev2d_POST
12557 0U, // ST3Threev2s
12558 0U, // ST3Threev2s_POST
12559 0U, // ST3Threev4h
12560 0U, // ST3Threev4h_POST
12561 0U, // ST3Threev4s
12562 0U, // ST3Threev4s_POST
12563 0U, // ST3Threev8b
12564 0U, // ST3Threev8b_POST
12565 0U, // ST3Threev8h
12566 0U, // ST3Threev8h_POST
12567 17928U, // ST3W
12568 18440U, // ST3W_IMM
12569 0U, // ST3i16
12570 1U, // ST3i16_POST
12571 0U, // ST3i32
12572 1U, // ST3i32_POST
12573 0U, // ST3i64
12574 1U, // ST3i64_POST
12575 0U, // ST3i8
12576 1U, // ST3i8_POST
12577 16904U, // ST4B
12578 572168U, // ST4B_IMM
12579 17160U, // ST4D
12580 572168U, // ST4D_IMM
12581 0U, // ST4Fourv16b
12582 0U, // ST4Fourv16b_POST
12583 0U, // ST4Fourv2d
12584 0U, // ST4Fourv2d_POST
12585 0U, // ST4Fourv2s
12586 0U, // ST4Fourv2s_POST
12587 0U, // ST4Fourv4h
12588 0U, // ST4Fourv4h_POST
12589 0U, // ST4Fourv4s
12590 0U, // ST4Fourv4s_POST
12591 0U, // ST4Fourv8b
12592 0U, // ST4Fourv8b_POST
12593 0U, // ST4Fourv8h
12594 0U, // ST4Fourv8h_POST
12595 17416U, // ST4H
12596 572168U, // ST4H_IMM
12597 17928U, // ST4W
12598 572168U, // ST4W_IMM
12599 0U, // ST4i16
12600 1U, // ST4i16_POST
12601 0U, // ST4i32
12602 1U, // ST4i32_POST
12603 0U, // ST4i64
12604 1U, // ST4i64_POST
12605 0U, // ST4i8
12606 1U, // ST4i8_POST
12607 0U, // ST64B
12608 1U, // ST64BV
12609 1U, // ST64BV0
12610 60U, // STGM
12611 263176U, // STGOffset
12612 21005080U, // STGPi
12613 18238U, // STGPostIndex
12614 24716568U, // STGPpost
12615 292594968U, // STGPpre
12616 640776U, // STGPreIndex
12617 60U, // STLLRB
12618 60U, // STLLRH
12619 60U, // STLLRW
12620 60U, // STLLRX
12621 60U, // STLRB
12622 60U, // STLRH
12623 60U, // STLRW
12624 60U, // STLRX
12625 262920U, // STLURBi
12626 262920U, // STLURHi
12627 262920U, // STLURWi
12628 262920U, // STLURXi
12629 656136U, // STLXPW
12630 656136U, // STLXPX
12631 262936U, // STLXRB
12632 262936U, // STLXRH
12633 262936U, // STLXRW
12634 262936U, // STLXRX
12635 19956504U, // STNPDi
12636 21005080U, // STNPQi
12637 22053656U, // STNPSi
12638 22053656U, // STNPWi
12639 19956504U, // STNPXi
12640 566536U, // STNT1B_ZRI
12641 16904U, // STNT1B_ZRR
12642 271624U, // STNT1B_ZZR_D_REAL
12643 271624U, // STNT1B_ZZR_S_REAL
12644 566536U, // STNT1D_ZRI
12645 17160U, // STNT1D_ZRR
12646 271624U, // STNT1D_ZZR_D_REAL
12647 566536U, // STNT1H_ZRI
12648 17416U, // STNT1H_ZRR
12649 271624U, // STNT1H_ZZR_D_REAL
12650 271624U, // STNT1H_ZZR_S_REAL
12651 566536U, // STNT1W_ZRI
12652 17928U, // STNT1W_ZRR
12653 271624U, // STNT1W_ZZR_D_REAL
12654 271624U, // STNT1W_ZZR_S_REAL
12655 19956504U, // STPDi
12656 23667992U, // STPDpost
12657 291546392U, // STPDpre
12658 21005080U, // STPQi
12659 24716568U, // STPQpost
12660 292594968U, // STPQpre
12661 22053656U, // STPSi
12662 25765144U, // STPSpost
12663 293643544U, // STPSpre
12664 22053656U, // STPWi
12665 25765144U, // STPWpost
12666 293643544U, // STPWpre
12667 19956504U, // STPXi
12668 23667992U, // STPXpost
12669 291546392U, // STPXpre
12670 9534U, // STRBBpost
12671 632072U, // STRBBpre
12672 26247944U, // STRBBroW
12673 27296520U, // STRBBroX
12674 18952U, // STRBBui
12675 9534U, // STRBpost
12676 632072U, // STRBpre
12677 26247944U, // STRBroW
12678 27296520U, // STRBroX
12679 18952U, // STRBui
12680 9534U, // STRDpost
12681 632072U, // STRDpre
12682 28345096U, // STRDroW
12683 29393672U, // STRDroX
12684 19208U, // STRDui
12685 9534U, // STRHHpost
12686 632072U, // STRHHpre
12687 30442248U, // STRHHroW
12688 31490824U, // STRHHroX
12689 19464U, // STRHHui
12690 9534U, // STRHpost
12691 632072U, // STRHpre
12692 30442248U, // STRHroW
12693 31490824U, // STRHroX
12694 19464U, // STRHui
12695 9534U, // STRQpost
12696 632072U, // STRQpre
12697 32539400U, // STRQroW
12698 33587976U, // STRQroX
12699 19720U, // STRQui
12700 9534U, // STRSpost
12701 632072U, // STRSpre
12702 34636552U, // STRSroW
12703 35685128U, // STRSroX
12704 19976U, // STRSui
12705 9534U, // STRWpost
12706 632072U, // STRWpre
12707 34636552U, // STRWroW
12708 35685128U, // STRWroX
12709 19976U, // STRWui
12710 9534U, // STRXpost
12711 632072U, // STRXpre
12712 28345096U, // STRXroW
12713 29393672U, // STRXroX
12714 19208U, // STRXui
12715 557832U, // STR_PXI
12716 557832U, // STR_ZXI
12717 262920U, // STTRBi
12718 262920U, // STTRHi
12719 262920U, // STTRWi
12720 262920U, // STTRXi
12721 262920U, // STURBBi
12722 262920U, // STURBi
12723 262920U, // STURDi
12724 262920U, // STURHHi
12725 262920U, // STURHi
12726 262920U, // STURQi
12727 262920U, // STURSi
12728 262920U, // STURWi
12729 262920U, // STURXi
12730 656136U, // STXPW
12731 656136U, // STXPX
12732 262936U, // STXRB
12733 262936U, // STXRH
12734 262936U, // STXRW
12735 262936U, // STXRX
12736 263176U, // STZ2GOffset
12737 18238U, // STZ2GPostIndex
12738 640776U, // STZ2GPreIndex
12739 60U, // STZGM
12740 263176U, // STZGOffset
12741 18238U, // STZGPostIndex
12742 640776U, // STZGPreIndex
12743 33800U, // SUBG
12744 1288U, // SUBHNB_ZZZ_B
12745 10U, // SUBHNB_ZZZ_H
12746 1544U, // SUBHNB_ZZZ_S
12747 1800U, // SUBHNT_ZZZ_B
12748 4U, // SUBHNT_ZZZ_H
12749 264U, // SUBHNT_ZZZ_S
12750 2056U, // SUBHNv2i64_v2i32
12751 2312U, // SUBHNv2i64_v4i32
12752 2056U, // SUBHNv4i32_v4i16
12753 2312U, // SUBHNv4i32_v8i16
12754 2312U, // SUBHNv8i16_v16i8
12755 2056U, // SUBHNv8i16_v8i8
12756 776U, // SUBP
12757 776U, // SUBPS
12758 4104U, // SUBR_ZI_B
12759 4360U, // SUBR_ZI_D
12760 16U, // SUBR_ZI_H
12761 4616U, // SUBR_ZI_S
12762 1083916U, // SUBR_ZPmZ_B
12763 2131468U, // SUBR_ZPmZ_D
12764 3214094U, // SUBR_ZPmZ_H
12765 4230156U, // SUBR_ZPmZ_S
12766 3336U, // SUBSWri
12767 3592U, // SUBSWrs
12768 3848U, // SUBSWrx
12769 3336U, // SUBSXri
12770 3592U, // SUBSXrs
12771 3848U, // SUBSXrx
12772 99080U, // SUBSXrx64
12773 3336U, // SUBWri
12774 3592U, // SUBWrs
12775 3848U, // SUBWrx
12776 3336U, // SUBXri
12777 3592U, // SUBXrs
12778 3848U, // SUBXrx
12779 99080U, // SUBXrx64
12780 4104U, // SUB_ZI_B
12781 4360U, // SUB_ZI_D
12782 16U, // SUB_ZI_H
12783 4616U, // SUB_ZI_S
12784 1083916U, // SUB_ZPmZ_B
12785 2131468U, // SUB_ZPmZ_D
12786 3214094U, // SUB_ZPmZ_H
12787 4230156U, // SUB_ZPmZ_S
12788 2568U, // SUB_ZZZ_B
12789 1544U, // SUB_ZZZ_D
12790 14U, // SUB_ZZZ_H
12791 3080U, // SUB_ZZZ_S
12792 2056U, // SUBv16i8
12793 776U, // SUBv1i64
12794 2056U, // SUBv2i32
12795 2056U, // SUBv2i64
12796 2056U, // SUBv4i16
12797 2056U, // SUBv4i32
12798 2056U, // SUBv8i16
12799 2056U, // SUBv8i8
12800 9728U, // SUDOT_ZZZI
12801 3344648U, // SUDOTlanev16i8
12802 3344648U, // SUDOTlanev8i8
12803 6U, // SUNPKHI_ZZ_D
12804 0U, // SUNPKHI_ZZ_H
12805 6U, // SUNPKHI_ZZ_S
12806 6U, // SUNPKLO_ZZ_D
12807 0U, // SUNPKLO_ZZ_H
12808 6U, // SUNPKLO_ZZ_S
12809 1083916U, // SUQADD_ZPmZ_B
12810 2131468U, // SUQADD_ZPmZ_D
12811 3214094U, // SUQADD_ZPmZ_H
12812 4230156U, // SUQADD_ZPmZ_S
12813 6U, // SUQADDv16i8
12814 6U, // SUQADDv1i16
12815 6U, // SUQADDv1i32
12816 6U, // SUQADDv1i64
12817 6U, // SUQADDv1i8
12818 6U, // SUQADDv2i32
12819 6U, // SUQADDv2i64
12820 6U, // SUQADDv4i16
12821 6U, // SUQADDv4i32
12822 6U, // SUQADDv8i16
12823 6U, // SUQADDv8i8
12824 0U, // SVC
12825 1U, // SWPAB
12826 1U, // SWPAH
12827 1U, // SWPALB
12828 1U, // SWPALH
12829 1U, // SWPALW
12830 1U, // SWPALX
12831 1U, // SWPAW
12832 1U, // SWPAX
12833 1U, // SWPB
12834 1U, // SWPH
12835 1U, // SWPLB
12836 1U, // SWPLH
12837 1U, // SWPLW
12838 1U, // SWPLX
12839 1U, // SWPW
12840 1U, // SWPX
12841 2U, // SXTB_ZPmZ_D
12842 0U, // SXTB_ZPmZ_H
12843 4U, // SXTB_ZPmZ_S
12844 2U, // SXTH_ZPmZ_D
12845 4U, // SXTH_ZPmZ_S
12846 2U, // SXTW_ZPmZ_D
12847 22024U, // SYSLxt
12848 1U, // SYSxt
12849 67U, // TBL_ZZZZ_B
12850 1U, // TBL_ZZZZ_D
12851 0U, // TBL_ZZZZ_H
12852 1U, // TBL_ZZZZ_S
12853 67U, // TBL_ZZZ_B
12854 1U, // TBL_ZZZ_D
12855 0U, // TBL_ZZZ_H
12856 1U, // TBL_ZZZ_S
12857 133U, // TBLv16i8Four
12858 133U, // TBLv16i8One
12859 133U, // TBLv16i8Three
12860 133U, // TBLv16i8Two
12861 135U, // TBLv8i8Four
12862 135U, // TBLv8i8One
12863 135U, // TBLv8i8Three
12864 135U, // TBLv8i8Two
12865 22280U, // TBNZW
12866 22280U, // TBNZX
12867 0U, // TBX_ZZZ_B
12868 264U, // TBX_ZZZ_D
12869 28U, // TBX_ZZZ_H
12870 520U, // TBX_ZZZ_S
12871 133U, // TBXv16i8Four
12872 133U, // TBXv16i8One
12873 133U, // TBXv16i8Three
12874 133U, // TBXv16i8Two
12875 135U, // TBXv8i8Four
12876 135U, // TBXv8i8One
12877 135U, // TBXv8i8Three
12878 135U, // TBXv8i8Two
12879 22280U, // TBZW
12880 22280U, // TBZX
12881 0U, // TCANCEL
12882 0U, // TCOMMIT
12883 2568U, // TRN1_PPP_B
12884 1544U, // TRN1_PPP_D
12885 14U, // TRN1_PPP_H
12886 3080U, // TRN1_PPP_S
12887 2568U, // TRN1_ZZZ_B
12888 1544U, // TRN1_ZZZ_D
12889 14U, // TRN1_ZZZ_H
12890 136U, // TRN1_ZZZ_Q
12891 3080U, // TRN1_ZZZ_S
12892 2056U, // TRN1v16i8
12893 2056U, // TRN1v2i32
12894 2056U, // TRN1v2i64
12895 2056U, // TRN1v4i16
12896 2056U, // TRN1v4i32
12897 2056U, // TRN1v8i16
12898 2056U, // TRN1v8i8
12899 2568U, // TRN2_PPP_B
12900 1544U, // TRN2_PPP_D
12901 14U, // TRN2_PPP_H
12902 3080U, // TRN2_PPP_S
12903 2568U, // TRN2_ZZZ_B
12904 1544U, // TRN2_ZZZ_D
12905 14U, // TRN2_ZZZ_H
12906 136U, // TRN2_ZZZ_Q
12907 3080U, // TRN2_ZZZ_S
12908 2056U, // TRN2v16i8
12909 2056U, // TRN2v2i32
12910 2056U, // TRN2v2i64
12911 2056U, // TRN2v4i16
12912 2056U, // TRN2v4i32
12913 2056U, // TRN2v8i16
12914 2056U, // TRN2v8i8
12915 0U, // TSB
12916 0U, // TSTART
12917 0U, // TTEST
12918 520U, // UABALB_ZZZ_D
12919 0U, // UABALB_ZZZ_H
12920 1800U, // UABALB_ZZZ_S
12921 520U, // UABALT_ZZZ_D
12922 0U, // UABALT_ZZZ_H
12923 1800U, // UABALT_ZZZ_S
12924 2312U, // UABALv16i8_v8i16
12925 2312U, // UABALv2i32_v2i64
12926 2312U, // UABALv4i16_v4i32
12927 2312U, // UABALv4i32_v2i64
12928 2312U, // UABALv8i16_v4i32
12929 2312U, // UABALv8i8_v8i16
12930 0U, // UABA_ZZZ_B
12931 264U, // UABA_ZZZ_D
12932 28U, // UABA_ZZZ_H
12933 520U, // UABA_ZZZ_S
12934 2312U, // UABAv16i8
12935 2312U, // UABAv2i32
12936 2312U, // UABAv4i16
12937 2312U, // UABAv4i32
12938 2312U, // UABAv8i16
12939 2312U, // UABAv8i8
12940 3080U, // UABDLB_ZZZ_D
12941 66U, // UABDLB_ZZZ_H
12942 1288U, // UABDLB_ZZZ_S
12943 3080U, // UABDLT_ZZZ_D
12944 66U, // UABDLT_ZZZ_H
12945 1288U, // UABDLT_ZZZ_S
12946 2056U, // UABDLv16i8_v8i16
12947 2056U, // UABDLv2i32_v2i64
12948 2056U, // UABDLv4i16_v4i32
12949 2056U, // UABDLv4i32_v2i64
12950 2056U, // UABDLv8i16_v4i32
12951 2056U, // UABDLv8i8_v8i16
12952 1083916U, // UABD_ZPmZ_B
12953 2131468U, // UABD_ZPmZ_D
12954 3214094U, // UABD_ZPmZ_H
12955 4230156U, // UABD_ZPmZ_S
12956 2056U, // UABDv16i8
12957 2056U, // UABDv2i32
12958 2056U, // UABDv4i16
12959 2056U, // UABDv4i32
12960 2056U, // UABDv8i16
12961 2056U, // UABDv8i8
12962 524U, // UADALP_ZPmZ_D
12963 0U, // UADALP_ZPmZ_H
12964 1804U, // UADALP_ZPmZ_S
12965 6U, // UADALPv16i8_v8i16
12966 6U, // UADALPv2i32_v1i64
12967 6U, // UADALPv4i16_v2i32
12968 6U, // UADALPv4i32_v2i64
12969 6U, // UADALPv8i16_v4i32
12970 6U, // UADALPv8i8_v4i16
12971 3080U, // UADDLB_ZZZ_D
12972 66U, // UADDLB_ZZZ_H
12973 1288U, // UADDLB_ZZZ_S
12974 6U, // UADDLPv16i8_v8i16
12975 6U, // UADDLPv2i32_v1i64
12976 6U, // UADDLPv4i16_v2i32
12977 6U, // UADDLPv4i32_v2i64
12978 6U, // UADDLPv8i16_v4i32
12979 6U, // UADDLPv8i8_v4i16
12980 3080U, // UADDLT_ZZZ_D
12981 66U, // UADDLT_ZZZ_H
12982 1288U, // UADDLT_ZZZ_S
12983 6U, // UADDLVv16i8v
12984 6U, // UADDLVv4i16v
12985 6U, // UADDLVv4i32v
12986 6U, // UADDLVv8i16v
12987 6U, // UADDLVv8i8v
12988 2056U, // UADDLv16i8_v8i16
12989 2056U, // UADDLv2i32_v2i64
12990 2056U, // UADDLv4i16_v4i32
12991 2056U, // UADDLv4i32_v2i64
12992 2056U, // UADDLv8i16_v4i32
12993 2056U, // UADDLv8i8_v8i16
12994 0U, // UADDV_VPZ_B
12995 0U, // UADDV_VPZ_D
12996 0U, // UADDV_VPZ_H
12997 0U, // UADDV_VPZ_S
12998 3080U, // UADDWB_ZZZ_D
12999 66U, // UADDWB_ZZZ_H
13000 1288U, // UADDWB_ZZZ_S
13001 3080U, // UADDWT_ZZZ_D
13002 66U, // UADDWT_ZZZ_H
13003 1288U, // UADDWT_ZZZ_S
13004 2056U, // UADDWv16i8_v8i16
13005 2056U, // UADDWv2i32_v2i64
13006 2056U, // UADDWv4i16_v4i32
13007 2056U, // UADDWv4i32_v2i64
13008 2056U, // UADDWv8i16_v4i32
13009 2056U, // UADDWv8i8_v8i16
13010 33544U, // UBFMWri
13011 33544U, // UBFMXri
13012 776U, // UCVTFSWDri
13013 776U, // UCVTFSWHri
13014 776U, // UCVTFSWSri
13015 776U, // UCVTFSXDri
13016 776U, // UCVTFSXHri
13017 776U, // UCVTFSXSri
13018 6U, // UCVTFUWDri
13019 6U, // UCVTFUWHri
13020 6U, // UCVTFUWSri
13021 6U, // UCVTFUXDri
13022 6U, // UCVTFUXHri
13023 6U, // UCVTFUXSri
13024 2U, // UCVTF_ZPmZ_DtoD
13025 1U, // UCVTF_ZPmZ_DtoH
13026 2U, // UCVTF_ZPmZ_DtoS
13027 0U, // UCVTF_ZPmZ_HtoH
13028 4U, // UCVTF_ZPmZ_StoD
13029 0U, // UCVTF_ZPmZ_StoH
13030 4U, // UCVTF_ZPmZ_StoS
13031 776U, // UCVTFd
13032 776U, // UCVTFh
13033 776U, // UCVTFs
13034 6U, // UCVTFv1i16
13035 6U, // UCVTFv1i32
13036 6U, // UCVTFv1i64
13037 6U, // UCVTFv2f32
13038 6U, // UCVTFv2f64
13039 776U, // UCVTFv2i32_shift
13040 776U, // UCVTFv2i64_shift
13041 6U, // UCVTFv4f16
13042 6U, // UCVTFv4f32
13043 776U, // UCVTFv4i16_shift
13044 776U, // UCVTFv4i32_shift
13045 6U, // UCVTFv8f16
13046 776U, // UCVTFv8i16_shift
13047 0U, // UDF
13048 2131468U, // UDIVR_ZPmZ_D
13049 4230156U, // UDIVR_ZPmZ_S
13050 776U, // UDIVWr
13051 776U, // UDIVXr
13052 2131468U, // UDIV_ZPmZ_D
13053 4230156U, // UDIV_ZPmZ_S
13054 3344136U, // UDOT_ZZZI_D
13055 9728U, // UDOT_ZZZI_S
13056 1800U, // UDOT_ZZZ_D
13057 0U, // UDOT_ZZZ_S
13058 3344648U, // UDOTlanev16i8
13059 3344648U, // UDOTlanev8i8
13060 0U, // UDOTv16i8
13061 0U, // UDOTv8i8
13062 1083916U, // UHADD_ZPmZ_B
13063 2131468U, // UHADD_ZPmZ_D
13064 3214094U, // UHADD_ZPmZ_H
13065 4230156U, // UHADD_ZPmZ_S
13066 2056U, // UHADDv16i8
13067 2056U, // UHADDv2i32
13068 2056U, // UHADDv4i16
13069 2056U, // UHADDv4i32
13070 2056U, // UHADDv8i16
13071 2056U, // UHADDv8i8
13072 1083916U, // UHSUBR_ZPmZ_B
13073 2131468U, // UHSUBR_ZPmZ_D
13074 3214094U, // UHSUBR_ZPmZ_H
13075 4230156U, // UHSUBR_ZPmZ_S
13076 1083916U, // UHSUB_ZPmZ_B
13077 2131468U, // UHSUB_ZPmZ_D
13078 3214094U, // UHSUB_ZPmZ_H
13079 4230156U, // UHSUB_ZPmZ_S
13080 2056U, // UHSUBv16i8
13081 2056U, // UHSUBv2i32
13082 2056U, // UHSUBv4i16
13083 2056U, // UHSUBv4i32
13084 2056U, // UHSUBv8i16
13085 2056U, // UHSUBv8i8
13086 33544U, // UMADDLrrr
13087 1083916U, // UMAXP_ZPmZ_B
13088 2131468U, // UMAXP_ZPmZ_D
13089 3214094U, // UMAXP_ZPmZ_H
13090 4230156U, // UMAXP_ZPmZ_S
13091 2056U, // UMAXPv16i8
13092 2056U, // UMAXPv2i32
13093 2056U, // UMAXPv4i16
13094 2056U, // UMAXPv4i32
13095 2056U, // UMAXPv8i16
13096 2056U, // UMAXPv8i8
13097 0U, // UMAXV_VPZ_B
13098 0U, // UMAXV_VPZ_D
13099 0U, // UMAXV_VPZ_H
13100 0U, // UMAXV_VPZ_S
13101 6U, // UMAXVv16i8v
13102 6U, // UMAXVv4i16v
13103 6U, // UMAXVv4i32v
13104 6U, // UMAXVv8i16v
13105 6U, // UMAXVv8i8v
13106 22536U, // UMAX_ZI_B
13107 22536U, // UMAX_ZI_D
13108 44U, // UMAX_ZI_H
13109 22536U, // UMAX_ZI_S
13110 1083916U, // UMAX_ZPmZ_B
13111 2131468U, // UMAX_ZPmZ_D
13112 3214094U, // UMAX_ZPmZ_H
13113 4230156U, // UMAX_ZPmZ_S
13114 2056U, // UMAXv16i8
13115 2056U, // UMAXv2i32
13116 2056U, // UMAXv4i16
13117 2056U, // UMAXv4i32
13118 2056U, // UMAXv8i16
13119 2056U, // UMAXv8i8
13120 1083916U, // UMINP_ZPmZ_B
13121 2131468U, // UMINP_ZPmZ_D
13122 3214094U, // UMINP_ZPmZ_H
13123 4230156U, // UMINP_ZPmZ_S
13124 2056U, // UMINPv16i8
13125 2056U, // UMINPv2i32
13126 2056U, // UMINPv4i16
13127 2056U, // UMINPv4i32
13128 2056U, // UMINPv8i16
13129 2056U, // UMINPv8i8
13130 0U, // UMINV_VPZ_B
13131 0U, // UMINV_VPZ_D
13132 0U, // UMINV_VPZ_H
13133 0U, // UMINV_VPZ_S
13134 6U, // UMINVv16i8v
13135 6U, // UMINVv4i16v
13136 6U, // UMINVv4i32v
13137 6U, // UMINVv8i16v
13138 6U, // UMINVv8i8v
13139 22536U, // UMIN_ZI_B
13140 22536U, // UMIN_ZI_D
13141 44U, // UMIN_ZI_H
13142 22536U, // UMIN_ZI_S
13143 1083916U, // UMIN_ZPmZ_B
13144 2131468U, // UMIN_ZPmZ_D
13145 3214094U, // UMIN_ZPmZ_H
13146 4230156U, // UMIN_ZPmZ_S
13147 2056U, // UMINv16i8
13148 2056U, // UMINv2i32
13149 2056U, // UMINv4i16
13150 2056U, // UMINv4i32
13151 2056U, // UMINv8i16
13152 2056U, // UMINv8i8
13153 3342856U, // UMLALB_ZZZI_D
13154 3344136U, // UMLALB_ZZZI_S
13155 520U, // UMLALB_ZZZ_D
13156 0U, // UMLALB_ZZZ_H
13157 1800U, // UMLALB_ZZZ_S
13158 3342856U, // UMLALT_ZZZI_D
13159 3344136U, // UMLALT_ZZZI_S
13160 520U, // UMLALT_ZZZ_D
13161 0U, // UMLALT_ZZZ_H
13162 1800U, // UMLALT_ZZZ_S
13163 2312U, // UMLALv16i8_v8i16
13164 3344648U, // UMLALv2i32_indexed
13165 2312U, // UMLALv2i32_v2i64
13166 3344648U, // UMLALv4i16_indexed
13167 2312U, // UMLALv4i16_v4i32
13168 3344648U, // UMLALv4i32_indexed
13169 2312U, // UMLALv4i32_v2i64
13170 3344648U, // UMLALv8i16_indexed
13171 2312U, // UMLALv8i16_v4i32
13172 2312U, // UMLALv8i8_v8i16
13173 3342856U, // UMLSLB_ZZZI_D
13174 3344136U, // UMLSLB_ZZZI_S
13175 520U, // UMLSLB_ZZZ_D
13176 0U, // UMLSLB_ZZZ_H
13177 1800U, // UMLSLB_ZZZ_S
13178 3342856U, // UMLSLT_ZZZI_D
13179 3344136U, // UMLSLT_ZZZI_S
13180 520U, // UMLSLT_ZZZ_D
13181 0U, // UMLSLT_ZZZ_H
13182 1800U, // UMLSLT_ZZZ_S
13183 2312U, // UMLSLv16i8_v8i16
13184 3344648U, // UMLSLv2i32_indexed
13185 2312U, // UMLSLv2i32_v2i64
13186 3344648U, // UMLSLv4i16_indexed
13187 2312U, // UMLSLv4i16_v4i32
13188 3344648U, // UMLSLv4i32_indexed
13189 2312U, // UMLSLv4i32_v2i64
13190 3344648U, // UMLSLv8i16_indexed
13191 2312U, // UMLSLv8i16_v4i32
13192 2312U, // UMLSLv8i8_v8i16
13193 0U, // UMMLA
13194 0U, // UMMLA_ZZZ
13195 42U, // UMOVvi16
13196 42U, // UMOVvi32
13197 42U, // UMOVvi64
13198 42U, // UMOVvi8
13199 33544U, // UMSUBLrrr
13200 1083916U, // UMULH_ZPmZ_B
13201 2131468U, // UMULH_ZPmZ_D
13202 3214094U, // UMULH_ZPmZ_H
13203 4230156U, // UMULH_ZPmZ_S
13204 2568U, // UMULH_ZZZ_B
13205 1544U, // UMULH_ZZZ_D
13206 14U, // UMULH_ZZZ_H
13207 3080U, // UMULH_ZZZ_S
13208 776U, // UMULHrr
13209 494600U, // UMULLB_ZZZI_D
13210 492808U, // UMULLB_ZZZI_S
13211 3080U, // UMULLB_ZZZ_D
13212 66U, // UMULLB_ZZZ_H
13213 1288U, // UMULLB_ZZZ_S
13214 494600U, // UMULLT_ZZZI_D
13215 492808U, // UMULLT_ZZZI_S
13216 3080U, // UMULLT_ZZZ_D
13217 66U, // UMULLT_ZZZ_H
13218 1288U, // UMULLT_ZZZ_S
13219 2056U, // UMULLv16i8_v8i16
13220 493576U, // UMULLv2i32_indexed
13221 2056U, // UMULLv2i32_v2i64
13222 493576U, // UMULLv4i16_indexed
13223 2056U, // UMULLv4i16_v4i32
13224 493576U, // UMULLv4i32_indexed
13225 2056U, // UMULLv4i32_v2i64
13226 493576U, // UMULLv8i16_indexed
13227 2056U, // UMULLv8i16_v4i32
13228 2056U, // UMULLv8i8_v8i16
13229 4104U, // UQADD_ZI_B
13230 4360U, // UQADD_ZI_D
13231 16U, // UQADD_ZI_H
13232 4616U, // UQADD_ZI_S
13233 1083916U, // UQADD_ZPmZ_B
13234 2131468U, // UQADD_ZPmZ_D
13235 3214094U, // UQADD_ZPmZ_H
13236 4230156U, // UQADD_ZPmZ_S
13237 2568U, // UQADD_ZZZ_B
13238 1544U, // UQADD_ZZZ_D
13239 14U, // UQADD_ZZZ_H
13240 3080U, // UQADD_ZZZ_S
13241 2056U, // UQADDv16i8
13242 776U, // UQADDv1i16
13243 776U, // UQADDv1i32
13244 776U, // UQADDv1i64
13245 776U, // UQADDv1i8
13246 2056U, // UQADDv2i32
13247 2056U, // UQADDv2i64
13248 2056U, // UQADDv4i16
13249 2056U, // UQADDv4i32
13250 2056U, // UQADDv8i16
13251 2056U, // UQADDv8i8
13252 0U, // UQDECB_WPiI
13253 0U, // UQDECB_XPiI
13254 0U, // UQDECD_WPiI
13255 0U, // UQDECD_XPiI
13256 0U, // UQDECD_ZPiI
13257 0U, // UQDECH_WPiI
13258 0U, // UQDECH_XPiI
13259 0U, // UQDECH_ZPiI
13260 6U, // UQDECP_WP_B
13261 6U, // UQDECP_WP_D
13262 6U, // UQDECP_WP_H
13263 6U, // UQDECP_WP_S
13264 6U, // UQDECP_XP_B
13265 6U, // UQDECP_XP_D
13266 6U, // UQDECP_XP_H
13267 6U, // UQDECP_XP_S
13268 6U, // UQDECP_ZP_D
13269 0U, // UQDECP_ZP_H
13270 6U, // UQDECP_ZP_S
13271 0U, // UQDECW_WPiI
13272 0U, // UQDECW_XPiI
13273 0U, // UQDECW_ZPiI
13274 0U, // UQINCB_WPiI
13275 0U, // UQINCB_XPiI
13276 0U, // UQINCD_WPiI
13277 0U, // UQINCD_XPiI
13278 0U, // UQINCD_ZPiI
13279 0U, // UQINCH_WPiI
13280 0U, // UQINCH_XPiI
13281 0U, // UQINCH_ZPiI
13282 6U, // UQINCP_WP_B
13283 6U, // UQINCP_WP_D
13284 6U, // UQINCP_WP_H
13285 6U, // UQINCP_WP_S
13286 6U, // UQINCP_XP_B
13287 6U, // UQINCP_XP_D
13288 6U, // UQINCP_XP_H
13289 6U, // UQINCP_XP_S
13290 6U, // UQINCP_ZP_D
13291 0U, // UQINCP_ZP_H
13292 6U, // UQINCP_ZP_S
13293 0U, // UQINCW_WPiI
13294 0U, // UQINCW_XPiI
13295 0U, // UQINCW_ZPiI
13296 1083916U, // UQRSHLR_ZPmZ_B
13297 2131468U, // UQRSHLR_ZPmZ_D
13298 3214094U, // UQRSHLR_ZPmZ_H
13299 4230156U, // UQRSHLR_ZPmZ_S
13300 1083916U, // UQRSHL_ZPmZ_B
13301 2131468U, // UQRSHL_ZPmZ_D
13302 3214094U, // UQRSHL_ZPmZ_H
13303 4230156U, // UQRSHL_ZPmZ_S
13304 2056U, // UQRSHLv16i8
13305 776U, // UQRSHLv1i16
13306 776U, // UQRSHLv1i32
13307 776U, // UQRSHLv1i64
13308 776U, // UQRSHLv1i8
13309 2056U, // UQRSHLv2i32
13310 2056U, // UQRSHLv2i64
13311 2056U, // UQRSHLv4i16
13312 2056U, // UQRSHLv4i32
13313 2056U, // UQRSHLv8i16
13314 2056U, // UQRSHLv8i8
13315 776U, // UQRSHRNB_ZZI_B
13316 22U, // UQRSHRNB_ZZI_H
13317 776U, // UQRSHRNB_ZZI_S
13318 9480U, // UQRSHRNT_ZZI_B
13319 38U, // UQRSHRNT_ZZI_H
13320 9480U, // UQRSHRNT_ZZI_S
13321 776U, // UQRSHRNb
13322 776U, // UQRSHRNh
13323 776U, // UQRSHRNs
13324 9480U, // UQRSHRNv16i8_shift
13325 776U, // UQRSHRNv2i32_shift
13326 776U, // UQRSHRNv4i16_shift
13327 9480U, // UQRSHRNv4i32_shift
13328 9480U, // UQRSHRNv8i16_shift
13329 776U, // UQRSHRNv8i8_shift
13330 1083916U, // UQSHLR_ZPmZ_B
13331 2131468U, // UQSHLR_ZPmZ_D
13332 3214094U, // UQSHLR_ZPmZ_H
13333 4230156U, // UQSHLR_ZPmZ_S
13334 35340U, // UQSHL_ZPmI_B
13335 34316U, // UQSHL_ZPmI_D
13336 133902U, // UQSHL_ZPmI_H
13337 35852U, // UQSHL_ZPmI_S
13338 1083916U, // UQSHL_ZPmZ_B
13339 2131468U, // UQSHL_ZPmZ_D
13340 3214094U, // UQSHL_ZPmZ_H
13341 4230156U, // UQSHL_ZPmZ_S
13342 776U, // UQSHLb
13343 776U, // UQSHLd
13344 776U, // UQSHLh
13345 776U, // UQSHLs
13346 2056U, // UQSHLv16i8
13347 776U, // UQSHLv16i8_shift
13348 776U, // UQSHLv1i16
13349 776U, // UQSHLv1i32
13350 776U, // UQSHLv1i64
13351 776U, // UQSHLv1i8
13352 2056U, // UQSHLv2i32
13353 776U, // UQSHLv2i32_shift
13354 2056U, // UQSHLv2i64
13355 776U, // UQSHLv2i64_shift
13356 2056U, // UQSHLv4i16
13357 776U, // UQSHLv4i16_shift
13358 2056U, // UQSHLv4i32
13359 776U, // UQSHLv4i32_shift
13360 2056U, // UQSHLv8i16
13361 776U, // UQSHLv8i16_shift
13362 2056U, // UQSHLv8i8
13363 776U, // UQSHLv8i8_shift
13364 776U, // UQSHRNB_ZZI_B
13365 22U, // UQSHRNB_ZZI_H
13366 776U, // UQSHRNB_ZZI_S
13367 9480U, // UQSHRNT_ZZI_B
13368 38U, // UQSHRNT_ZZI_H
13369 9480U, // UQSHRNT_ZZI_S
13370 776U, // UQSHRNb
13371 776U, // UQSHRNh
13372 776U, // UQSHRNs
13373 9480U, // UQSHRNv16i8_shift
13374 776U, // UQSHRNv2i32_shift
13375 776U, // UQSHRNv4i16_shift
13376 9480U, // UQSHRNv4i32_shift
13377 9480U, // UQSHRNv8i16_shift
13378 776U, // UQSHRNv8i8_shift
13379 1083916U, // UQSUBR_ZPmZ_B
13380 2131468U, // UQSUBR_ZPmZ_D
13381 3214094U, // UQSUBR_ZPmZ_H
13382 4230156U, // UQSUBR_ZPmZ_S
13383 4104U, // UQSUB_ZI_B
13384 4360U, // UQSUB_ZI_D
13385 16U, // UQSUB_ZI_H
13386 4616U, // UQSUB_ZI_S
13387 1083916U, // UQSUB_ZPmZ_B
13388 2131468U, // UQSUB_ZPmZ_D
13389 3214094U, // UQSUB_ZPmZ_H
13390 4230156U, // UQSUB_ZPmZ_S
13391 2568U, // UQSUB_ZZZ_B
13392 1544U, // UQSUB_ZZZ_D
13393 14U, // UQSUB_ZZZ_H
13394 3080U, // UQSUB_ZZZ_S
13395 2056U, // UQSUBv16i8
13396 776U, // UQSUBv1i16
13397 776U, // UQSUBv1i32
13398 776U, // UQSUBv1i64
13399 776U, // UQSUBv1i8
13400 2056U, // UQSUBv2i32
13401 2056U, // UQSUBv2i64
13402 2056U, // UQSUBv4i16
13403 2056U, // UQSUBv4i32
13404 2056U, // UQSUBv8i16
13405 2056U, // UQSUBv8i8
13406 6U, // UQXTNB_ZZ_B
13407 0U, // UQXTNB_ZZ_H
13408 6U, // UQXTNB_ZZ_S
13409 6U, // UQXTNT_ZZ_B
13410 0U, // UQXTNT_ZZ_H
13411 6U, // UQXTNT_ZZ_S
13412 6U, // UQXTNv16i8
13413 6U, // UQXTNv1i16
13414 6U, // UQXTNv1i32
13415 6U, // UQXTNv1i8
13416 6U, // UQXTNv2i32
13417 6U, // UQXTNv4i16
13418 6U, // UQXTNv4i32
13419 6U, // UQXTNv8i16
13420 6U, // UQXTNv8i8
13421 4U, // URECPE_ZPmZ_S
13422 6U, // URECPEv2i32
13423 6U, // URECPEv4i32
13424 1083916U, // URHADD_ZPmZ_B
13425 2131468U, // URHADD_ZPmZ_D
13426 3214094U, // URHADD_ZPmZ_H
13427 4230156U, // URHADD_ZPmZ_S
13428 2056U, // URHADDv16i8
13429 2056U, // URHADDv2i32
13430 2056U, // URHADDv4i16
13431 2056U, // URHADDv4i32
13432 2056U, // URHADDv8i16
13433 2056U, // URHADDv8i8
13434 1083916U, // URSHLR_ZPmZ_B
13435 2131468U, // URSHLR_ZPmZ_D
13436 3214094U, // URSHLR_ZPmZ_H
13437 4230156U, // URSHLR_ZPmZ_S
13438 1083916U, // URSHL_ZPmZ_B
13439 2131468U, // URSHL_ZPmZ_D
13440 3214094U, // URSHL_ZPmZ_H
13441 4230156U, // URSHL_ZPmZ_S
13442 2056U, // URSHLv16i8
13443 776U, // URSHLv1i64
13444 2056U, // URSHLv2i32
13445 2056U, // URSHLv2i64
13446 2056U, // URSHLv4i16
13447 2056U, // URSHLv4i32
13448 2056U, // URSHLv8i16
13449 2056U, // URSHLv8i8
13450 35340U, // URSHR_ZPmI_B
13451 34316U, // URSHR_ZPmI_D
13452 133902U, // URSHR_ZPmI_H
13453 35852U, // URSHR_ZPmI_S
13454 776U, // URSHRd
13455 776U, // URSHRv16i8_shift
13456 776U, // URSHRv2i32_shift
13457 776U, // URSHRv2i64_shift
13458 776U, // URSHRv4i16_shift
13459 776U, // URSHRv4i32_shift
13460 776U, // URSHRv8i16_shift
13461 776U, // URSHRv8i8_shift
13462 4U, // URSQRTE_ZPmZ_S
13463 6U, // URSQRTEv2i32
13464 6U, // URSQRTEv4i32
13465 38U, // URSRA_ZZI_B
13466 9480U, // URSRA_ZZI_D
13467 38U, // URSRA_ZZI_H
13468 9480U, // URSRA_ZZI_S
13469 9480U, // URSRAd
13470 9480U, // URSRAv16i8_shift
13471 9480U, // URSRAv2i32_shift
13472 9480U, // URSRAv2i64_shift
13473 9480U, // URSRAv4i16_shift
13474 9480U, // URSRAv4i32_shift
13475 9480U, // URSRAv8i16_shift
13476 9480U, // URSRAv8i8_shift
13477 0U, // USDOT_ZZZ
13478 9728U, // USDOT_ZZZI
13479 3344648U, // USDOTlanev16i8
13480 3344648U, // USDOTlanev8i8
13481 0U, // USDOTv16i8
13482 0U, // USDOTv8i8
13483 776U, // USHLLB_ZZI_D
13484 22U, // USHLLB_ZZI_H
13485 776U, // USHLLB_ZZI_S
13486 776U, // USHLLT_ZZI_D
13487 22U, // USHLLT_ZZI_H
13488 776U, // USHLLT_ZZI_S
13489 776U, // USHLLv16i8_shift
13490 776U, // USHLLv2i32_shift
13491 776U, // USHLLv4i16_shift
13492 776U, // USHLLv4i32_shift
13493 776U, // USHLLv8i16_shift
13494 776U, // USHLLv8i8_shift
13495 2056U, // USHLv16i8
13496 776U, // USHLv1i64
13497 2056U, // USHLv2i32
13498 2056U, // USHLv2i64
13499 2056U, // USHLv4i16
13500 2056U, // USHLv4i32
13501 2056U, // USHLv8i16
13502 2056U, // USHLv8i8
13503 776U, // USHRd
13504 776U, // USHRv16i8_shift
13505 776U, // USHRv2i32_shift
13506 776U, // USHRv2i64_shift
13507 776U, // USHRv4i16_shift
13508 776U, // USHRv4i32_shift
13509 776U, // USHRv8i16_shift
13510 776U, // USHRv8i8_shift
13511 0U, // USMMLA
13512 0U, // USMMLA_ZZZ
13513 1083916U, // USQADD_ZPmZ_B
13514 2131468U, // USQADD_ZPmZ_D
13515 3214094U, // USQADD_ZPmZ_H
13516 4230156U, // USQADD_ZPmZ_S
13517 6U, // USQADDv16i8
13518 6U, // USQADDv1i16
13519 6U, // USQADDv1i32
13520 6U, // USQADDv1i64
13521 6U, // USQADDv1i8
13522 6U, // USQADDv2i32
13523 6U, // USQADDv2i64
13524 6U, // USQADDv4i16
13525 6U, // USQADDv4i32
13526 6U, // USQADDv8i16
13527 6U, // USQADDv8i8
13528 38U, // USRA_ZZI_B
13529 9480U, // USRA_ZZI_D
13530 38U, // USRA_ZZI_H
13531 9480U, // USRA_ZZI_S
13532 9480U, // USRAd
13533 9480U, // USRAv16i8_shift
13534 9480U, // USRAv2i32_shift
13535 9480U, // USRAv2i64_shift
13536 9480U, // USRAv4i16_shift
13537 9480U, // USRAv4i32_shift
13538 9480U, // USRAv8i16_shift
13539 9480U, // USRAv8i8_shift
13540 3080U, // USUBLB_ZZZ_D
13541 66U, // USUBLB_ZZZ_H
13542 1288U, // USUBLB_ZZZ_S
13543 3080U, // USUBLT_ZZZ_D
13544 66U, // USUBLT_ZZZ_H
13545 1288U, // USUBLT_ZZZ_S
13546 2056U, // USUBLv16i8_v8i16
13547 2056U, // USUBLv2i32_v2i64
13548 2056U, // USUBLv4i16_v4i32
13549 2056U, // USUBLv4i32_v2i64
13550 2056U, // USUBLv8i16_v4i32
13551 2056U, // USUBLv8i8_v8i16
13552 3080U, // USUBWB_ZZZ_D
13553 66U, // USUBWB_ZZZ_H
13554 1288U, // USUBWB_ZZZ_S
13555 3080U, // USUBWT_ZZZ_D
13556 66U, // USUBWT_ZZZ_H
13557 1288U, // USUBWT_ZZZ_S
13558 2056U, // USUBWv16i8_v8i16
13559 2056U, // USUBWv2i32_v2i64
13560 2056U, // USUBWv4i16_v4i32
13561 2056U, // USUBWv4i32_v2i64
13562 2056U, // USUBWv8i16_v4i32
13563 2056U, // USUBWv8i8_v8i16
13564 6U, // UUNPKHI_ZZ_D
13565 0U, // UUNPKHI_ZZ_H
13566 6U, // UUNPKHI_ZZ_S
13567 6U, // UUNPKLO_ZZ_D
13568 0U, // UUNPKLO_ZZ_H
13569 6U, // UUNPKLO_ZZ_S
13570 2U, // UXTB_ZPmZ_D
13571 0U, // UXTB_ZPmZ_H
13572 4U, // UXTB_ZPmZ_S
13573 2U, // UXTH_ZPmZ_D
13574 4U, // UXTH_ZPmZ_S
13575 2U, // UXTW_ZPmZ_D
13576 2568U, // UZP1_PPP_B
13577 1544U, // UZP1_PPP_D
13578 14U, // UZP1_PPP_H
13579 3080U, // UZP1_PPP_S
13580 2568U, // UZP1_ZZZ_B
13581 1544U, // UZP1_ZZZ_D
13582 14U, // UZP1_ZZZ_H
13583 136U, // UZP1_ZZZ_Q
13584 3080U, // UZP1_ZZZ_S
13585 2056U, // UZP1v16i8
13586 2056U, // UZP1v2i32
13587 2056U, // UZP1v2i64
13588 2056U, // UZP1v4i16
13589 2056U, // UZP1v4i32
13590 2056U, // UZP1v8i16
13591 2056U, // UZP1v8i8
13592 2568U, // UZP2_PPP_B
13593 1544U, // UZP2_PPP_D
13594 14U, // UZP2_PPP_H
13595 3080U, // UZP2_PPP_S
13596 2568U, // UZP2_ZZZ_B
13597 1544U, // UZP2_ZZZ_D
13598 14U, // UZP2_ZZZ_H
13599 136U, // UZP2_ZZZ_Q
13600 3080U, // UZP2_ZZZ_S
13601 2056U, // UZP2v16i8
13602 2056U, // UZP2v2i32
13603 2056U, // UZP2v2i64
13604 2056U, // UZP2v4i16
13605 2056U, // UZP2v4i32
13606 2056U, // UZP2v8i16
13607 2056U, // UZP2v8i8
13608 0U, // WFET
13609 0U, // WFIT
13610 776U, // WHILEGE_PWW_B
13611 776U, // WHILEGE_PWW_D
13612 22U, // WHILEGE_PWW_H
13613 776U, // WHILEGE_PWW_S
13614 776U, // WHILEGE_PXX_B
13615 776U, // WHILEGE_PXX_D
13616 22U, // WHILEGE_PXX_H
13617 776U, // WHILEGE_PXX_S
13618 776U, // WHILEGT_PWW_B
13619 776U, // WHILEGT_PWW_D
13620 22U, // WHILEGT_PWW_H
13621 776U, // WHILEGT_PWW_S
13622 776U, // WHILEGT_PXX_B
13623 776U, // WHILEGT_PXX_D
13624 22U, // WHILEGT_PXX_H
13625 776U, // WHILEGT_PXX_S
13626 776U, // WHILEHI_PWW_B
13627 776U, // WHILEHI_PWW_D
13628 22U, // WHILEHI_PWW_H
13629 776U, // WHILEHI_PWW_S
13630 776U, // WHILEHI_PXX_B
13631 776U, // WHILEHI_PXX_D
13632 22U, // WHILEHI_PXX_H
13633 776U, // WHILEHI_PXX_S
13634 776U, // WHILEHS_PWW_B
13635 776U, // WHILEHS_PWW_D
13636 22U, // WHILEHS_PWW_H
13637 776U, // WHILEHS_PWW_S
13638 776U, // WHILEHS_PXX_B
13639 776U, // WHILEHS_PXX_D
13640 22U, // WHILEHS_PXX_H
13641 776U, // WHILEHS_PXX_S
13642 776U, // WHILELE_PWW_B
13643 776U, // WHILELE_PWW_D
13644 22U, // WHILELE_PWW_H
13645 776U, // WHILELE_PWW_S
13646 776U, // WHILELE_PXX_B
13647 776U, // WHILELE_PXX_D
13648 22U, // WHILELE_PXX_H
13649 776U, // WHILELE_PXX_S
13650 776U, // WHILELO_PWW_B
13651 776U, // WHILELO_PWW_D
13652 22U, // WHILELO_PWW_H
13653 776U, // WHILELO_PWW_S
13654 776U, // WHILELO_PXX_B
13655 776U, // WHILELO_PXX_D
13656 22U, // WHILELO_PXX_H
13657 776U, // WHILELO_PXX_S
13658 776U, // WHILELS_PWW_B
13659 776U, // WHILELS_PWW_D
13660 22U, // WHILELS_PWW_H
13661 776U, // WHILELS_PWW_S
13662 776U, // WHILELS_PXX_B
13663 776U, // WHILELS_PXX_D
13664 22U, // WHILELS_PXX_H
13665 776U, // WHILELS_PXX_S
13666 776U, // WHILELT_PWW_B
13667 776U, // WHILELT_PWW_D
13668 22U, // WHILELT_PWW_H
13669 776U, // WHILELT_PWW_S
13670 776U, // WHILELT_PXX_B
13671 776U, // WHILELT_PXX_D
13672 22U, // WHILELT_PXX_H
13673 776U, // WHILELT_PXX_S
13674 776U, // WHILERW_PXX_B
13675 776U, // WHILERW_PXX_D
13676 22U, // WHILERW_PXX_H
13677 776U, // WHILERW_PXX_S
13678 776U, // WHILEWR_PXX_B
13679 776U, // WHILEWR_PXX_D
13680 22U, // WHILEWR_PXX_H
13681 776U, // WHILEWR_PXX_S
13682 0U, // WRFFR
13683 0U, // XAFLAG
13684 34824U, // XAR
13685 35336U, // XAR_ZZZI_B
13686 34312U, // XAR_ZZZI_D
13687 133902U, // XAR_ZZZI_H
13688 35848U, // XAR_ZZZI_S
13689 0U, // XPACD
13690 0U, // XPACI
13691 0U, // XPACLRI
13692 6U, // XTNv16i8
13693 6U, // XTNv2i32
13694 6U, // XTNv4i16
13695 6U, // XTNv4i32
13696 6U, // XTNv8i16
13697 6U, // XTNv8i8
13698 2568U, // ZIP1_PPP_B
13699 1544U, // ZIP1_PPP_D
13700 14U, // ZIP1_PPP_H
13701 3080U, // ZIP1_PPP_S
13702 2568U, // ZIP1_ZZZ_B
13703 1544U, // ZIP1_ZZZ_D
13704 14U, // ZIP1_ZZZ_H
13705 136U, // ZIP1_ZZZ_Q
13706 3080U, // ZIP1_ZZZ_S
13707 2056U, // ZIP1v16i8
13708 2056U, // ZIP1v2i32
13709 2056U, // ZIP1v2i64
13710 2056U, // ZIP1v4i16
13711 2056U, // ZIP1v4i32
13712 2056U, // ZIP1v8i16
13713 2056U, // ZIP1v8i8
13714 2568U, // ZIP2_PPP_B
13715 1544U, // ZIP2_PPP_D
13716 14U, // ZIP2_PPP_H
13717 3080U, // ZIP2_PPP_S
13718 2568U, // ZIP2_ZZZ_B
13719 1544U, // ZIP2_ZZZ_D
13720 14U, // ZIP2_ZZZ_H
13721 136U, // ZIP2_ZZZ_Q
13722 3080U, // ZIP2_ZZZ_S
13723 2056U, // ZIP2v16i8
13724 2056U, // ZIP2v2i32
13725 2056U, // ZIP2v2i64
13726 2056U, // ZIP2v4i16
13727 2056U, // ZIP2v4i32
13728 2056U, // ZIP2v8i16
13729 2056U, // ZIP2v8i8
13730 };
13731
13732 // Emit the opcode for the instruction.
13733 uint64_t Bits = 0;
13734 Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0;
13735 Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32;
13736 return {AsmStrs+(Bits & 32767)-1, Bits};
13737
13738}
13739/// printInstruction - This method is automatically generated by tablegen
13740/// from the instruction set description.
13741void AArch64AppleInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) {
13742 O << "\t";
13743
13744 auto MnemonicInfo = getMnemonic(MI);
13745
13746 O << MnemonicInfo.first;
13747
13748 uint64_t Bits = MnemonicInfo.second;
13749 assert(Bits != 0 && "Cannot print this instruction.");
13750
13751 // Fragment 0 encoded into 6 bits for 60 unique commands.
13752 switch ((Bits >> 15) & 63) {
13753 default: llvm_unreachable("Invalid command number.");
13754 case 0:
13755 // DBG_VALUE, DBG_INSTR_REF, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_...
13756 return;
13757 break;
13758 case 1:
13759 // TLSDESCCALL, ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDG, ADDPL_XXI, ...
13760 printOperand(MI, 0, STI, O);
13761 break;
13762 case 2:
13763 // ABS_ZPmZ_B, ADDHNB_ZZZ_B, ADDHNT_ZZZ_B, ADDP_ZPmZ_B, ADD_ZI_B, ADD_ZPm...
13764 printSVERegOp<'b'>(MI, 0, STI, O);
13765 break;
13766 case 3:
13767 // ABS_ZPmZ_D, ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDP_ZPmZ_D, ADD_ZI_D, ADD_ZPmZ_...
13768 printSVERegOp<'d'>(MI, 0, STI, O);
13769 break;
13770 case 4:
13771 // ABS_ZPmZ_H, ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADDP_ZPmZ_H, ADD_ZI_H, ADD_ZPm...
13772 printSVERegOp<'h'>(MI, 0, STI, O);
13773 O << ", ";
13774 break;
13775 case 5:
13776 // ABS_ZPmZ_S, ADCLB_ZZZ_S, ADCLT_ZZZ_S, ADDHNB_ZZZ_S, ADDHNT_ZZZ_S, ADDP...
13777 printSVERegOp<'s'>(MI, 0, STI, O);
13778 break;
13779 case 6:
13780 // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A...
13781 printVRegOperand(MI, 0, STI, O);
13782 break;
13783 case 7:
13784 // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ...
13785 printVRegOperand(MI, 1, STI, O);
13786 break;
13787 case 8:
13788 // ANDV_VPZ_B, EORV_VPZ_B, ORV_VPZ_B, SMAXV_VPZ_B, SMINV_VPZ_B, UMAXV_VPZ...
13789 printZPRasFPR<8>(MI, 0, STI, O);
13790 O << ", ";
13791 printSVERegOp<>(MI, 1, STI, O);
13792 O << ", ";
13793 printSVERegOp<'b'>(MI, 2, STI, O);
13794 return;
13795 break;
13796 case 9:
13797 // ANDV_VPZ_D, EORV_VPZ_D, FADDA_VPZ_D, FADDV_VPZ_D, FMAXNMV_VPZ_D, FMAXV...
13798 printZPRasFPR<64>(MI, 0, STI, O);
13799 O << ", ";
13800 printSVERegOp<>(MI, 1, STI, O);
13801 O << ", ";
13802 break;
13803 case 10:
13804 // ANDV_VPZ_H, EORV_VPZ_H, FADDA_VPZ_H, FADDV_VPZ_H, FMAXNMV_VPZ_H, FMAXV...
13805 printZPRasFPR<16>(MI, 0, STI, O);
13806 O << ", ";
13807 printSVERegOp<>(MI, 1, STI, O);
13808 O << ", ";
13809 break;
13810 case 11:
13811 // ANDV_VPZ_S, EORV_VPZ_S, FADDA_VPZ_S, FADDV_VPZ_S, FMAXNMV_VPZ_S, FMAXV...
13812 printZPRasFPR<32>(MI, 0, STI, O);
13813 O << ", ";
13814 printSVERegOp<>(MI, 1, STI, O);
13815 O << ", ";
13816 break;
13817 case 12:
13818 // B, BL
13819 printAlignedLabel(MI, Address, 0, STI, O);
13820 return;
13821 break;
13822 case 13:
13823 // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC, TCANCEL
13824 printImmHex(MI, 0, STI, O);
13825 return;
13826 break;
13827 case 14:
13828 // Bcc
13829 printCondCode(MI, 0, STI, O);
13830 O << "\t";
13831 printAlignedLabel(MI, Address, 1, STI, O);
13832 return;
13833 break;
13834 case 15:
13835 // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH...
13836 printOperand(MI, 1, STI, O);
13837 break;
13838 case 16:
13839 // CASPALW, CASPAW, CASPLW, CASPW
13840 printGPRSeqPairsClassOperand<32>(MI, 1, STI, O);
13841 O << ", ";
13842 printGPRSeqPairsClassOperand<32>(MI, 2, STI, O);
13843 O << ", [";
13844 printOperand(MI, 3, STI, O);
13845 O << ']';
13846 return;
13847 break;
13848 case 17:
13849 // CASPALX, CASPAX, CASPLX, CASPX
13850 printGPRSeqPairsClassOperand<64>(MI, 1, STI, O);
13851 O << ", ";
13852 printGPRSeqPairsClassOperand<64>(MI, 2, STI, O);
13853 O << ", [";
13854 printOperand(MI, 3, STI, O);
13855 O << ']';
13856 return;
13857 break;
13858 case 18:
13859 // DMB, DSB, ISB, TSB
13860 printBarrierOption(MI, 0, STI, O);
13861 return;
13862 break;
13863 case 19:
13864 // DSBnXS
13865 printBarriernXSOption(MI, 0, STI, O);
13866 return;
13867 break;
13868 case 20:
13869 // DUP_ZZI_Q, PMULLB_ZZZ_Q, PMULLT_ZZZ_Q, TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZ...
13870 printSVERegOp<'q'>(MI, 0, STI, O);
13871 O << ", ";
13872 break;
13873 case 21:
13874 // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ...
13875 printTypedVectorList<0,'d'>(MI, 0, STI, O);
13876 O << ", ";
13877 printSVERegOp<>(MI, 1, STI, O);
13878 break;
13879 case 22:
13880 // GLD1B_S_IMM_REAL, GLD1B_S_SXTW_REAL, GLD1B_S_UXTW_REAL, GLD1H_S_IMM_RE...
13881 printTypedVectorList<0,'s'>(MI, 0, STI, O);
13882 O << ", ";
13883 printSVERegOp<>(MI, 1, STI, O);
13884 break;
13885 case 23:
13886 // HINT
13887 printImm(MI, 0, STI, O);
13888 return;
13889 break;
13890 case 24:
13891 // LD1B, LD1B_IMM_REAL, LD1RB_IMM, LD1RO_B, LD1RO_B_IMM, LD1RQ_B, LD1RQ_B...
13892 printTypedVectorList<0,'b'>(MI, 0, STI, O);
13893 O << ", ";
13894 printSVERegOp<>(MI, 1, STI, O);
13895 break;
13896 case 25:
13897 // LD1B_H, LD1B_H_IMM_REAL, LD1H, LD1H_IMM_REAL, LD1RB_H_IMM, LD1RH_IMM, ...
13898 printTypedVectorList<0,'h'>(MI, 0, STI, O);
13899 O << ", ";
13900 printSVERegOp<>(MI, 1, STI, O);
13901 break;
13902 case 26:
13903 // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,...
13904 printTypedVectorList<16, 'b'>(MI, 0, STI, O);
13905 O << ", [";
13906 printOperand(MI, 1, STI, O);
13907 O << ']';
13908 return;
13909 break;
13910 case 27:
13911 // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L...
13912 printTypedVectorList<16, 'b'>(MI, 1, STI, O);
13913 O << ", [";
13914 printOperand(MI, 2, STI, O);
13915 O << "], ";
13916 break;
13917 case 28:
13918 // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv...
13919 printTypedVectorList<1, 'd'>(MI, 0, STI, O);
13920 O << ", [";
13921 printOperand(MI, 1, STI, O);
13922 O << ']';
13923 return;
13924 break;
13925 case 29:
13926 // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw...
13927 printTypedVectorList<1, 'd'>(MI, 1, STI, O);
13928 O << ", [";
13929 printOperand(MI, 2, STI, O);
13930 O << "], ";
13931 break;
13932 case 30:
13933 // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw...
13934 printTypedVectorList<2, 'd'>(MI, 0, STI, O);
13935 O << ", [";
13936 printOperand(MI, 1, STI, O);
13937 O << ']';
13938 return;
13939 break;
13940 case 31:
13941 // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw...
13942 printTypedVectorList<2, 'd'>(MI, 1, STI, O);
13943 O << ", [";
13944 printOperand(MI, 2, STI, O);
13945 O << "], ";
13946 break;
13947 case 32:
13948 // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw...
13949 printTypedVectorList<2, 's'>(MI, 0, STI, O);
13950 O << ", [";
13951 printOperand(MI, 1, STI, O);
13952 O << ']';
13953 return;
13954 break;
13955 case 33:
13956 // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw...
13957 printTypedVectorList<2, 's'>(MI, 1, STI, O);
13958 O << ", [";
13959 printOperand(MI, 2, STI, O);
13960 O << "], ";
13961 break;
13962 case 34:
13963 // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw...
13964 printTypedVectorList<4, 'h'>(MI, 0, STI, O);
13965 O << ", [";
13966 printOperand(MI, 1, STI, O);
13967 O << ']';
13968 return;
13969 break;
13970 case 35:
13971 // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw...
13972 printTypedVectorList<4, 'h'>(MI, 1, STI, O);
13973 O << ", [";
13974 printOperand(MI, 2, STI, O);
13975 O << "], ";
13976 break;
13977 case 36:
13978 // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw...
13979 printTypedVectorList<4, 's'>(MI, 0, STI, O);
13980 O << ", [";
13981 printOperand(MI, 1, STI, O);
13982 O << ']';
13983 return;
13984 break;
13985 case 37:
13986 // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw...
13987 printTypedVectorList<4, 's'>(MI, 1, STI, O);
13988 O << ", [";
13989 printOperand(MI, 2, STI, O);
13990 O << "], ";
13991 break;
13992 case 38:
13993 // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw...
13994 printTypedVectorList<8, 'b'>(MI, 0, STI, O);
13995 O << ", [";
13996 printOperand(MI, 1, STI, O);
13997 O << ']';
13998 return;
13999 break;
14000 case 39:
14001 // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw...
14002 printTypedVectorList<8, 'b'>(MI, 1, STI, O);
14003 O << ", [";
14004 printOperand(MI, 2, STI, O);
14005 O << "], ";
14006 break;
14007 case 40:
14008 // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw...
14009 printTypedVectorList<8, 'h'>(MI, 0, STI, O);
14010 O << ", [";
14011 printOperand(MI, 1, STI, O);
14012 O << ']';
14013 return;
14014 break;
14015 case 41:
14016 // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw...
14017 printTypedVectorList<8, 'h'>(MI, 1, STI, O);
14018 O << ", [";
14019 printOperand(MI, 2, STI, O);
14020 O << "], ";
14021 break;
14022 case 42:
14023 // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,...
14024 printTypedVectorList<0, 'h'>(MI, 1, STI, O);
14025 printVectorIndex(MI, 2, STI, O);
14026 O << ", [";
14027 printOperand(MI, 3, STI, O);
14028 break;
14029 case 43:
14030 // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST
14031 printTypedVectorList<0, 'h'>(MI, 2, STI, O);
14032 printVectorIndex(MI, 3, STI, O);
14033 O << ", [";
14034 printOperand(MI, 4, STI, O);
14035 O << "], ";
14036 break;
14037 case 44:
14038 // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,...
14039 printTypedVectorList<0, 's'>(MI, 1, STI, O);
14040 printVectorIndex(MI, 2, STI, O);
14041 O << ", [";
14042 printOperand(MI, 3, STI, O);
14043 break;
14044 case 45:
14045 // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST
14046 printTypedVectorList<0, 's'>(MI, 2, STI, O);
14047 printVectorIndex(MI, 3, STI, O);
14048 O << ", [";
14049 printOperand(MI, 4, STI, O);
14050 O << "], ";
14051 break;
14052 case 46:
14053 // LD1i64, LD2i64, LD3i64, LD4i64, ST1i64_POST, ST2i64_POST, ST3i64_POST,...
14054 printTypedVectorList<0, 'd'>(MI, 1, STI, O);
14055 printVectorIndex(MI, 2, STI, O);
14056 O << ", [";
14057 printOperand(MI, 3, STI, O);
14058 break;
14059 case 47:
14060 // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST
14061 printTypedVectorList<0, 'd'>(MI, 2, STI, O);
14062 printVectorIndex(MI, 3, STI, O);
14063 O << ", [";
14064 printOperand(MI, 4, STI, O);
14065 O << "], ";
14066 break;
14067 case 48:
14068 // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_...
14069 printTypedVectorList<0, 'b'>(MI, 1, STI, O);
14070 printVectorIndex(MI, 2, STI, O);
14071 O << ", [";
14072 printOperand(MI, 3, STI, O);
14073 break;
14074 case 49:
14075 // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST
14076 printTypedVectorList<0, 'b'>(MI, 2, STI, O);
14077 printVectorIndex(MI, 3, STI, O);
14078 O << ", [";
14079 printOperand(MI, 4, STI, O);
14080 O << "], ";
14081 break;
14082 case 50:
14083 // LD64B, ST64B
14084 printGPR64x8(MI, 0, STI, O);
14085 O << ", [";
14086 printOperand(MI, 1, STI, O);
14087 O << ']';
14088 return;
14089 break;
14090 case 51:
14091 // LDR_PXI, LDR_ZXI, MOVPRFX_ZZ, PTEST_PP, STR_PXI, STR_ZXI
14092 printSVERegOp<>(MI, 0, STI, O);
14093 break;
14094 case 52:
14095 // MSR
14096 printMSRSystemRegister(MI, 0, STI, O);
14097 O << ", ";
14098 printOperand(MI, 1, STI, O);
14099 return;
14100 break;
14101 case 53:
14102 // MSRpstateImm1, MSRpstateImm4
14103 printSystemPStateField(MI, 0, STI, O);
14104 O << ", ";
14105 printOperand(MI, 1, STI, O);
14106 return;
14107 break;
14108 case 54:
14109 // PRFB_D_PZI, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_SCALED, PRF...
14110 printPrefetchOp<true>(MI, 0, STI, O);
14111 O << ", ";
14112 printSVERegOp<>(MI, 1, STI, O);
14113 O << ", [";
14114 break;
14115 case 55:
14116 // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi
14117 printPrefetchOp(MI, 0, STI, O);
14118 break;
14119 case 56:
14120 // ST1i16, ST2i16, ST3i16, ST4i16
14121 printTypedVectorList<0, 'h'>(MI, 0, STI, O);
14122 printVectorIndex(MI, 1, STI, O);
14123 O << ", [";
14124 printOperand(MI, 2, STI, O);
14125 O << ']';
14126 return;
14127 break;
14128 case 57:
14129 // ST1i32, ST2i32, ST3i32, ST4i32
14130 printTypedVectorList<0, 's'>(MI, 0, STI, O);
14131 printVectorIndex(MI, 1, STI, O);
14132 O << ", [";
14133 printOperand(MI, 2, STI, O);
14134 O << ']';
14135 return;
14136 break;
14137 case 58:
14138 // ST1i64, ST2i64, ST3i64, ST4i64
14139 printTypedVectorList<0, 'd'>(MI, 0, STI, O);
14140 printVectorIndex(MI, 1, STI, O);
14141 O << ", [";
14142 printOperand(MI, 2, STI, O);
14143 O << ']';
14144 return;
14145 break;
14146 case 59:
14147 // ST1i8, ST2i8, ST3i8, ST4i8
14148 printTypedVectorList<0, 'b'>(MI, 0, STI, O);
14149 printVectorIndex(MI, 1, STI, O);
14150 O << ", [";
14151 printOperand(MI, 2, STI, O);
14152 O << ']';
14153 return;
14154 break;
14155 }
14156
14157
14158 // Fragment 1 encoded into 6 bits for 59 unique commands.
14159 switch ((Bits >> 21) & 63) {
14160 default: llvm_unreachable("Invalid command number.");
14161 case 0:
14162 // TLSDESCCALL, AUTDZA, AUTDZB, AUTIZA, AUTIZB, BLR, BLRAAZ, BLRABZ, BR, ...
14163 return;
14164 break;
14165 case 1:
14166 // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ABSv16i8, ABSv1i64, ABSv2i32, ABSv...
14167 O << ", ";
14168 break;
14169 case 2:
14170 // ABS_ZPmZ_H, BFCVTNT_ZPmZ, BFCVT_ZPmZ, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPm...
14171 printSVERegOp<>(MI, 2, STI, O);
14172 O << "/m, ";
14173 break;
14174 case 3:
14175 // ADDHNB_ZZZ_H, RADDHNB_ZZZ_H, RSHRNB_ZZI_H, RSUBHNB_ZZZ_H, SHRNB_ZZI_H,...
14176 printSVERegOp<'s'>(MI, 1, STI, O);
14177 break;
14178 case 4:
14179 // ADDHNT_ZZZ_H, ANDV_VPZ_S, EORV_VPZ_S, FADDV_VPZ_S, FMAXNMV_VPZ_S, FMAX...
14180 printSVERegOp<'s'>(MI, 2, STI, O);
14181 break;
14182 case 5:
14183 // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID...
14184 printSVERegOp<>(MI, 1, STI, O);
14185 break;
14186 case 6:
14187 // ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_ZZI_H, BDEP_ZZZ_H, BEXT_ZZZ_H...
14188 printSVERegOp<'h'>(MI, 1, STI, O);
14189 break;
14190 case 7:
14191 // ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2, ADR_LSL_ZZZ_D_3, AD...
14192 O << ", [";
14193 break;
14194 case 8:
14195 // ANDV_VPZ_D, EORV_VPZ_D, FADDV_VPZ_D, FMAXNMV_VPZ_D, FMAXV_VPZ_D, FMINN...
14196 printSVERegOp<'d'>(MI, 2, STI, O);
14197 break;
14198 case 9:
14199 // ANDV_VPZ_H, CMLA_ZZZI_H, CMLA_ZZZ_H, DECP_ZP_H, EORBT_ZZZ_H, EORTB_ZZZ...
14200 printSVERegOp<'h'>(MI, 2, STI, O);
14201 break;
14202 case 10:
14203 // DECH_ZPiI, INCH_ZPiI, SQDECH_ZPiI, SQINCH_ZPiI, UQDECH_ZPiI, UQINCH_ZP...
14204 printSVEPattern(MI, 2, STI, O);
14205 O << ", mul ";
14206 printOperand(MI, 3, STI, O);
14207 return;
14208 break;
14209 case 11:
14210 // DUP_ZI_H
14211 printImm8OptLsl<int16_t>(MI, 1, STI, O);
14212 return;
14213 break;
14214 case 12:
14215 // DUP_ZR_H, INDEX_RI_H, INDEX_RR_H, WHILEGE_PWW_H, WHILEGE_PXX_H, WHILEG...
14216 printOperand(MI, 1, STI, O);
14217 break;
14218 case 13:
14219 // DUP_ZZI_Q, TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZZ_Q, UZP2_ZZZ_Q, ZIP1_ZZZ_Q,...
14220 printSVERegOp<'q'>(MI, 1, STI, O);
14221 break;
14222 case 14:
14223 // FADDA_VPZ_D
14224 printZPRasFPR<64>(MI, 2, STI, O);
14225 O << ", ";
14226 printSVERegOp<'d'>(MI, 3, STI, O);
14227 return;
14228 break;
14229 case 15:
14230 // FADDA_VPZ_H
14231 printZPRasFPR<16>(MI, 2, STI, O);
14232 O << ", ";
14233 printSVERegOp<'h'>(MI, 3, STI, O);
14234 return;
14235 break;
14236 case 16:
14237 // FADDA_VPZ_S
14238 printZPRasFPR<32>(MI, 2, STI, O);
14239 O << ", ";
14240 printSVERegOp<'s'>(MI, 3, STI, O);
14241 return;
14242 break;
14243 case 17:
14244 // FCMPDri, FCMPEDri, FCMPEHri, FCMPESri, FCMPHri, FCMPSri
14245 O << ", #0.0";
14246 return;
14247 break;
14248 case 18:
14249 // FCVTLv2i32, FCVTLv4i32
14250 O << ".2d, ";
14251 printVRegOperand(MI, 1, STI, O);
14252 break;
14253 case 19:
14254 // FCVTLv4i16, FCVTLv8i16, FCVTNv4i32, FCVTXNv4f32
14255 O << ".4s, ";
14256 break;
14257 case 20:
14258 // FCVTNv2i32, FCVTXNv2f32
14259 O << ".2s, ";
14260 printVRegOperand(MI, 1, STI, O);
14261 O << ".2d";
14262 return;
14263 break;
14264 case 21:
14265 // FCVTNv4i16
14266 O << ".4h, ";
14267 printVRegOperand(MI, 1, STI, O);
14268 O << ".4s";
14269 return;
14270 break;
14271 case 22:
14272 // FCVTNv8i16
14273 O << ".8h, ";
14274 printVRegOperand(MI, 2, STI, O);
14275 O << ".4s";
14276 return;
14277 break;
14278 case 23:
14279 // FDUP_ZI_H
14280 printFPImmOperand(MI, 1, STI, O);
14281 return;
14282 break;
14283 case 24:
14284 // FMOVXDHighr, INSvi16gpr, INSvi16lane, INSvi32gpr, INSvi32lane, INSvi64...
14285 printVectorIndex(MI, 2, STI, O);
14286 O << ", ";
14287 break;
14288 case 25:
14289 // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ...
14290 O << "/z, [";
14291 break;
14292 case 26:
14293 // INDEX_II_H, INDEX_IR_H
14294 printSImm<16>(MI, 1, STI, O);
14295 O << ", ";
14296 break;
14297 case 27:
14298 // INSR_ZR_H, INSR_ZV_H, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_S...
14299 printOperand(MI, 2, STI, O);
14300 break;
14301 case 28:
14302 // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L...
14303 printPostIncOperand<64>(MI, 3, STI, O);
14304 return;
14305 break;
14306 case 29:
14307 // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD...
14308 printPostIncOperand<32>(MI, 3, STI, O);
14309 return;
14310 break;
14311 case 30:
14312 // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw...
14313 printPostIncOperand<16>(MI, 3, STI, O);
14314 return;
14315 break;
14316 case 31:
14317 // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1...
14318 printPostIncOperand<8>(MI, 3, STI, O);
14319 return;
14320 break;
14321 case 32:
14322 // LD1Rv16b_POST, LD1Rv8b_POST
14323 printPostIncOperand<1>(MI, 3, STI, O);
14324 return;
14325 break;
14326 case 33:
14327 // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,...
14328 printPostIncOperand<4>(MI, 3, STI, O);
14329 return;
14330 break;
14331 case 34:
14332 // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST
14333 printPostIncOperand<2>(MI, 3, STI, O);
14334 return;
14335 break;
14336 case 35:
14337 // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS...
14338 printPostIncOperand<48>(MI, 3, STI, O);
14339 return;
14340 break;
14341 case 36:
14342 // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST...
14343 printPostIncOperand<24>(MI, 3, STI, O);
14344 return;
14345 break;
14346 case 37:
14347 // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ...
14348 O << ']';
14349 return;
14350 break;
14351 case 38:
14352 // LD1i16_POST, LD2i8_POST
14353 printPostIncOperand<2>(MI, 5, STI, O);
14354 return;
14355 break;
14356 case 39:
14357 // LD1i32_POST, LD2i16_POST, LD4i8_POST
14358 printPostIncOperand<4>(MI, 5, STI, O);
14359 return;
14360 break;
14361 case 40:
14362 // LD1i64_POST, LD2i32_POST, LD4i16_POST
14363 printPostIncOperand<8>(MI, 5, STI, O);
14364 return;
14365 break;
14366 case 41:
14367 // LD1i8_POST
14368 printPostIncOperand<1>(MI, 5, STI, O);
14369 return;
14370 break;
14371 case 42:
14372 // LD2i64_POST, LD4i32_POST
14373 printPostIncOperand<16>(MI, 5, STI, O);
14374 return;
14375 break;
14376 case 43:
14377 // LD3Rv16b_POST, LD3Rv8b_POST
14378 printPostIncOperand<3>(MI, 3, STI, O);
14379 return;
14380 break;
14381 case 44:
14382 // LD3Rv2s_POST, LD3Rv4s_POST
14383 printPostIncOperand<12>(MI, 3, STI, O);
14384 return;
14385 break;
14386 case 45:
14387 // LD3Rv4h_POST, LD3Rv8h_POST
14388 printPostIncOperand<6>(MI, 3, STI, O);
14389 return;
14390 break;
14391 case 46:
14392 // LD3i16_POST
14393 printPostIncOperand<6>(MI, 5, STI, O);
14394 return;
14395 break;
14396 case 47:
14397 // LD3i32_POST
14398 printPostIncOperand<12>(MI, 5, STI, O);
14399 return;
14400 break;
14401 case 48:
14402 // LD3i64_POST
14403 printPostIncOperand<24>(MI, 5, STI, O);
14404 return;
14405 break;
14406 case 49:
14407 // LD3i8_POST
14408 printPostIncOperand<3>(MI, 5, STI, O);
14409 return;
14410 break;
14411 case 50:
14412 // LD4i64_POST
14413 printPostIncOperand<32>(MI, 5, STI, O);
14414 return;
14415 break;
14416 case 51:
14417 // PMULLB_ZZZ_H, PMULLT_ZZZ_H, PUNPKHI_PP, PUNPKLO_PP, SABDLB_ZZZ_H, SABD...
14418 printSVERegOp<'b'>(MI, 1, STI, O);
14419 break;
14420 case 52:
14421 // PMULLB_ZZZ_Q, PMULLT_ZZZ_Q
14422 printSVERegOp<'d'>(MI, 1, STI, O);
14423 O << ", ";
14424 printSVERegOp<'d'>(MI, 2, STI, O);
14425 return;
14426 break;
14427 case 53:
14428 // PTRUES_H, PTRUE_H
14429 printSVEPattern(MI, 1, STI, O);
14430 return;
14431 break;
14432 case 54:
14433 // SABALB_ZZZ_H, SABALT_ZZZ_H, SADDV_VPZ_B, SMLALB_ZZZ_H, SMLALT_ZZZ_H, S...
14434 printSVERegOp<'b'>(MI, 2, STI, O);
14435 break;
14436 case 55:
14437 // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32...
14438 O << "], ";
14439 break;
14440 case 56:
14441 // TBL_ZZZZ_H, TBL_ZZZ_H
14442 printTypedVectorList<0,'h'>(MI, 1, STI, O);
14443 O << ", ";
14444 printSVERegOp<'h'>(MI, 2, STI, O);
14445 return;
14446 break;
14447 case 57:
14448 // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBXv16i8Four, T...
14449 O << ".16b, ";
14450 break;
14451 case 58:
14452 // TBLv8i8Four, TBLv8i8One, TBLv8i8Three, TBLv8i8Two, TBXv8i8Four, TBXv8i...
14453 O << ".8b, ";
14454 break;
14455 }
14456
14457
14458 // Fragment 2 encoded into 6 bits for 62 unique commands.
14459 switch ((Bits >> 27) & 63) {
14460 default: llvm_unreachable("Invalid command number.");
14461 case 0:
14462 // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, ...
14463 printSVERegOp<>(MI, 2, STI, O);
14464 O << "/m, ";
14465 break;
14466 case 1:
14467 // ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, FABS_ZPmZ...
14468 printSVERegOp<'h'>(MI, 3, STI, O);
14469 return;
14470 break;
14471 case 2:
14472 // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A...
14473 printVRegOperand(MI, 1, STI, O);
14474 break;
14475 case 3:
14476 // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDG, ADDPL_XXI, ADDSWri, ADDS...
14477 printOperand(MI, 1, STI, O);
14478 break;
14479 case 4:
14480 // ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, DECP_ZP_D, EORBT_Z...
14481 printSVERegOp<'d'>(MI, 2, STI, O);
14482 break;
14483 case 5:
14484 // ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, DECP_ZP_S, EORBT_ZZ...
14485 printSVERegOp<'s'>(MI, 2, STI, O);
14486 break;
14487 case 6:
14488 // ADDHNB_ZZZ_B, DECP_XP_H, INCP_XP_H, RADDHNB_ZZZ_B, RSHRNB_ZZI_B, RSUBH...
14489 printSVERegOp<'h'>(MI, 1, STI, O);
14490 break;
14491 case 7:
14492 // ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_Z...
14493 O << ", ";
14494 break;
14495 case 8:
14496 // ADDHNB_ZZZ_S, ADD_ZI_D, ADD_ZZZ_D, ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, A...
14497 printSVERegOp<'d'>(MI, 1, STI, O);
14498 break;
14499 case 9:
14500 // ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMMLA_B_ZZI, BFMMLA_B_ZZZ, BFMMLA...
14501 printSVERegOp<'h'>(MI, 2, STI, O);
14502 break;
14503 case 10:
14504 // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ...
14505 printVRegOperand(MI, 2, STI, O);
14506 break;
14507 case 11:
14508 // ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPm...
14509 printSVERegOp<>(MI, 1, STI, O);
14510 break;
14511 case 12:
14512 // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID...
14513 O << "/m, ";
14514 break;
14515 case 13:
14516 // ADD_ZI_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_B, AESIMC_ZZ_B, AESMC_ZZ_B, ...
14517 printSVERegOp<'b'>(MI, 1, STI, O);
14518 break;
14519 case 14:
14520 // ADD_ZI_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_LSL_ZZZ_S_1, ADR_LSL_ZZZ_S_2...
14521 printSVERegOp<'s'>(MI, 1, STI, O);
14522 break;
14523 case 15:
14524 // ADRP
14525 printAdrpLabel(MI, Address, 1, STI, O);
14526 return;
14527 break;
14528 case 16:
14529 // ANDV_VPZ_D, ANDV_VPZ_H, ANDV_VPZ_S, DECP_ZP_H, DUP_ZR_H, EORV_VPZ_D, E...
14530 return;
14531 break;
14532 case 17:
14533 // BFCVTNT_ZPmZ, BFCVT_ZPmZ, FCVTNT_ZPmZ_StoH, FCVT_ZPmZ_StoH, SCVTF_ZPmZ...
14534 printSVERegOp<'s'>(MI, 3, STI, O);
14535 return;
14536 break;
14537 case 18:
14538 // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C...
14539 printOperand(MI, 2, STI, O);
14540 break;
14541 case 19:
14542 // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv...
14543 printImm(MI, 2, STI, O);
14544 printShifter(MI, 3, STI, O);
14545 return;
14546 break;
14547 case 20:
14548 // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P...
14549 printAlignedLabel(MI, Address, 1, STI, O);
14550 return;
14551 break;
14552 case 21:
14553 // CDOT_ZZZI_S, CDOT_ZZZ_S, CMLA_ZZZ_B, EORBT_ZZZ_B, EORTB_ZZZ_B, SABA_ZZ...
14554 printSVERegOp<'b'>(MI, 2, STI, O);
14555 O << ", ";
14556 break;
14557 case 22:
14558 // CMPEQ_PPzZI_H, CMPEQ_PPzZZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_PPzZI_H, CMPGE...
14559 O << "/z, ";
14560 break;
14561 case 23:
14562 // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI, PTRUES_B, PTRUES_D, PTRUES...
14563 printSVEPattern(MI, 1, STI, O);
14564 break;
14565 case 24:
14566 // CPY_ZPmI_H
14567 printImm8OptLsl<int16_t>(MI, 3, STI, O);
14568 return;
14569 break;
14570 case 25:
14571 // CPY_ZPmR_H, CPY_ZPmV_H, INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr
14572 printOperand(MI, 3, STI, O);
14573 return;
14574 break;
14575 case 26:
14576 // DECB_XPiI, DECD_XPiI, DECD_ZPiI, DECH_XPiI, DECW_XPiI, DECW_ZPiI, INCB...
14577 printSVEPattern(MI, 2, STI, O);
14578 O << ", mul ";
14579 printOperand(MI, 3, STI, O);
14580 return;
14581 break;
14582 case 27:
14583 // DUPM_ZI
14584 printLogicalImm<int64_t>(MI, 1, STI, O);
14585 return;
14586 break;
14587 case 28:
14588 // DUP_ZI_B
14589 printImm8OptLsl<int8_t>(MI, 1, STI, O);
14590 return;
14591 break;
14592 case 29:
14593 // DUP_ZI_D
14594 printImm8OptLsl<int64_t>(MI, 1, STI, O);
14595 return;
14596 break;
14597 case 30:
14598 // DUP_ZI_S
14599 printImm8OptLsl<int32_t>(MI, 1, STI, O);
14600 return;
14601 break;
14602 case 31:
14603 // DUP_ZZI_H, DUP_ZZI_Q
14604 printVectorIndex(MI, 2, STI, O);
14605 return;
14606 break;
14607 case 32:
14608 // EXT_ZZI_B, TBL_ZZZZ_B, TBL_ZZZ_B
14609 printTypedVectorList<0,'b'>(MI, 1, STI, O);
14610 O << ", ";
14611 break;
14612 case 33:
14613 // FCPY_ZPmI_H
14614 printFPImmOperand(MI, 3, STI, O);
14615 return;
14616 break;
14617 case 34:
14618 // FCVTLv2i32
14619 O << ".2s";
14620 return;
14621 break;
14622 case 35:
14623 // FCVTLv4i32
14624 O << ".4s";
14625 return;
14626 break;
14627 case 36:
14628 // FCVT_ZPmZ_DtoH, SCVTF_ZPmZ_DtoH, UCVTF_ZPmZ_DtoH
14629 printSVERegOp<'d'>(MI, 3, STI, O);
14630 return;
14631 break;
14632 case 37:
14633 // FDUP_ZI_D, FDUP_ZI_S, FMOVDi, FMOVHi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_...
14634 printFPImmOperand(MI, 1, STI, O);
14635 return;
14636 break;
14637 case 38:
14638 // INDEX_II_B, INDEX_IR_B
14639 printSImm<8>(MI, 1, STI, O);
14640 O << ", ";
14641 break;
14642 case 39:
14643 // INDEX_II_H
14644 printSImm<16>(MI, 2, STI, O);
14645 return;
14646 break;
14647 case 40:
14648 // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane
14649 printVRegOperand(MI, 3, STI, O);
14650 printVectorIndex(MI, 4, STI, O);
14651 return;
14652 break;
14653 case 41:
14654 // LDADDAB, LDADDAH, LDADDALB, LDADDALH, LDADDALW, LDADDALX, LDADDAW, LDA...
14655 printOperand(MI, 0, STI, O);
14656 O << ", [";
14657 printOperand(MI, 2, STI, O);
14658 O << ']';
14659 return;
14660 break;
14661 case 42:
14662 // MOVID, MOVIv2d_ns
14663 printSIMDType10Operand(MI, 1, STI, O);
14664 return;
14665 break;
14666 case 43:
14667 // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl...
14668 printImm(MI, 1, STI, O);
14669 break;
14670 case 44:
14671 // MRS
14672 printMRSSystemRegister(MI, 1, STI, O);
14673 return;
14674 break;
14675 case 45:
14676 // SQDECB_XPiWdI, SQDECD_XPiWdI, SQDECH_XPiWdI, SQDECW_XPiWdI, SQINCB_XPi...
14677 printGPR64as32(MI, 1, STI, O);
14678 O << ", ";
14679 printSVEPattern(MI, 2, STI, O);
14680 O << ", mul ";
14681 printOperand(MI, 3, STI, O);
14682 return;
14683 break;
14684 case 46:
14685 // ST1i16_POST, ST2i8_POST
14686 printPostIncOperand<2>(MI, 4, STI, O);
14687 return;
14688 break;
14689 case 47:
14690 // ST1i32_POST, ST2i16_POST, ST4i8_POST
14691 printPostIncOperand<4>(MI, 4, STI, O);
14692 return;
14693 break;
14694 case 48:
14695 // ST1i64_POST, ST2i32_POST, ST4i16_POST
14696 printPostIncOperand<8>(MI, 4, STI, O);
14697 return;
14698 break;
14699 case 49:
14700 // ST1i8_POST
14701 printPostIncOperand<1>(MI, 4, STI, O);
14702 return;
14703 break;
14704 case 50:
14705 // ST2i64_POST, ST4i32_POST
14706 printPostIncOperand<16>(MI, 4, STI, O);
14707 return;
14708 break;
14709 case 51:
14710 // ST3i16_POST
14711 printPostIncOperand<6>(MI, 4, STI, O);
14712 return;
14713 break;
14714 case 52:
14715 // ST3i32_POST
14716 printPostIncOperand<12>(MI, 4, STI, O);
14717 return;
14718 break;
14719 case 53:
14720 // ST3i64_POST
14721 printPostIncOperand<24>(MI, 4, STI, O);
14722 return;
14723 break;
14724 case 54:
14725 // ST3i8_POST
14726 printPostIncOperand<3>(MI, 4, STI, O);
14727 return;
14728 break;
14729 case 55:
14730 // ST4i64_POST
14731 printPostIncOperand<32>(MI, 4, STI, O);
14732 return;
14733 break;
14734 case 56:
14735 // ST64BV, ST64BV0
14736 printGPR64x8(MI, 1, STI, O);
14737 O << ", [";
14738 printOperand(MI, 2, STI, O);
14739 O << ']';
14740 return;
14741 break;
14742 case 57:
14743 // SYSxt
14744 printSysCROperand(MI, 1, STI, O);
14745 O << ", ";
14746 printSysCROperand(MI, 2, STI, O);
14747 O << ", ";
14748 printOperand(MI, 3, STI, O);
14749 O << ", ";
14750 printOperand(MI, 4, STI, O);
14751 return;
14752 break;
14753 case 58:
14754 // TBL_ZZZZ_D, TBL_ZZZ_D
14755 printTypedVectorList<0,'d'>(MI, 1, STI, O);
14756 O << ", ";
14757 printSVERegOp<'d'>(MI, 2, STI, O);
14758 return;
14759 break;
14760 case 59:
14761 // TBL_ZZZZ_S, TBL_ZZZ_S
14762 printTypedVectorList<0,'s'>(MI, 1, STI, O);
14763 O << ", ";
14764 printSVERegOp<'s'>(MI, 2, STI, O);
14765 return;
14766 break;
14767 case 60:
14768 // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB...
14769 printTypedVectorList<16, 'b'>(MI, 1, STI, O);
14770 O << ", ";
14771 printVRegOperand(MI, 2, STI, O);
14772 break;
14773 case 61:
14774 // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB...
14775 printTypedVectorList<16, 'b'>(MI, 2, STI, O);
14776 O << ", ";
14777 printVRegOperand(MI, 3, STI, O);
14778 break;
14779 }
14780
14781
14782 // Fragment 3 encoded into 7 bits for 69 unique commands.
14783 switch ((Bits >> 33) & 127) {
14784 default: llvm_unreachable("Invalid command number.");
14785 case 0:
14786 // ABS_ZPmZ_B, BRKA_PPmP, BRKB_PPmP, CDOT_ZZZI_S, CDOT_ZZZ_S, CLS_ZPmZ_B,...
14787 printSVERegOp<'b'>(MI, 3, STI, O);
14788 break;
14789 case 1:
14790 // ABS_ZPmZ_D, CLS_ZPmZ_D, CLZ_ZPmZ_D, CNOT_ZPmZ_D, CNT_ZPmZ_D, FABS_ZPmZ...
14791 printSVERegOp<'d'>(MI, 3, STI, O);
14792 return;
14793 break;
14794 case 2:
14795 // ABS_ZPmZ_S, ADDHNT_ZZZ_H, CLS_ZPmZ_S, CLZ_ZPmZ_S, CNOT_ZPmZ_S, CNT_ZPm...
14796 printSVERegOp<'s'>(MI, 3, STI, O);
14797 return;
14798 break;
14799 case 3:
14800 // ABSv16i8, ABSv1i64, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ...
14801 return;
14802 break;
14803 case 4:
14804 // ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD...
14805 O << ", ";
14806 break;
14807 case 5:
14808 // ADDHNB_ZZZ_H, RADDHNB_ZZZ_H, RSUBHNB_ZZZ_H, SUBHNB_ZZZ_H
14809 printSVERegOp<'s'>(MI, 2, STI, O);
14810 return;
14811 break;
14812 case 6:
14813 // ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPm...
14814 O << "/m, ";
14815 break;
14816 case 7:
14817 // ADDP_ZPmZ_H, ADD_ZPmZ_H, ADD_ZZZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ...
14818 printSVERegOp<'h'>(MI, 2, STI, O);
14819 break;
14820 case 8:
14821 // ADD_ZI_H, SQADD_ZI_H, SQSUB_ZI_H, SUBR_ZI_H, SUB_ZI_H, UQADD_ZI_H, UQS...
14822 printImm8OptLsl<uint16_t>(MI, 2, STI, O);
14823 return;
14824 break;
14825 case 9:
14826 // ANDS_PPzPP, AND_PPzPP, BICS_PPzPP, BIC_PPzPP, BRKAS_PPzP, BRKA_PPzP, B...
14827 O << "/z, ";
14828 break;
14829 case 10:
14830 // ASR_WIDE_ZZZ_H, LSL_WIDE_ZZZ_H, LSR_WIDE_ZZZ_H
14831 printSVERegOp<'d'>(MI, 2, STI, O);
14832 return;
14833 break;
14834 case 11:
14835 // ASR_ZZI_H, INDEX_IR_B, INDEX_RR_H, LSL_ZZI_H, LSR_ZZI_H, MUL_ZI_H, RSH...
14836 printOperand(MI, 2, STI, O);
14837 return;
14838 break;
14839 case 12:
14840 // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH...
14841 O << ", [";
14842 break;
14843 case 13:
14844 // CMEQv16i8rz, CMEQv1i64rz, CMEQv2i32rz, CMEQv2i64rz, CMEQv4i16rz, CMEQv...
14845 O << ", #0";
14846 return;
14847 break;
14848 case 14:
14849 // CMLA_ZZZI_H, CMLA_ZZZ_H, EORBT_ZZZ_H, EORTB_ZZZ_H, FCMLA_ZPmZZ_H, FCML...
14850 printSVERegOp<'h'>(MI, 3, STI, O);
14851 break;
14852 case 15:
14853 // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI
14854 O << ", mul ";
14855 printOperand(MI, 2, STI, O);
14856 return;
14857 break;
14858 case 16:
14859 // CPY_ZPmI_B
14860 printImm8OptLsl<int8_t>(MI, 3, STI, O);
14861 return;
14862 break;
14863 case 17:
14864 // CPY_ZPmI_D
14865 printImm8OptLsl<int64_t>(MI, 3, STI, O);
14866 return;
14867 break;
14868 case 18:
14869 // CPY_ZPmI_S
14870 printImm8OptLsl<int32_t>(MI, 3, STI, O);
14871 return;
14872 break;
14873 case 19:
14874 // CPY_ZPmR_B, CPY_ZPmR_D, CPY_ZPmR_S, CPY_ZPmV_B, CPY_ZPmV_D, CPY_ZPmV_S...
14875 printOperand(MI, 3, STI, O);
14876 break;
14877 case 20:
14878 // CPY_ZPzI_H
14879 printImm8OptLsl<int16_t>(MI, 2, STI, O);
14880 return;
14881 break;
14882 case 21:
14883 // CPYi16, CPYi32, CPYi64, CPYi8, DUP_ZZI_B, DUP_ZZI_D, DUP_ZZI_S, DUPv16...
14884 printVectorIndex(MI, 2, STI, O);
14885 return;
14886 break;
14887 case 22:
14888 // EXT_ZZI_B, UMAX_ZI_H, UMIN_ZI_H
14889 printImm(MI, 2, STI, O);
14890 return;
14891 break;
14892 case 23:
14893 // FCMEQv1i16rz, FCMEQv1i32rz, FCMEQv1i64rz, FCMEQv2i32rz, FCMEQv2i64rz, ...
14894 O << ", #0.0";
14895 return;
14896 break;
14897 case 24:
14898 // FCPY_ZPmI_D, FCPY_ZPmI_S
14899 printFPImmOperand(MI, 3, STI, O);
14900 return;
14901 break;
14902 case 25:
14903 // FCVTLv4i16
14904 O << ".4h";
14905 return;
14906 break;
14907 case 26:
14908 // FCVTLv8i16
14909 O << ".8h";
14910 return;
14911 break;
14912 case 27:
14913 // FCVTNv4i32, FCVTXNv4f32
14914 O << ".2d";
14915 return;
14916 break;
14917 case 28:
14918 // INDEX_II_B
14919 printSImm<8>(MI, 2, STI, O);
14920 return;
14921 break;
14922 case 29:
14923 // INDEX_RI_H
14924 printSImm<16>(MI, 2, STI, O);
14925 return;
14926 break;
14927 case 30:
14928 // LDAPRB, LDAPRH, LDAPRW, LDAPRX, LDARB, LDARH, LDARW, LDARX, LDAXRB, LD...
14929 O << ']';
14930 return;
14931 break;
14932 case 31:
14933 // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo...
14934 O << "], ";
14935 break;
14936 case 32:
14937 // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ...
14938 printShifter(MI, 2, STI, O);
14939 return;
14940 break;
14941 case 33:
14942 // PMULLB_ZZZ_H, PMULLT_ZZZ_H, SABDLB_ZZZ_H, SABDLT_ZZZ_H, SADDLBT_ZZZ_H,...
14943 printSVERegOp<'b'>(MI, 2, STI, O);
14944 return;
14945 break;
14946 case 34:
14947 // PRFB_D_SCALED
14948 printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 3, STI, O);
14949 O << ']';
14950 return;
14951 break;
14952 case 35:
14953 // PRFB_D_SXTW_SCALED
14954 printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 3, STI, O);
14955 O << ']';
14956 return;
14957 break;
14958 case 36:
14959 // PRFB_D_UXTW_SCALED
14960 printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 3, STI, O);
14961 O << ']';
14962 return;
14963 break;
14964 case 37:
14965 // PRFB_PRR
14966 printRegWithShiftExtend<false, 8, 'x', 0>(MI, 3, STI, O);
14967 O << ']';
14968 return;
14969 break;
14970 case 38:
14971 // PRFB_S_SXTW_SCALED
14972 printRegWithShiftExtend<true, 8, 'w', 's'>(MI, 3, STI, O);
14973 O << ']';
14974 return;
14975 break;
14976 case 39:
14977 // PRFB_S_UXTW_SCALED
14978 printRegWithShiftExtend<false, 8, 'w', 's'>(MI, 3, STI, O);
14979 O << ']';
14980 return;
14981 break;
14982 case 40:
14983 // PRFD_D_PZI, PRFD_S_PZI
14984 printImmScale<8>(MI, 3, STI, O);
14985 O << ']';
14986 return;
14987 break;
14988 case 41:
14989 // PRFD_D_SCALED
14990 printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 3, STI, O);
14991 O << ']';
14992 return;
14993 break;
14994 case 42:
14995 // PRFD_D_SXTW_SCALED
14996 printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 3, STI, O);
14997 O << ']';
14998 return;
14999 break;
15000 case 43:
15001 // PRFD_D_UXTW_SCALED
15002 printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 3, STI, O);
15003 O << ']';
15004 return;
15005 break;
15006 case 44:
15007 // PRFD_PRR
15008 printRegWithShiftExtend<false, 64, 'x', 0>(MI, 3, STI, O);
15009 O << ']';
15010 return;
15011 break;
15012 case 45:
15013 // PRFD_S_SXTW_SCALED
15014 printRegWithShiftExtend<true, 64, 'w', 's'>(MI, 3, STI, O);
15015 O << ']';
15016 return;
15017 break;
15018 case 46:
15019 // PRFD_S_UXTW_SCALED
15020 printRegWithShiftExtend<false, 64, 'w', 's'>(MI, 3, STI, O);
15021 O << ']';
15022 return;
15023 break;
15024 case 47:
15025 // PRFH_D_PZI, PRFH_S_PZI
15026 printImmScale<2>(MI, 3, STI, O);
15027 O << ']';
15028 return;
15029 break;
15030 case 48:
15031 // PRFH_D_SCALED
15032 printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 3, STI, O);
15033 O << ']';
15034 return;
15035 break;
15036 case 49:
15037 // PRFH_D_SXTW_SCALED
15038 printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 3, STI, O);
15039 O << ']';
15040 return;
15041 break;
15042 case 50:
15043 // PRFH_D_UXTW_SCALED
15044 printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 3, STI, O);
15045 O << ']';
15046 return;
15047 break;
15048 case 51:
15049 // PRFH_PRR
15050 printRegWithShiftExtend<false, 16, 'x', 0>(MI, 3, STI, O);
15051 O << ']';
15052 return;
15053 break;
15054 case 52:
15055 // PRFH_S_SXTW_SCALED
15056 printRegWithShiftExtend<true, 16, 'w', 's'>(MI, 3, STI, O);
15057 O << ']';
15058 return;
15059 break;
15060 case 53:
15061 // PRFH_S_UXTW_SCALED
15062 printRegWithShiftExtend<false, 16, 'w', 's'>(MI, 3, STI, O);
15063 O << ']';
15064 return;
15065 break;
15066 case 54:
15067 // PRFS_PRR
15068 printRegWithShiftExtend<false, 32, 'x', 0>(MI, 3, STI, O);
15069 O << ']';
15070 return;
15071 break;
15072 case 55:
15073 // PRFW_D_PZI, PRFW_S_PZI
15074 printImmScale<4>(MI, 3, STI, O);
15075 O << ']';
15076 return;
15077 break;
15078 case 56:
15079 // PRFW_D_SCALED
15080 printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 3, STI, O);
15081 O << ']';
15082 return;
15083 break;
15084 case 57:
15085 // PRFW_D_SXTW_SCALED
15086 printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 3, STI, O);
15087 O << ']';
15088 return;
15089 break;
15090 case 58:
15091 // PRFW_D_UXTW_SCALED
15092 printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 3, STI, O);
15093 O << ']';
15094 return;
15095 break;
15096 case 59:
15097 // PRFW_S_SXTW_SCALED
15098 printRegWithShiftExtend<true, 32, 'w', 's'>(MI, 3, STI, O);
15099 O << ']';
15100 return;
15101 break;
15102 case 60:
15103 // PRFW_S_UXTW_SCALED
15104 printRegWithShiftExtend<false, 32, 'w', 's'>(MI, 3, STI, O);
15105 O << ']';
15106 return;
15107 break;
15108 case 61:
15109 // RDFFRS_PPz, RDFFR_PPz_REAL
15110 O << "/z";
15111 return;
15112 break;
15113 case 62:
15114 // SHLLv16i8, SHLLv8i8
15115 O << ", #8";
15116 return;
15117 break;
15118 case 63:
15119 // SHLLv2i32, SHLLv4i32
15120 O << ", #32";
15121 return;
15122 break;
15123 case 64:
15124 // SHLLv4i16, SHLLv8i16
15125 O << ", #16";
15126 return;
15127 break;
15128 case 65:
15129 // SPLICE_ZPZZ_H
15130 printTypedVectorList<0,'h'>(MI, 2, STI, O);
15131 return;
15132 break;
15133 case 66:
15134 // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBXv16i8Four, T...
15135 O << ".16b";
15136 return;
15137 break;
15138 case 67:
15139 // TBLv8i8Four, TBLv8i8One, TBLv8i8Three, TBLv8i8Two, TBXv8i8Four, TBXv8i...
15140 O << ".8b";
15141 return;
15142 break;
15143 case 68:
15144 // TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZZ_Q, UZP2_ZZZ_Q, ZIP1_ZZZ_Q, ZIP2_ZZZ_Q
15145 printSVERegOp<'q'>(MI, 2, STI, O);
15146 return;
15147 break;
15148 }
15149
15150
15151 // Fragment 4 encoded into 7 bits for 89 unique commands.
15152 switch ((Bits >> 40) & 127) {
15153 default: llvm_unreachable("Invalid command number.");
15154 case 0:
15155 // ABS_ZPmZ_B, ADD_ZZZ_H, BDEP_ZZZ_H, BEXT_ZZZ_H, BGRP_ZZZ_H, BRKA_PPmP, ...
15156 return;
15157 break;
15158 case 1:
15159 // ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, EORBT_ZZZ_D, EORTB...
15160 printSVERegOp<'d'>(MI, 3, STI, O);
15161 break;
15162 case 2:
15163 // ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, EORBT_ZZZ_S, EORTB_...
15164 printSVERegOp<'s'>(MI, 3, STI, O);
15165 break;
15166 case 3:
15167 // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSXrx64, ADDVL_XXI, ADDXrx6...
15168 printOperand(MI, 2, STI, O);
15169 break;
15170 case 4:
15171 // ADDG, ST2GOffset, STGOffset, STZ2GOffset, STZGOffset, SUBG
15172 printImmScale<16>(MI, 2, STI, O);
15173 break;
15174 case 5:
15175 // ADDHNB_ZZZ_B, CNTP_XPP_H, LASTA_RPZ_H, LASTA_VPZ_H, LASTB_RPZ_H, LASTB...
15176 printSVERegOp<'h'>(MI, 2, STI, O);
15177 break;
15178 case 6:
15179 // ADDHNB_ZZZ_S, ADDP_ZPmZ_D, ADD_ZPmZ_D, ADD_ZZZ_D, AND_ZPmZ_D, AND_ZZZ,...
15180 printSVERegOp<'d'>(MI, 2, STI, O);
15181 break;
15182 case 7:
15183 // ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMMLA_B_ZZI, BFMMLA_B_ZZZ, BFMMLA...
15184 printSVERegOp<'h'>(MI, 3, STI, O);
15185 break;
15186 case 8:
15187 // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2...
15188 printVRegOperand(MI, 2, STI, O);
15189 break;
15190 case 9:
15191 // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BF16DOTlanev4bf1...
15192 printVRegOperand(MI, 3, STI, O);
15193 break;
15194 case 10:
15195 // ADDP_ZPmZ_B, ADD_ZPmZ_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_B, ANDS_PPzPP...
15196 printSVERegOp<'b'>(MI, 2, STI, O);
15197 break;
15198 case 11:
15199 // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID...
15200 O << ", ";
15201 break;
15202 case 12:
15203 // ADDP_ZPmZ_S, ADD_ZPmZ_S, ADD_ZZZ_S, AND_ZPmZ_S, ASRD_ZPmI_S, ASRR_ZPmZ...
15204 printSVERegOp<'s'>(MI, 2, STI, O);
15205 break;
15206 case 13:
15207 // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri
15208 printAddSubImm(MI, 2, STI, O);
15209 return;
15210 break;
15211 case 14:
15212 // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI...
15213 printShiftedRegister(MI, 2, STI, O);
15214 return;
15215 break;
15216 case 15:
15217 // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx
15218 printExtendedRegister(MI, 2, STI, O);
15219 return;
15220 break;
15221 case 16:
15222 // ADD_ZI_B, SQADD_ZI_B, SQSUB_ZI_B, SUBR_ZI_B, SUB_ZI_B, UQADD_ZI_B, UQS...
15223 printImm8OptLsl<uint8_t>(MI, 2, STI, O);
15224 return;
15225 break;
15226 case 17:
15227 // ADD_ZI_D, SQADD_ZI_D, SQSUB_ZI_D, SUBR_ZI_D, SUB_ZI_D, UQADD_ZI_D, UQS...
15228 printImm8OptLsl<uint64_t>(MI, 2, STI, O);
15229 return;
15230 break;
15231 case 18:
15232 // ADD_ZI_S, SQADD_ZI_S, SQSUB_ZI_S, SUBR_ZI_S, SUB_ZI_S, UQADD_ZI_S, UQS...
15233 printImm8OptLsl<uint32_t>(MI, 2, STI, O);
15234 return;
15235 break;
15236 case 19:
15237 // ADR_LSL_ZZZ_D_0
15238 printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 2, STI, O);
15239 O << ']';
15240 return;
15241 break;
15242 case 20:
15243 // ADR_LSL_ZZZ_D_1
15244 printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 2, STI, O);
15245 O << ']';
15246 return;
15247 break;
15248 case 21:
15249 // ADR_LSL_ZZZ_D_2
15250 printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 2, STI, O);
15251 O << ']';
15252 return;
15253 break;
15254 case 22:
15255 // ADR_LSL_ZZZ_D_3
15256 printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 2, STI, O);
15257 O << ']';
15258 return;
15259 break;
15260 case 23:
15261 // ADR_LSL_ZZZ_S_0
15262 printRegWithShiftExtend<false, 8, 'x', 's'>(MI, 2, STI, O);
15263 O << ']';
15264 return;
15265 break;
15266 case 24:
15267 // ADR_LSL_ZZZ_S_1
15268 printRegWithShiftExtend<false, 16, 'x', 's'>(MI, 2, STI, O);
15269 O << ']';
15270 return;
15271 break;
15272 case 25:
15273 // ADR_LSL_ZZZ_S_2
15274 printRegWithShiftExtend<false, 32, 'x', 's'>(MI, 2, STI, O);
15275 O << ']';
15276 return;
15277 break;
15278 case 26:
15279 // ADR_LSL_ZZZ_S_3
15280 printRegWithShiftExtend<false, 64, 'x', 's'>(MI, 2, STI, O);
15281 O << ']';
15282 return;
15283 break;
15284 case 27:
15285 // ADR_SXTW_ZZZ_D_0
15286 printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 2, STI, O);
15287 O << ']';
15288 return;
15289 break;
15290 case 28:
15291 // ADR_SXTW_ZZZ_D_1
15292 printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 2, STI, O);
15293 O << ']';
15294 return;
15295 break;
15296 case 29:
15297 // ADR_SXTW_ZZZ_D_2
15298 printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 2, STI, O);
15299 O << ']';
15300 return;
15301 break;
15302 case 30:
15303 // ADR_SXTW_ZZZ_D_3
15304 printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 2, STI, O);
15305 O << ']';
15306 return;
15307 break;
15308 case 31:
15309 // ADR_UXTW_ZZZ_D_0
15310 printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 2, STI, O);
15311 O << ']';
15312 return;
15313 break;
15314 case 32:
15315 // ADR_UXTW_ZZZ_D_1
15316 printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 2, STI, O);
15317 O << ']';
15318 return;
15319 break;
15320 case 33:
15321 // ADR_UXTW_ZZZ_D_2
15322 printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 2, STI, O);
15323 O << ']';
15324 return;
15325 break;
15326 case 34:
15327 // ADR_UXTW_ZZZ_D_3
15328 printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 2, STI, O);
15329 O << ']';
15330 return;
15331 break;
15332 case 35:
15333 // ANDSWri, ANDWri, EORWri, ORRWri
15334 printLogicalImm<int32_t>(MI, 2, STI, O);
15335 return;
15336 break;
15337 case 36:
15338 // ANDSXri, ANDXri, AND_ZI, EORXri, EOR_ZI, ORRXri, ORR_ZI
15339 printLogicalImm<int64_t>(MI, 2, STI, O);
15340 return;
15341 break;
15342 case 37:
15343 // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C...
15344 printOperand(MI, 3, STI, O);
15345 break;
15346 case 38:
15347 // CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, FMLA_ZZZI_H, FMLS_ZZZI_H, MLA_...
15348 printVectorIndex(MI, 4, STI, O);
15349 break;
15350 case 39:
15351 // CPY_ZPzI_B
15352 printImm8OptLsl<int8_t>(MI, 2, STI, O);
15353 return;
15354 break;
15355 case 40:
15356 // CPY_ZPzI_D
15357 printImm8OptLsl<int64_t>(MI, 2, STI, O);
15358 return;
15359 break;
15360 case 41:
15361 // CPY_ZPzI_S
15362 printImm8OptLsl<int32_t>(MI, 2, STI, O);
15363 return;
15364 break;
15365 case 42:
15366 // FCMEQ_PPzZ0_H, FCMGE_PPzZ0_H, FCMGT_PPzZ0_H, FCMLE_PPzZ0_H, FCMLT_PPzZ...
15367 O << ", #0.0";
15368 return;
15369 break;
15370 case 43:
15371 // FMUL_ZZZI_H, MUL_ZZZI_H, SQDMULH_ZZZI_H, SQRDMULH_ZZZI_H
15372 printVectorIndex(MI, 3, STI, O);
15373 return;
15374 break;
15375 case 44:
15376 // GLD1B_D_REAL, GLD1D_REAL, GLD1H_D_REAL, GLD1SB_D_REAL, GLD1SH_D_REAL, ...
15377 printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 3, STI, O);
15378 O << ']';
15379 return;
15380 break;
15381 case 45:
15382 // GLD1B_D_SXTW_REAL, GLD1D_SXTW_REAL, GLD1H_D_SXTW_REAL, GLD1SB_D_SXTW_R...
15383 printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 3, STI, O);
15384 O << ']';
15385 return;
15386 break;
15387 case 46:
15388 // GLD1B_D_UXTW_REAL, GLD1D_UXTW_REAL, GLD1H_D_UXTW_REAL, GLD1SB_D_UXTW_R...
15389 printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 3, STI, O);
15390 O << ']';
15391 return;
15392 break;
15393 case 47:
15394 // GLD1B_S_SXTW_REAL, GLD1H_S_SXTW_REAL, GLD1SB_S_SXTW_REAL, GLD1SH_S_SXT...
15395 printRegWithShiftExtend<true, 8, 'w', 's'>(MI, 3, STI, O);
15396 O << ']';
15397 return;
15398 break;
15399 case 48:
15400 // GLD1B_S_UXTW_REAL, GLD1H_S_UXTW_REAL, GLD1SB_S_UXTW_REAL, GLD1SH_S_UXT...
15401 printRegWithShiftExtend<false, 8, 'w', 's'>(MI, 3, STI, O);
15402 O << ']';
15403 return;
15404 break;
15405 case 49:
15406 // GLD1D_IMM_REAL, GLDFF1D_IMM_REAL, LD1RD_IMM, LDRAAwriteback, LDRABwrit...
15407 printImmScale<8>(MI, 3, STI, O);
15408 break;
15409 case 50:
15410 // GLD1D_SCALED_REAL, GLDFF1D_SCALED_REAL, SST1D_SCALED_SCALED_REAL
15411 printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 3, STI, O);
15412 O << ']';
15413 return;
15414 break;
15415 case 51:
15416 // GLD1D_SXTW_SCALED_REAL, GLDFF1D_SXTW_SCALED_REAL, SST1D_SXTW_SCALED
15417 printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 3, STI, O);
15418 O << ']';
15419 return;
15420 break;
15421 case 52:
15422 // GLD1D_UXTW_SCALED_REAL, GLDFF1D_UXTW_SCALED_REAL, SST1D_UXTW_SCALED
15423 printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 3, STI, O);
15424 O << ']';
15425 return;
15426 break;
15427 case 53:
15428 // GLD1H_D_IMM_REAL, GLD1H_S_IMM_REAL, GLD1SH_D_IMM_REAL, GLD1SH_S_IMM_RE...
15429 printImmScale<2>(MI, 3, STI, O);
15430 break;
15431 case 54:
15432 // GLD1H_D_SCALED_REAL, GLD1SH_D_SCALED_REAL, GLDFF1H_D_SCALED_REAL, GLDF...
15433 printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 3, STI, O);
15434 O << ']';
15435 return;
15436 break;
15437 case 55:
15438 // GLD1H_D_SXTW_SCALED_REAL, GLD1SH_D_SXTW_SCALED_REAL, GLDFF1H_D_SXTW_SC...
15439 printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 3, STI, O);
15440 O << ']';
15441 return;
15442 break;
15443 case 56:
15444 // GLD1H_D_UXTW_SCALED_REAL, GLD1SH_D_UXTW_SCALED_REAL, GLDFF1H_D_UXTW_SC...
15445 printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 3, STI, O);
15446 O << ']';
15447 return;
15448 break;
15449 case 57:
15450 // GLD1H_S_SXTW_SCALED_REAL, GLD1SH_S_SXTW_SCALED_REAL, GLDFF1H_S_SXTW_SC...
15451 printRegWithShiftExtend<true, 16, 'w', 's'>(MI, 3, STI, O);
15452 O << ']';
15453 return;
15454 break;
15455 case 58:
15456 // GLD1H_S_UXTW_SCALED_REAL, GLD1SH_S_UXTW_SCALED_REAL, GLDFF1H_S_UXTW_SC...
15457 printRegWithShiftExtend<false, 16, 'w', 's'>(MI, 3, STI, O);
15458 O << ']';
15459 return;
15460 break;
15461 case 59:
15462 // GLD1SW_D_IMM_REAL, GLD1W_D_IMM_REAL, GLD1W_IMM_REAL, GLDFF1SW_D_IMM_RE...
15463 printImmScale<4>(MI, 3, STI, O);
15464 break;
15465 case 60:
15466 // GLD1SW_D_SCALED_REAL, GLD1W_D_SCALED_REAL, GLDFF1SW_D_SCALED_REAL, GLD...
15467 printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 3, STI, O);
15468 O << ']';
15469 return;
15470 break;
15471 case 61:
15472 // GLD1SW_D_SXTW_SCALED_REAL, GLD1W_D_SXTW_SCALED_REAL, GLDFF1SW_D_SXTW_S...
15473 printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 3, STI, O);
15474 O << ']';
15475 return;
15476 break;
15477 case 62:
15478 // GLD1SW_D_UXTW_SCALED_REAL, GLD1W_D_UXTW_SCALED_REAL, GLDFF1SW_D_UXTW_S...
15479 printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 3, STI, O);
15480 O << ']';
15481 return;
15482 break;
15483 case 63:
15484 // GLD1W_SXTW_SCALED_REAL, GLDFF1W_SXTW_SCALED_REAL, SST1W_SXTW_SCALED
15485 printRegWithShiftExtend<true, 32, 'w', 's'>(MI, 3, STI, O);
15486 O << ']';
15487 return;
15488 break;
15489 case 64:
15490 // GLD1W_UXTW_SCALED_REAL, GLDFF1W_UXTW_SCALED_REAL, SST1W_UXTW_SCALED
15491 printRegWithShiftExtend<false, 32, 'w', 's'>(MI, 3, STI, O);
15492 O << ']';
15493 return;
15494 break;
15495 case 65:
15496 // INDEX_RI_B
15497 printSImm<8>(MI, 2, STI, O);
15498 return;
15499 break;
15500 case 66:
15501 // LD1B, LD1B_D, LD1B_H, LD1B_S, LD1RO_B, LD1RQ_B, LD1SB_D, LD1SB_H, LD1S...
15502 printRegWithShiftExtend<false, 8, 'x', 0>(MI, 3, STI, O);
15503 O << ']';
15504 return;
15505 break;
15506 case 67:
15507 // LD1D, LD1RO_D, LD1RQ_D, LD2D, LD3D, LD4D, LDFF1D_REAL, LDNT1D_ZRR, ST1...
15508 printRegWithShiftExtend<false, 64, 'x', 0>(MI, 3, STI, O);
15509 O << ']';
15510 return;
15511 break;
15512 case 68:
15513 // LD1H, LD1H_D, LD1H_S, LD1RO_H, LD1RQ_H, LD1SH_D, LD1SH_S, LD2H, LD3H, ...
15514 printRegWithShiftExtend<false, 16, 'x', 0>(MI, 3, STI, O);
15515 O << ']';
15516 return;
15517 break;
15518 case 69:
15519 // LD1RO_B_IMM, LD1RO_D_IMM, LD1RO_H_IMM, LD1RO_W_IMM
15520 printImmScale<32>(MI, 3, STI, O);
15521 O << ']';
15522 return;
15523 break;
15524 case 70:
15525 // LD1RO_W, LD1RQ_W, LD1SW_D, LD1W, LD1W_D, LD2W, LD3W, LD4W, LDFF1SW_D_R...
15526 printRegWithShiftExtend<false, 32, 'x', 0>(MI, 3, STI, O);
15527 O << ']';
15528 return;
15529 break;
15530 case 71:
15531 // LD1RQ_B_IMM, LD1RQ_D_IMM, LD1RQ_H_IMM, LD1RQ_W_IMM, LDG, ST2GPostIndex...
15532 printImmScale<16>(MI, 3, STI, O);
15533 break;
15534 case 72:
15535 // LD3B_IMM, LD3D_IMM, LD3H_IMM, LD3W_IMM, ST3B_IMM, ST3D_IMM, ST3H_IMM, ...
15536 printImmScale<3>(MI, 3, STI, O);
15537 O << ", mul vl]";
15538 return;
15539 break;
15540 case 73:
15541 // LDRAAindexed, LDRABindexed
15542 printImmScale<8>(MI, 2, STI, O);
15543 O << ']';
15544 return;
15545 break;
15546 case 74:
15547 // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui
15548 printUImm12Offset<1>(MI, 2, STI, O);
15549 O << ']';
15550 return;
15551 break;
15552 case 75:
15553 // LDRDui, LDRXui, PRFMui, STRDui, STRXui
15554 printUImm12Offset<8>(MI, 2, STI, O);
15555 O << ']';
15556 return;
15557 break;
15558 case 76:
15559 // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui
15560 printUImm12Offset<2>(MI, 2, STI, O);
15561 O << ']';
15562 return;
15563 break;
15564 case 77:
15565 // LDRQui, STRQui
15566 printUImm12Offset<16>(MI, 2, STI, O);
15567 O << ']';
15568 return;
15569 break;
15570 case 78:
15571 // LDRSWui, LDRSui, LDRWui, STRSui, STRWui
15572 printUImm12Offset<4>(MI, 2, STI, O);
15573 O << ']';
15574 return;
15575 break;
15576 case 79:
15577 // MAD_ZPmZZ_B, MLA_ZPmZZ_B, MLS_ZPmZZ_B, MSB_ZPmZZ_B
15578 printSVERegOp<'b'>(MI, 3, STI, O);
15579 O << ", ";
15580 printSVERegOp<'b'>(MI, 4, STI, O);
15581 return;
15582 break;
15583 case 80:
15584 // PRFB_D_PZI, PRFB_S_PZI
15585 O << ']';
15586 return;
15587 break;
15588 case 81:
15589 // PRFB_PRI, PRFD_PRI, PRFH_PRI, PRFW_PRI
15590 O << ", mul vl]";
15591 return;
15592 break;
15593 case 82:
15594 // SPLICE_ZPZZ_B
15595 printTypedVectorList<0,'b'>(MI, 2, STI, O);
15596 return;
15597 break;
15598 case 83:
15599 // SPLICE_ZPZZ_D
15600 printTypedVectorList<0,'d'>(MI, 2, STI, O);
15601 return;
15602 break;
15603 case 84:
15604 // SPLICE_ZPZZ_S
15605 printTypedVectorList<0,'s'>(MI, 2, STI, O);
15606 return;
15607 break;
15608 case 85:
15609 // SQDECP_XPWd_B, SQDECP_XPWd_D, SQDECP_XPWd_H, SQDECP_XPWd_S, SQINCP_XPW...
15610 printGPR64as32(MI, 2, STI, O);
15611 return;
15612 break;
15613 case 86:
15614 // SYSLxt
15615 printSysCROperand(MI, 2, STI, O);
15616 O << ", ";
15617 printSysCROperand(MI, 3, STI, O);
15618 O << ", ";
15619 printOperand(MI, 4, STI, O);
15620 return;
15621 break;
15622 case 87:
15623 // TBNZW, TBNZX, TBZW, TBZX
15624 printAlignedLabel(MI, Address, 2, STI, O);
15625 return;
15626 break;
15627 case 88:
15628 // UMAX_ZI_B, UMAX_ZI_D, UMAX_ZI_S, UMIN_ZI_B, UMIN_ZI_D, UMIN_ZI_S
15629 printImm(MI, 2, STI, O);
15630 return;
15631 break;
15632 }
15633
15634
15635 // Fragment 5 encoded into 5 bits for 21 unique commands.
15636 switch ((Bits >> 47) & 31) {
15637 default: llvm_unreachable("Invalid command number.");
15638 case 0:
15639 // ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD...
15640 return;
15641 break;
15642 case 1:
15643 // ADDG, ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, A...
15644 O << ", ";
15645 break;
15646 case 2:
15647 // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BIC_ZPmZ...
15648 printSVERegOp<'h'>(MI, 3, STI, O);
15649 break;
15650 case 3:
15651 // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64
15652 printArithExtend(MI, 3, STI, O);
15653 return;
15654 break;
15655 case 4:
15656 // ASRD_ZPmI_H, ASR_ZPmI_H, CMPEQ_PPzZI_H, CMPGE_PPzZI_H, CMPGT_PPzZI_H, ...
15657 printOperand(MI, 3, STI, O);
15658 return;
15659 break;
15660 case 5:
15661 // ASR_WIDE_ZPmZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_WIDE_PPzZZ_H, CMPGT_WIDE_PP...
15662 printSVERegOp<'d'>(MI, 3, STI, O);
15663 return;
15664 break;
15665 case 6:
15666 // BF16DOTlanev4bf16, BF16DOTlanev8bf16, BFDOT_ZZI, BFMMLA_B_ZZI, BFMMLA_...
15667 printVectorIndex(MI, 4, STI, O);
15668 break;
15669 case 7:
15670 // CADD_ZZI_H, SQCADD_ZZI_H
15671 printComplexRotationOp<180, 90>(MI, 3, STI, O);
15672 return;
15673 break;
15674 case 8:
15675 // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH...
15676 O << ']';
15677 return;
15678 break;
15679 case 9:
15680 // CDOT_ZZZ_S, CMLA_ZZZ_B, CMLA_ZZZ_H, SQRDCMLAH_ZZZ_B, SQRDCMLAH_ZZZ_H
15681 printComplexRotationOp<90, 0>(MI, 4, STI, O);
15682 return;
15683 break;
15684 case 10:
15685 // CMPHI_PPzZI_H, CMPHS_PPzZI_H, CMPLO_PPzZI_H, CMPLS_PPzZI_H
15686 printImm(MI, 3, STI, O);
15687 return;
15688 break;
15689 case 11:
15690 // FADD_ZPmI_H, FSUBR_ZPmI_H, FSUB_ZPmI_H
15691 printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, 3, STI, O);
15692 return;
15693 break;
15694 case 12:
15695 // FCMEQ_PPzZ0_D, FCMEQ_PPzZ0_S, FCMGE_PPzZ0_D, FCMGE_PPzZ0_S, FCMGT_PPzZ...
15696 O << ", #0.0";
15697 return;
15698 break;
15699 case 13:
15700 // FCMLA_ZPmZZ_H, FMAD_ZPmZZ_H, FMLA_ZPmZZ_H, FMLS_ZPmZZ_H, FMSB_ZPmZZ_H,...
15701 printSVERegOp<'h'>(MI, 4, STI, O);
15702 break;
15703 case 14:
15704 // FMAXNM_ZPmI_H, FMAX_ZPmI_H, FMINNM_ZPmI_H, FMIN_ZPmI_H
15705 printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, 3, STI, O);
15706 return;
15707 break;
15708 case 15:
15709 // FMULXv1i16_indexed, FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32...
15710 printVectorIndex(MI, 3, STI, O);
15711 return;
15712 break;
15713 case 16:
15714 // FMUL_ZPmI_H
15715 printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, 3, STI, O);
15716 return;
15717 break;
15718 case 17:
15719 // LD1B_D_IMM_REAL, LD1B_H_IMM_REAL, LD1B_IMM_REAL, LD1B_S_IMM_REAL, LD1D...
15720 O << ", mul vl]";
15721 return;
15722 break;
15723 case 18:
15724 // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STGPpost,...
15725 O << "], ";
15726 break;
15727 case 19:
15728 // LDRAAwriteback, LDRABwriteback, LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, ...
15729 O << "]!";
15730 return;
15731 break;
15732 case 20:
15733 // STLXPW, STLXPX, STXPW, STXPX
15734 O << ", [";
15735 printOperand(MI, 3, STI, O);
15736 O << ']';
15737 return;
15738 break;
15739 }
15740
15741
15742 // Fragment 6 encoded into 6 bits for 35 unique commands.
15743 switch ((Bits >> 52) & 63) {
15744 default: llvm_unreachable("Invalid command number.");
15745 case 0:
15746 // ADDG, ASRD_ZPmI_B, ASRD_ZPmI_D, ASRD_ZPmI_S, ASR_ZPmI_B, ASR_ZPmI_D, A...
15747 printOperand(MI, 3, STI, O);
15748 return;
15749 break;
15750 case 1:
15751 // ADDP_ZPmZ_B, ADD_ZPmZ_B, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B, ASRR_ZPmZ_...
15752 printSVERegOp<'b'>(MI, 3, STI, O);
15753 return;
15754 break;
15755 case 2:
15756 // ADDP_ZPmZ_D, ADD_ZPmZ_D, AND_ZPmZ_D, ASRR_ZPmZ_D, ASR_WIDE_ZPmZ_B, ASR...
15757 printSVERegOp<'d'>(MI, 3, STI, O);
15758 break;
15759 case 3:
15760 // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BF16DOTl...
15761 return;
15762 break;
15763 case 4:
15764 // ADDP_ZPmZ_S, ADD_ZPmZ_S, AND_ZPmZ_S, ASRR_ZPmZ_S, ASR_ZPmZ_S, BIC_ZPmZ...
15765 printSVERegOp<'s'>(MI, 3, STI, O);
15766 break;
15767 case 5:
15768 // BCAX, EOR3, SM3SS1
15769 printVRegOperand(MI, 3, STI, O);
15770 return;
15771 break;
15772 case 6:
15773 // BFMWri, BFMXri
15774 printOperand(MI, 4, STI, O);
15775 return;
15776 break;
15777 case 7:
15778 // CADD_ZZI_B, CADD_ZZI_D, CADD_ZZI_S, FCADDv2f32, FCADDv2f64, FCADDv4f16...
15779 printComplexRotationOp<180, 90>(MI, 3, STI, O);
15780 return;
15781 break;
15782 case 8:
15783 // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr...
15784 printCondCode(MI, 3, STI, O);
15785 return;
15786 break;
15787 case 9:
15788 // CDOT_ZZZI_D, CMLA_ZZZI_S, FCADD_ZPmZ_H, FCMLA_ZPmZZ_H, FCMLA_ZZZI_S, F...
15789 O << ", ";
15790 break;
15791 case 10:
15792 // CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, SQRDCMLAH_ZZZI_H
15793 printComplexRotationOp<90, 0>(MI, 5, STI, O);
15794 return;
15795 break;
15796 case 11:
15797 // CDOT_ZZZ_D, CMLA_ZZZ_D, CMLA_ZZZ_S, FCMLAv2f32, FCMLAv2f64, FCMLAv4f16...
15798 printComplexRotationOp<90, 0>(MI, 4, STI, O);
15799 return;
15800 break;
15801 case 12:
15802 // CLASTA_RPZ_H, CLASTA_VPZ_H, CLASTB_RPZ_H, CLASTB_VPZ_H
15803 printSVERegOp<'h'>(MI, 3, STI, O);
15804 return;
15805 break;
15806 case 13:
15807 // CMPHI_PPzZI_B, CMPHI_PPzZI_D, CMPHI_PPzZI_S, CMPHS_PPzZI_B, CMPHS_PPzZ...
15808 printImm(MI, 3, STI, O);
15809 return;
15810 break;
15811 case 14:
15812 // FADD_ZPmI_D, FADD_ZPmI_S, FSUBR_ZPmI_D, FSUBR_ZPmI_S, FSUB_ZPmI_D, FSU...
15813 printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, 3, STI, O);
15814 return;
15815 break;
15816 case 15:
15817 // FCMLA_ZPmZZ_D, FMAD_ZPmZZ_D, FMLA_ZPmZZ_D, FMLS_ZPmZZ_D, FMSB_ZPmZZ_D,...
15818 printSVERegOp<'d'>(MI, 4, STI, O);
15819 break;
15820 case 16:
15821 // FCMLA_ZPmZZ_S, FMAD_ZPmZZ_S, FMLA_ZPmZZ_S, FMLS_ZPmZZ_S, FMSB_ZPmZZ_S,...
15822 printSVERegOp<'s'>(MI, 4, STI, O);
15823 break;
15824 case 17:
15825 // FMAXNM_ZPmI_D, FMAXNM_ZPmI_S, FMAX_ZPmI_D, FMAX_ZPmI_S, FMINNM_ZPmI_D,...
15826 printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, 3, STI, O);
15827 return;
15828 break;
15829 case 18:
15830 // FMUL_ZPmI_D, FMUL_ZPmI_S
15831 printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, 3, STI, O);
15832 return;
15833 break;
15834 case 19:
15835 // LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi
15836 printImmScale<8>(MI, 3, STI, O);
15837 O << ']';
15838 return;
15839 break;
15840 case 20:
15841 // LDNPQi, LDPQi, STGPi, STNPQi, STPQi
15842 printImmScale<16>(MI, 3, STI, O);
15843 O << ']';
15844 return;
15845 break;
15846 case 21:
15847 // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi
15848 printImmScale<4>(MI, 3, STI, O);
15849 O << ']';
15850 return;
15851 break;
15852 case 22:
15853 // LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP...
15854 printImmScale<8>(MI, 4, STI, O);
15855 break;
15856 case 23:
15857 // LDPQpost, LDPQpre, STGPpost, STGPpre, STPQpost, STPQpre
15858 printImmScale<16>(MI, 4, STI, O);
15859 break;
15860 case 24:
15861 // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S...
15862 printImmScale<4>(MI, 4, STI, O);
15863 break;
15864 case 25:
15865 // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW
15866 printMemExtend<'w', 8>(MI, 3, STI, O);
15867 O << ']';
15868 return;
15869 break;
15870 case 26:
15871 // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX
15872 printMemExtend<'x', 8>(MI, 3, STI, O);
15873 O << ']';
15874 return;
15875 break;
15876 case 27:
15877 // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW
15878 printMemExtend<'w', 64>(MI, 3, STI, O);
15879 O << ']';
15880 return;
15881 break;
15882 case 28:
15883 // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX
15884 printMemExtend<'x', 64>(MI, 3, STI, O);
15885 O << ']';
15886 return;
15887 break;
15888 case 29:
15889 // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW
15890 printMemExtend<'w', 16>(MI, 3, STI, O);
15891 O << ']';
15892 return;
15893 break;
15894 case 30:
15895 // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX
15896 printMemExtend<'x', 16>(MI, 3, STI, O);
15897 O << ']';
15898 return;
15899 break;
15900 case 31:
15901 // LDRQroW, STRQroW
15902 printMemExtend<'w', 128>(MI, 3, STI, O);
15903 O << ']';
15904 return;
15905 break;
15906 case 32:
15907 // LDRQroX, STRQroX
15908 printMemExtend<'x', 128>(MI, 3, STI, O);
15909 O << ']';
15910 return;
15911 break;
15912 case 33:
15913 // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW
15914 printMemExtend<'w', 32>(MI, 3, STI, O);
15915 O << ']';
15916 return;
15917 break;
15918 case 34:
15919 // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX
15920 printMemExtend<'x', 32>(MI, 3, STI, O);
15921 O << ']';
15922 return;
15923 break;
15924 }
15925
15926
15927 // Fragment 7 encoded into 3 bits for 5 unique commands.
15928 switch ((Bits >> 58) & 7) {
15929 default: llvm_unreachable("Invalid command number.");
15930 case 0:
15931 // ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_D, ADD_ZPmZ_S, AND_ZPmZ_D, AND_ZPmZ...
15932 return;
15933 break;
15934 case 1:
15935 // CDOT_ZZZI_D, CMLA_ZZZI_S, FCMLA_ZPmZZ_H, FCMLA_ZZZI_S, FCMLAv4f16_inde...
15936 printComplexRotationOp<90, 0>(MI, 5, STI, O);
15937 return;
15938 break;
15939 case 2:
15940 // FCADD_ZPmZ_D, FCADD_ZPmZ_S, FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S
15941 O << ", ";
15942 break;
15943 case 3:
15944 // FCADD_ZPmZ_H
15945 printComplexRotationOp<180, 90>(MI, 4, STI, O);
15946 return;
15947 break;
15948 case 4:
15949 // LDPDpre, LDPQpre, LDPSWpre, LDPSpre, LDPWpre, LDPXpre, STGPpre, STPDpr...
15950 O << "]!";
15951 return;
15952 break;
15953 }
15954
15955
15956 // Fragment 8 encoded into 1 bits for 2 unique commands.
15957 if ((Bits >> 61) & 1) {
15958 // FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S
15959 printComplexRotationOp<90, 0>(MI, 5, STI, O);
15960 return;
15961 } else {
15962 // FCADD_ZPmZ_D, FCADD_ZPmZ_S
15963 printComplexRotationOp<180, 90>(MI, 4, STI, O);
15964 return;
15965 }
15966
15967}
15968
15969
15970/// getRegisterName - This method is automatically generated by tblgen
15971/// from the register set description. This returns the assembler name
15972/// for the specified register.
15973const char *AArch64AppleInstPrinter::
15974getRegisterName(unsigned RegNo, unsigned AltIdx) {
15975 assert(RegNo && RegNo < 642 && "Invalid register number!");
15976
15977
15978#ifdef __GNUC__
15979#pragma GCC diagnostic push
15980#pragma GCC diagnostic ignored "-Woverlength-strings"
15981#endif
15982 static const char AsmStrsNoRegAltName[] = {
15983 /* 0 */ "D7_D8_D9_D10\0"
15984 /* 13 */ "Q7_Q8_Q9_Q10\0"
15985 /* 26 */ "Z7_Z8_Z9_Z10\0"
15986 /* 39 */ "b10\0"
15987 /* 43 */ "d10\0"
15988 /* 47 */ "h10\0"
15989 /* 51 */ "p10\0"
15990 /* 55 */ "q10\0"
15991 /* 59 */ "s10\0"
15992 /* 63 */ "w10\0"
15993 /* 67 */ "x10\0"
15994 /* 71 */ "z10\0"
15995 /* 75 */ "D17_D18_D19_D20\0"
15996 /* 91 */ "Q17_Q18_Q19_Q20\0"
15997 /* 107 */ "Z17_Z18_Z19_Z20\0"
15998 /* 123 */ "b20\0"
15999 /* 127 */ "d20\0"
16000 /* 131 */ "h20\0"
16001 /* 135 */ "q20\0"
16002 /* 139 */ "s20\0"
16003 /* 143 */ "w20\0"
16004 /* 147 */ "x20\0"
16005 /* 151 */ "z20\0"
16006 /* 155 */ "D27_D28_D29_D30\0"
16007 /* 171 */ "Q27_Q28_Q29_Q30\0"
16008 /* 187 */ "Z27_Z28_Z29_Z30\0"
16009 /* 203 */ "b30\0"
16010 /* 207 */ "d30\0"
16011 /* 211 */ "h30\0"
16012 /* 215 */ "q30\0"
16013 /* 219 */ "s30\0"
16014 /* 223 */ "w30\0"
16015 /* 227 */ "x30\0"
16016 /* 231 */ "z30\0"
16017 /* 235 */ "D29_D30_D31_D0\0"
16018 /* 250 */ "Q29_Q30_Q31_Q0\0"
16019 /* 265 */ "Z29_Z30_Z31_Z0\0"
16020 /* 280 */ "b0\0"
16021 /* 283 */ "d0\0"
16022 /* 286 */ "h0\0"
16023 /* 289 */ "p0\0"
16024 /* 292 */ "q0\0"
16025 /* 295 */ "s0\0"
16026 /* 298 */ "w0\0"
16027 /* 301 */ "x0\0"
16028 /* 304 */ "z0\0"
16029 /* 307 */ "D8_D9_D10_D11\0"
16030 /* 321 */ "Q8_Q9_Q10_Q11\0"
16031 /* 335 */ "W10_W11\0"
16032 /* 343 */ "X4_X5_X6_X7_X8_X9_X10_X11\0"
16033 /* 369 */ "Z8_Z9_Z10_Z11\0"
16034 /* 383 */ "b11\0"
16035 /* 387 */ "d11\0"
16036 /* 391 */ "h11\0"
16037 /* 395 */ "p11\0"
16038 /* 399 */ "q11\0"
16039 /* 403 */ "s11\0"
16040 /* 407 */ "w11\0"
16041 /* 411 */ "x11\0"
16042 /* 415 */ "z11\0"
16043 /* 419 */ "D18_D19_D20_D21\0"
16044 /* 435 */ "Q18_Q19_Q20_Q21\0"
16045 /* 451 */ "W20_W21\0"
16046 /* 459 */ "X14_X15_X16_X17_X18_X19_X20_X21\0"
16047 /* 491 */ "Z18_Z19_Z20_Z21\0"
16048 /* 507 */ "b21\0"
16049 /* 511 */ "d21\0"
16050 /* 515 */ "h21\0"
16051 /* 519 */ "q21\0"
16052 /* 523 */ "s21\0"
16053 /* 527 */ "w21\0"
16054 /* 531 */ "x21\0"
16055 /* 535 */ "z21\0"
16056 /* 539 */ "D28_D29_D30_D31\0"
16057 /* 555 */ "Q28_Q29_Q30_Q31\0"
16058 /* 571 */ "Z28_Z29_Z30_Z31\0"
16059 /* 587 */ "b31\0"
16060 /* 591 */ "d31\0"
16061 /* 595 */ "h31\0"
16062 /* 599 */ "q31\0"
16063 /* 603 */ "s31\0"
16064 /* 607 */ "z31\0"
16065 /* 611 */ "D30_D31_D0_D1\0"
16066 /* 625 */ "Q30_Q31_Q0_Q1\0"
16067 /* 639 */ "W0_W1\0"
16068 /* 645 */ "X0_X1\0"
16069 /* 651 */ "Z30_Z31_Z0_Z1\0"
16070 /* 665 */ "b1\0"
16071 /* 668 */ "d1\0"
16072 /* 671 */ "h1\0"
16073 /* 674 */ "p1\0"
16074 /* 677 */ "q1\0"
16075 /* 680 */ "s1\0"
16076 /* 683 */ "w1\0"
16077 /* 686 */ "x1\0"
16078 /* 689 */ "z1\0"
16079 /* 692 */ "D9_D10_D11_D12\0"
16080 /* 707 */ "Q9_Q10_Q11_Q12\0"
16081 /* 722 */ "Z9_Z10_Z11_Z12\0"
16082 /* 737 */ "b12\0"
16083 /* 741 */ "d12\0"
16084 /* 745 */ "h12\0"
16085 /* 749 */ "p12\0"
16086 /* 753 */ "q12\0"
16087 /* 757 */ "s12\0"
16088 /* 761 */ "w12\0"
16089 /* 765 */ "x12\0"
16090 /* 769 */ "z12\0"
16091 /* 773 */ "D19_D20_D21_D22\0"
16092 /* 789 */ "Q19_Q20_Q21_Q22\0"
16093 /* 805 */ "Z19_Z20_Z21_Z22\0"
16094 /* 821 */ "b22\0"
16095 /* 825 */ "d22\0"
16096 /* 829 */ "h22\0"
16097 /* 833 */ "q22\0"
16098 /* 837 */ "s22\0"
16099 /* 841 */ "w22\0"
16100 /* 845 */ "x22\0"
16101 /* 849 */ "z22\0"
16102 /* 853 */ "D31_D0_D1_D2\0"
16103 /* 866 */ "Q31_Q0_Q1_Q2\0"
16104 /* 879 */ "Z31_Z0_Z1_Z2\0"
16105 /* 892 */ "b2\0"
16106 /* 895 */ "d2\0"
16107 /* 898 */ "h2\0"
16108 /* 901 */ "p2\0"
16109 /* 904 */ "q2\0"
16110 /* 907 */ "s2\0"
16111 /* 910 */ "w2\0"
16112 /* 913 */ "x2\0"
16113 /* 916 */ "z2\0"
16114 /* 919 */ "D10_D11_D12_D13\0"
16115 /* 935 */ "Q10_Q11_Q12_Q13\0"
16116 /* 951 */ "W12_W13\0"
16117 /* 959 */ "X6_X7_X8_X9_X10_X11_X12_X13\0"
16118 /* 987 */ "Z10_Z11_Z12_Z13\0"
16119 /* 1003 */ "b13\0"
16120 /* 1007 */ "d13\0"
16121 /* 1011 */ "h13\0"
16122 /* 1015 */ "p13\0"
16123 /* 1019 */ "q13\0"
16124 /* 1023 */ "s13\0"
16125 /* 1027 */ "w13\0"
16126 /* 1031 */ "x13\0"
16127 /* 1035 */ "z13\0"
16128 /* 1039 */ "D20_D21_D22_D23\0"
16129 /* 1055 */ "Q20_Q21_Q22_Q23\0"
16130 /* 1071 */ "W22_W23\0"
16131 /* 1079 */ "X16_X17_X18_X19_X20_X21_X22_X23\0"
16132 /* 1111 */ "Z20_Z21_Z22_Z23\0"
16133 /* 1127 */ "b23\0"
16134 /* 1131 */ "d23\0"
16135 /* 1135 */ "h23\0"
16136 /* 1139 */ "q23\0"
16137 /* 1143 */ "s23\0"
16138 /* 1147 */ "w23\0"
16139 /* 1151 */ "x23\0"
16140 /* 1155 */ "z23\0"
16141 /* 1159 */ "D0_D1_D2_D3\0"
16142 /* 1171 */ "Q0_Q1_Q2_Q3\0"
16143 /* 1183 */ "W2_W3\0"
16144 /* 1189 */ "X2_X3\0"
16145 /* 1195 */ "Z0_Z1_Z2_Z3\0"
16146 /* 1207 */ "b3\0"
16147 /* 1210 */ "d3\0"
16148 /* 1213 */ "h3\0"
16149 /* 1216 */ "p3\0"
16150 /* 1219 */ "q3\0"
16151 /* 1222 */ "s3\0"
16152 /* 1225 */ "w3\0"
16153 /* 1228 */ "x3\0"
16154 /* 1231 */ "z3\0"
16155 /* 1234 */ "D11_D12_D13_D14\0"
16156 /* 1250 */ "Q11_Q12_Q13_Q14\0"
16157 /* 1266 */ "Z11_Z12_Z13_Z14\0"
16158 /* 1282 */ "b14\0"
16159 /* 1286 */ "d14\0"
16160 /* 1290 */ "h14\0"
16161 /* 1294 */ "p14\0"
16162 /* 1298 */ "q14\0"
16163 /* 1302 */ "s14\0"
16164 /* 1306 */ "w14\0"
16165 /* 1310 */ "x14\0"
16166 /* 1314 */ "z14\0"
16167 /* 1318 */ "D21_D22_D23_D24\0"
16168 /* 1334 */ "Q21_Q22_Q23_Q24\0"
16169 /* 1350 */ "Z21_Z22_Z23_Z24\0"
16170 /* 1366 */ "b24\0"
16171 /* 1370 */ "d24\0"
16172 /* 1374 */ "h24\0"
16173 /* 1378 */ "q24\0"
16174 /* 1382 */ "s24\0"
16175 /* 1386 */ "w24\0"
16176 /* 1390 */ "x24\0"
16177 /* 1394 */ "z24\0"
16178 /* 1398 */ "D1_D2_D3_D4\0"
16179 /* 1410 */ "Q1_Q2_Q3_Q4\0"
16180 /* 1422 */ "Z1_Z2_Z3_Z4\0"
16181 /* 1434 */ "b4\0"
16182 /* 1437 */ "d4\0"
16183 /* 1440 */ "h4\0"
16184 /* 1443 */ "p4\0"
16185 /* 1446 */ "q4\0"
16186 /* 1449 */ "s4\0"
16187 /* 1452 */ "w4\0"
16188 /* 1455 */ "x4\0"
16189 /* 1458 */ "z4\0"
16190 /* 1461 */ "D12_D13_D14_D15\0"
16191 /* 1477 */ "Q12_Q13_Q14_Q15\0"
16192 /* 1493 */ "W14_W15\0"
16193 /* 1501 */ "X8_X9_X10_X11_X12_X13_X14_X15\0"
16194 /* 1531 */ "Z12_Z13_Z14_Z15\0"
16195 /* 1547 */ "b15\0"
16196 /* 1551 */ "d15\0"
16197 /* 1555 */ "h15\0"
16198 /* 1559 */ "p15\0"
16199 /* 1563 */ "q15\0"
16200 /* 1567 */ "s15\0"
16201 /* 1571 */ "w15\0"
16202 /* 1575 */ "x15\0"
16203 /* 1579 */ "z15\0"
16204 /* 1583 */ "D22_D23_D24_D25\0"
16205 /* 1599 */ "Q22_Q23_Q24_Q25\0"
16206 /* 1615 */ "W24_W25\0"
16207 /* 1623 */ "X18_X19_X20_X21_X22_X23_X24_X25\0"
16208 /* 1655 */ "Z22_Z23_Z24_Z25\0"
16209 /* 1671 */ "b25\0"
16210 /* 1675 */ "d25\0"
16211 /* 1679 */ "h25\0"
16212 /* 1683 */ "q25\0"
16213 /* 1687 */ "s25\0"
16214 /* 1691 */ "w25\0"
16215 /* 1695 */ "x25\0"
16216 /* 1699 */ "z25\0"
16217 /* 1703 */ "D2_D3_D4_D5\0"
16218 /* 1715 */ "Q2_Q3_Q4_Q5\0"
16219 /* 1727 */ "W4_W5\0"
16220 /* 1733 */ "X4_X5\0"
16221 /* 1739 */ "Z2_Z3_Z4_Z5\0"
16222 /* 1751 */ "b5\0"
16223 /* 1754 */ "d5\0"
16224 /* 1757 */ "h5\0"
16225 /* 1760 */ "p5\0"
16226 /* 1763 */ "q5\0"
16227 /* 1766 */ "s5\0"
16228 /* 1769 */ "w5\0"
16229 /* 1772 */ "x5\0"
16230 /* 1775 */ "z5\0"
16231 /* 1778 */ "D13_D14_D15_D16\0"
16232 /* 1794 */ "Q13_Q14_Q15_Q16\0"
16233 /* 1810 */ "Z13_Z14_Z15_Z16\0"
16234 /* 1826 */ "b16\0"
16235 /* 1830 */ "d16\0"
16236 /* 1834 */ "h16\0"
16237 /* 1838 */ "q16\0"
16238 /* 1842 */ "s16\0"
16239 /* 1846 */ "w16\0"
16240 /* 1850 */ "x16\0"
16241 /* 1854 */ "z16\0"
16242 /* 1858 */ "D23_D24_D25_D26\0"
16243 /* 1874 */ "Q23_Q24_Q25_Q26\0"
16244 /* 1890 */ "Z23_Z24_Z25_Z26\0"
16245 /* 1906 */ "b26\0"
16246 /* 1910 */ "d26\0"
16247 /* 1914 */ "h26\0"
16248 /* 1918 */ "q26\0"
16249 /* 1922 */ "s26\0"
16250 /* 1926 */ "w26\0"
16251 /* 1930 */ "x26\0"
16252 /* 1934 */ "z26\0"
16253 /* 1938 */ "D3_D4_D5_D6\0"
16254 /* 1950 */ "Q3_Q4_Q5_Q6\0"
16255 /* 1962 */ "Z3_Z4_Z5_Z6\0"
16256 /* 1974 */ "b6\0"
16257 /* 1977 */ "d6\0"
16258 /* 1980 */ "h6\0"
16259 /* 1983 */ "p6\0"
16260 /* 1986 */ "q6\0"
16261 /* 1989 */ "s6\0"
16262 /* 1992 */ "w6\0"
16263 /* 1995 */ "x6\0"
16264 /* 1998 */ "z6\0"
16265 /* 2001 */ "D14_D15_D16_D17\0"
16266 /* 2017 */ "Q14_Q15_Q16_Q17\0"
16267 /* 2033 */ "W16_W17\0"
16268 /* 2041 */ "X10_X11_X12_X13_X14_X15_X16_X17\0"
16269 /* 2073 */ "Z14_Z15_Z16_Z17\0"
16270 /* 2089 */ "b17\0"
16271 /* 2093 */ "d17\0"
16272 /* 2097 */ "h17\0"
16273 /* 2101 */ "q17\0"
16274 /* 2105 */ "s17\0"
16275 /* 2109 */ "w17\0"
16276 /* 2113 */ "x17\0"
16277 /* 2117 */ "z17\0"
16278 /* 2121 */ "D24_D25_D26_D27\0"
16279 /* 2137 */ "Q24_Q25_Q26_Q27\0"
16280 /* 2153 */ "W26_W27\0"
16281 /* 2161 */ "X20_X21_X22_X23_X24_X25_X26_X27\0"
16282 /* 2193 */ "Z24_Z25_Z26_Z27\0"
16283 /* 2209 */ "b27\0"
16284 /* 2213 */ "d27\0"
16285 /* 2217 */ "h27\0"
16286 /* 2221 */ "q27\0"
16287 /* 2225 */ "s27\0"
16288 /* 2229 */ "w27\0"
16289 /* 2233 */ "x27\0"
16290 /* 2237 */ "z27\0"
16291 /* 2241 */ "D4_D5_D6_D7\0"
16292 /* 2253 */ "Q4_Q5_Q6_Q7\0"
16293 /* 2265 */ "W6_W7\0"
16294 /* 2271 */ "X0_X1_X2_X3_X4_X5_X6_X7\0"
16295 /* 2295 */ "Z4_Z5_Z6_Z7\0"
16296 /* 2307 */ "b7\0"
16297 /* 2310 */ "d7\0"
16298 /* 2313 */ "h7\0"
16299 /* 2316 */ "p7\0"
16300 /* 2319 */ "q7\0"
16301 /* 2322 */ "s7\0"
16302 /* 2325 */ "w7\0"
16303 /* 2328 */ "x7\0"
16304 /* 2331 */ "z7\0"
16305 /* 2334 */ "D15_D16_D17_D18\0"
16306 /* 2350 */ "Q15_Q16_Q17_Q18\0"
16307 /* 2366 */ "Z15_Z16_Z17_Z18\0"
16308 /* 2382 */ "b18\0"
16309 /* 2386 */ "d18\0"
16310 /* 2390 */ "h18\0"
16311 /* 2394 */ "q18\0"
16312 /* 2398 */ "s18\0"
16313 /* 2402 */ "w18\0"
16314 /* 2406 */ "x18\0"
16315 /* 2410 */ "z18\0"
16316 /* 2414 */ "D25_D26_D27_D28\0"
16317 /* 2430 */ "Q25_Q26_Q27_Q28\0"
16318 /* 2446 */ "Z25_Z26_Z27_Z28\0"
16319 /* 2462 */ "b28\0"
16320 /* 2466 */ "d28\0"
16321 /* 2470 */ "h28\0"
16322 /* 2474 */ "q28\0"
16323 /* 2478 */ "s28\0"
16324 /* 2482 */ "w28\0"
16325 /* 2486 */ "x28\0"
16326 /* 2490 */ "z28\0"
16327 /* 2494 */ "D5_D6_D7_D8\0"
16328 /* 2506 */ "Q5_Q6_Q7_Q8\0"
16329 /* 2518 */ "Z5_Z6_Z7_Z8\0"
16330 /* 2530 */ "b8\0"
16331 /* 2533 */ "d8\0"
16332 /* 2536 */ "h8\0"
16333 /* 2539 */ "p8\0"
16334 /* 2542 */ "q8\0"
16335 /* 2545 */ "s8\0"
16336 /* 2548 */ "w8\0"
16337 /* 2551 */ "x8\0"
16338 /* 2554 */ "z8\0"
16339 /* 2557 */ "D16_D17_D18_D19\0"
16340 /* 2573 */ "Q16_Q17_Q18_Q19\0"
16341 /* 2589 */ "W18_W19\0"
16342 /* 2597 */ "X12_X13_X14_X15_X16_X17_X18_X19\0"
16343 /* 2629 */ "Z16_Z17_Z18_Z19\0"
16344 /* 2645 */ "b19\0"
16345 /* 2649 */ "d19\0"
16346 /* 2653 */ "h19\0"
16347 /* 2657 */ "q19\0"
16348 /* 2661 */ "s19\0"
16349 /* 2665 */ "w19\0"
16350 /* 2669 */ "x19\0"
16351 /* 2673 */ "z19\0"
16352 /* 2677 */ "D26_D27_D28_D29\0"
16353 /* 2693 */ "Q26_Q27_Q28_Q29\0"
16354 /* 2709 */ "W28_W29\0"
16355 /* 2717 */ "Z26_Z27_Z28_Z29\0"
16356 /* 2733 */ "b29\0"
16357 /* 2737 */ "d29\0"
16358 /* 2741 */ "h29\0"
16359 /* 2745 */ "q29\0"
16360 /* 2749 */ "s29\0"
16361 /* 2753 */ "w29\0"
16362 /* 2757 */ "x29\0"
16363 /* 2761 */ "z29\0"
16364 /* 2765 */ "D6_D7_D8_D9\0"
16365 /* 2777 */ "Q6_Q7_Q8_Q9\0"
16366 /* 2789 */ "W8_W9\0"
16367 /* 2795 */ "X2_X3_X4_X5_X6_X7_X8_X9\0"
16368 /* 2819 */ "Z6_Z7_Z8_Z9\0"
16369 /* 2831 */ "b9\0"
16370 /* 2834 */ "d9\0"
16371 /* 2837 */ "h9\0"
16372 /* 2840 */ "p9\0"
16373 /* 2843 */ "q9\0"
16374 /* 2846 */ "s9\0"
16375 /* 2849 */ "w9\0"
16376 /* 2852 */ "x9\0"
16377 /* 2855 */ "z9\0"
16378 /* 2858 */ "X22_X23_X24_X25_X26_X27_X28_FP\0"
16379 /* 2889 */ "W30_WZR\0"
16380 /* 2897 */ "LR_XZR\0"
16381 /* 2904 */ "vg\0"
16382 /* 2907 */ "z10_hi\0"
16383 /* 2914 */ "z20_hi\0"
16384 /* 2921 */ "z30_hi\0"
16385 /* 2928 */ "z0_hi\0"
16386 /* 2934 */ "z11_hi\0"
16387 /* 2941 */ "z21_hi\0"
16388 /* 2948 */ "z31_hi\0"
16389 /* 2955 */ "z1_hi\0"
16390 /* 2961 */ "z12_hi\0"
16391 /* 2968 */ "z22_hi\0"
16392 /* 2975 */ "z2_hi\0"
16393 /* 2981 */ "z13_hi\0"
16394 /* 2988 */ "z23_hi\0"
16395 /* 2995 */ "z3_hi\0"
16396 /* 3001 */ "z14_hi\0"
16397 /* 3008 */ "z24_hi\0"
16398 /* 3015 */ "z4_hi\0"
16399 /* 3021 */ "z15_hi\0"
16400 /* 3028 */ "z25_hi\0"
16401 /* 3035 */ "z5_hi\0"
16402 /* 3041 */ "z16_hi\0"
16403 /* 3048 */ "z26_hi\0"
16404 /* 3055 */ "z6_hi\0"
16405 /* 3061 */ "z17_hi\0"
16406 /* 3068 */ "z27_hi\0"
16407 /* 3075 */ "z7_hi\0"
16408 /* 3081 */ "z18_hi\0"
16409 /* 3088 */ "z28_hi\0"
16410 /* 3095 */ "z8_hi\0"
16411 /* 3101 */ "z19_hi\0"
16412 /* 3108 */ "z29_hi\0"
16413 /* 3115 */ "z9_hi\0"
16414 /* 3121 */ "wsp\0"
16415 /* 3125 */ "ffr\0"
16416 /* 3129 */ "wzr\0"
16417 /* 3133 */ "xzr\0"
16418 /* 3137 */ "nzcv\0"
16419};
16420#ifdef __GNUC__
16421#pragma GCC diagnostic pop
16422#endif
16423
16424 static const uint16_t RegAsmOffsetNoRegAltName[] = {
16425 3125, 2757, 227, 3137, 3122, 2904, 3121, 3129, 3133, 280, 665, 892, 1207, 1434,
16426 1751, 1974, 2307, 2530, 2831, 39, 383, 737, 1003, 1282, 1547, 1826, 2089, 2382,
16427 2645, 123, 507, 821, 1127, 1366, 1671, 1906, 2209, 2462, 2733, 203, 587, 283,
16428 668, 895, 1210, 1437, 1754, 1977, 2310, 2533, 2834, 43, 387, 741, 1007, 1286,
16429 1551, 1830, 2093, 2386, 2649, 127, 511, 825, 1131, 1370, 1675, 1910, 2213, 2466,
16430 2737, 207, 591, 286, 671, 898, 1213, 1440, 1757, 1980, 2313, 2536, 2837, 47,
16431 391, 745, 1011, 1290, 1555, 1834, 2097, 2390, 2653, 131, 515, 829, 1135, 1374,
16432 1679, 1914, 2217, 2470, 2741, 211, 595, 289, 674, 901, 1216, 1443, 1760, 1983,
16433 2316, 2539, 2840, 51, 395, 749, 1015, 1294, 1559, 292, 677, 904, 1219, 1446,
16434 1763, 1986, 2319, 2542, 2843, 55, 399, 753, 1019, 1298, 1563, 1838, 2101, 2394,
16435 2657, 135, 519, 833, 1139, 1378, 1683, 1918, 2221, 2474, 2745, 215, 599, 295,
16436 680, 907, 1222, 1449, 1766, 1989, 2322, 2545, 2846, 59, 403, 757, 1023, 1302,
16437 1567, 1842, 2105, 2398, 2661, 139, 523, 837, 1143, 1382, 1687, 1922, 2225, 2478,
16438 2749, 219, 603, 298, 683, 910, 1225, 1452, 1769, 1992, 2325, 2548, 2849, 63,
16439 407, 761, 1027, 1306, 1571, 1846, 2109, 2402, 2665, 143, 527, 841, 1147, 1386,
16440 1691, 1926, 2229, 2482, 2753, 223, 301, 686, 913, 1228, 1455, 1772, 1995, 2328,
16441 2551, 2852, 67, 411, 765, 1031, 1310, 1575, 1850, 2113, 2406, 2669, 147, 531,
16442 845, 1151, 1390, 1695, 1930, 2233, 2486, 304, 689, 916, 1231, 1458, 1775, 1998,
16443 2331, 2554, 2855, 71, 415, 769, 1035, 1314, 1579, 1854, 2117, 2410, 2673, 151,
16444 535, 849, 1155, 1394, 1699, 1934, 2237, 2490, 2761, 231, 607, 2928, 2955, 2975,
16445 2995, 3015, 3035, 3055, 3075, 3095, 3115, 2907, 2934, 2961, 2981, 3001, 3021, 3041,
16446 3061, 3081, 3101, 2914, 2941, 2968, 2988, 3008, 3028, 3048, 3068, 3088, 3108, 2921,
16447 2948, 619, 860, 1165, 1404, 1709, 1944, 2247, 2500, 2771, 6, 313, 699, 927,
16448 1242, 1469, 1786, 2009, 2342, 2565, 83, 427, 781, 1047, 1326, 1591, 1866, 2129,
16449 2422, 2685, 163, 547, 243, 1159, 1398, 1703, 1938, 2241, 2494, 2765, 0, 307,
16450 692, 919, 1234, 1461, 1778, 2001, 2334, 2557, 75, 419, 773, 1039, 1318, 1583,
16451 1858, 2121, 2414, 2677, 155, 539, 235, 611, 853, 857, 1162, 1401, 1706, 1941,
16452 2244, 2497, 2768, 3, 310, 695, 923, 1238, 1465, 1782, 2005, 2338, 2561, 79,
16453 423, 777, 1043, 1322, 1587, 1862, 2125, 2418, 2681, 159, 543, 239, 615, 633,
16454 873, 1177, 1416, 1721, 1956, 2259, 2512, 2783, 19, 327, 714, 943, 1258, 1485,
16455 1802, 2025, 2358, 2581, 99, 443, 797, 1063, 1342, 1607, 1882, 2145, 2438, 2701,
16456 179, 563, 258, 1171, 1410, 1715, 1950, 2253, 2506, 2777, 13, 321, 707, 935,
16457 1250, 1477, 1794, 2017, 2350, 2573, 91, 435, 789, 1055, 1334, 1599, 1874, 2137,
16458 2430, 2693, 171, 555, 250, 625, 866, 870, 1174, 1413, 1718, 1953, 2256, 2509,
16459 2780, 16, 324, 710, 939, 1254, 1481, 1798, 2021, 2354, 2577, 95, 439, 793,
16460 1059, 1338, 1603, 1878, 2141, 2434, 2697, 175, 559, 254, 629, 2858, 2271, 2795,
16461 343, 959, 1501, 2041, 2597, 459, 1079, 1623, 2161, 2889, 639, 1183, 1727, 2265,
16462 2789, 335, 951, 1493, 2033, 2589, 451, 1071, 1615, 2153, 2709, 2897, 2882, 645,
16463 1189, 1733, 2289, 2813, 361, 979, 1523, 2065, 2621, 483, 1103, 1647, 2185, 659,
16464 886, 1201, 1428, 1745, 1968, 2301, 2524, 2825, 32, 375, 729, 995, 1274, 1539,
16465 1818, 2081, 2374, 2637, 115, 499, 813, 1119, 1358, 1663, 1898, 2201, 2454, 2725,
16466 195, 579, 273, 1195, 1422, 1739, 1962, 2295, 2518, 2819, 26, 369, 722, 987,
16467 1266, 1531, 1810, 2073, 2366, 2629, 107, 491, 805, 1111, 1350, 1655, 1890, 2193,
16468 2446, 2717, 187, 571, 265, 651, 879, 883, 1198, 1425, 1742, 1965, 2298, 2521,
16469 2822, 29, 372, 725, 991, 1270, 1535, 1814, 2077, 2370, 2633, 111, 495, 809,
16470 1115, 1354, 1659, 1894, 2197, 2450, 2721, 191, 575, 269, 655,
16471 };
16472
16473
16474#ifdef __GNUC__
16475#pragma GCC diagnostic push
16476#pragma GCC diagnostic ignored "-Woverlength-strings"
16477#endif
16478 static const char AsmStrsvlist1[] = {
16479 /* 0 */ "\0"
16480};
16481#ifdef __GNUC__
16482#pragma GCC diagnostic pop
16483#endif
16484
16485 static const uint8_t RegAsmOffsetvlist1[] = {
16486 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16487 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16488 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16489 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16490 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16491 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16492 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16493 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16494 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16495 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16496 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16497 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16498 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16499 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16500 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16501 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16502 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16503 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16504 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16505 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16506 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16507 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16508 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16509 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16510 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16511 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16512 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16513 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16514 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16515 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16516 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16517 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16518 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16519 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16520 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16521 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16522 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16523 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16524 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16525 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16526 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16527 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16528 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16529 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16530 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16531 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16532 };
16533
16534
16535#ifdef __GNUC__
16536#pragma GCC diagnostic push
16537#pragma GCC diagnostic ignored "-Woverlength-strings"
16538#endif
16539 static const char AsmStrsvreg[] = {
16540 /* 0 */ "v10\0"
16541 /* 4 */ "v20\0"
16542 /* 8 */ "v30\0"
16543 /* 12 */ "v0\0"
16544 /* 15 */ "v11\0"
16545 /* 19 */ "v21\0"
16546 /* 23 */ "v31\0"
16547 /* 27 */ "v1\0"
16548 /* 30 */ "v12\0"
16549 /* 34 */ "v22\0"
16550 /* 38 */ "v2\0"
16551 /* 41 */ "v13\0"
16552 /* 45 */ "v23\0"
16553 /* 49 */ "v3\0"
16554 /* 52 */ "v14\0"
16555 /* 56 */ "v24\0"
16556 /* 60 */ "v4\0"
16557 /* 63 */ "v15\0"
16558 /* 67 */ "v25\0"
16559 /* 71 */ "v5\0"
16560 /* 74 */ "v16\0"
16561 /* 78 */ "v26\0"
16562 /* 82 */ "v6\0"
16563 /* 85 */ "v17\0"
16564 /* 89 */ "v27\0"
16565 /* 93 */ "v7\0"
16566 /* 96 */ "v18\0"
16567 /* 100 */ "v28\0"
16568 /* 104 */ "v8\0"
16569 /* 107 */ "v19\0"
16570 /* 111 */ "v29\0"
16571 /* 115 */ "v9\0"
16572};
16573#ifdef __GNUC__
16574#pragma GCC diagnostic pop
16575#endif
16576
16577 static const uint8_t RegAsmOffsetvreg[] = {
16578 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16579 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16580 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12,
16581 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52,
16582 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100,
16583 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16584 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16585 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16586 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60,
16587 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96,
16588 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3,
16589 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16590 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16591 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16592 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16593 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16594 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16595 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16596 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16597 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16598 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16599 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16600 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30,
16601 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78,
16602 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104,
16603 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34,
16604 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60,
16605 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96,
16606 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12,
16607 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52,
16608 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100,
16609 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0,
16610 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56,
16611 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82,
16612 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4,
16613 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3,
16614 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16615 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16616 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16617 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16618 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16619 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16620 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16621 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16622 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16623 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
16624 };
16625
16626 switch(AltIdx) {
16627 default: llvm_unreachable("Invalid register alt name index!");
16628 case AArch64::NoRegAltName:
16629 assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
16630 "Invalid alt name index for register!");
16631 return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
16632 case AArch64::vlist1:
16633 assert(*(AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]) &&
16634 "Invalid alt name index for register!");
16635 return AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1];
16636 case AArch64::vreg:
16637 assert(*(AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]) &&
16638 "Invalid alt name index for register!");
16639 return AsmStrsvreg+RegAsmOffsetvreg[RegNo-1];
16640 }
16641}
16642
16643#ifdef PRINT_ALIAS_INSTR
16644#undef PRINT_ALIAS_INSTR
16645
16646static bool AArch64AppleInstPrinterValidateMCOperand(const MCOperand &MCOp,
16647 const MCSubtargetInfo &STI,
16648 unsigned PredicateIndex);
16649bool AArch64AppleInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) {
16650 static const PatternsForOpcode OpToPatterns[] = {
16651 {AArch64::ADDSWri, 0, 1 },
16652 {AArch64::ADDSWrs, 1, 3 },
16653 {AArch64::ADDSWrx, 4, 3 },
16654 {AArch64::ADDSXri, 7, 1 },
16655 {AArch64::ADDSXrs, 8, 3 },
16656 {AArch64::ADDSXrx, 11, 1 },
16657 {AArch64::ADDSXrx64, 12, 3 },
16658 {AArch64::ADDWri, 15, 2 },
16659 {AArch64::ADDWrs, 17, 1 },
16660 {AArch64::ADDWrx, 18, 2 },
16661 {AArch64::ADDXri, 20, 2 },
16662 {AArch64::ADDXrs, 22, 1 },
16663 {AArch64::ADDXrx64, 23, 2 },
16664 {AArch64::ANDSWri, 25, 1 },
16665 {AArch64::ANDSWrs, 26, 3 },
16666 {AArch64::ANDSXri, 29, 1 },
16667 {AArch64::ANDSXrs, 30, 3 },
16668 {AArch64::ANDS_PPzPP, 33, 1 },
16669 {AArch64::ANDWrs, 34, 1 },
16670 {AArch64::ANDXrs, 35, 1 },
16671 {AArch64::AND_PPzPP, 36, 1 },
16672 {AArch64::AND_ZI, 37, 3 },
16673 {AArch64::AUTIA1716, 40, 1 },
16674 {AArch64::AUTIASP, 41, 1 },
16675 {AArch64::AUTIAZ, 42, 1 },
16676 {AArch64::AUTIB1716, 43, 1 },
16677 {AArch64::AUTIBSP, 44, 1 },
16678 {AArch64::AUTIBZ, 45, 1 },
16679 {AArch64::BICSWrs, 46, 1 },
16680 {AArch64::BICSXrs, 47, 1 },
16681 {AArch64::BICWrs, 48, 1 },
16682 {AArch64::BICXrs, 49, 1 },
16683 {AArch64::CLREX, 50, 1 },
16684 {AArch64::CNTB_XPiI, 51, 2 },
16685 {AArch64::CNTD_XPiI, 53, 2 },
16686 {AArch64::CNTH_XPiI, 55, 2 },
16687 {AArch64::CNTW_XPiI, 57, 2 },
16688 {AArch64::CPY_ZPmI_B, 59, 1 },
16689 {AArch64::CPY_ZPmI_D, 60, 1 },
16690 {AArch64::CPY_ZPmI_H, 61, 1 },
16691 {AArch64::CPY_ZPmI_S, 62, 1 },
16692 {AArch64::CPY_ZPmR_B, 63, 1 },
16693 {AArch64::CPY_ZPmR_D, 64, 1 },
16694 {AArch64::CPY_ZPmR_H, 65, 1 },
16695 {AArch64::CPY_ZPmR_S, 66, 1 },
16696 {AArch64::CPY_ZPmV_B, 67, 1 },
16697 {AArch64::CPY_ZPmV_D, 68, 1 },
16698 {AArch64::CPY_ZPmV_H, 69, 1 },
16699 {AArch64::CPY_ZPmV_S, 70, 1 },
16700 {AArch64::CPY_ZPzI_B, 71, 1 },
16701 {AArch64::CPY_ZPzI_D, 72, 1 },
16702 {AArch64::CPY_ZPzI_H, 73, 1 },
16703 {AArch64::CPY_ZPzI_S, 74, 1 },
16704 {AArch64::CSINCWr, 75, 2 },
16705 {AArch64::CSINCXr, 77, 2 },
16706 {AArch64::CSINVWr, 79, 2 },
16707 {AArch64::CSINVXr, 81, 2 },
16708 {AArch64::CSNEGWr, 83, 1 },
16709 {AArch64::CSNEGXr, 84, 1 },
16710 {AArch64::DCPS1, 85, 1 },
16711 {AArch64::DCPS2, 86, 1 },
16712 {AArch64::DCPS3, 87, 1 },
16713 {AArch64::DECB_XPiI, 88, 2 },
16714 {AArch64::DECD_XPiI, 90, 2 },
16715 {AArch64::DECD_ZPiI, 92, 2 },
16716 {AArch64::DECH_XPiI, 94, 2 },
16717 {AArch64::DECH_ZPiI, 96, 2 },
16718 {AArch64::DECW_XPiI, 98, 2 },
16719 {AArch64::DECW_ZPiI, 100, 2 },
16720 {AArch64::DSB, 102, 2 },
16721 {AArch64::DUPM_ZI, 104, 6 },
16722 {AArch64::DUP_ZI_B, 110, 1 },
16723 {AArch64::DUP_ZI_D, 111, 2 },
16724 {AArch64::DUP_ZI_H, 113, 2 },
16725 {AArch64::DUP_ZI_S, 115, 2 },
16726 {AArch64::DUP_ZR_B, 117, 1 },
16727 {AArch64::DUP_ZR_D, 118, 1 },
16728 {AArch64::DUP_ZR_H, 119, 1 },
16729 {AArch64::DUP_ZR_S, 120, 1 },
16730 {AArch64::DUP_ZZI_B, 121, 2 },
16731 {AArch64::DUP_ZZI_D, 123, 2 },
16732 {AArch64::DUP_ZZI_H, 125, 2 },
16733 {AArch64::DUP_ZZI_Q, 127, 2 },
16734 {AArch64::DUP_ZZI_S, 129, 2 },
16735 {AArch64::EONWrs, 131, 1 },
16736 {AArch64::EONXrs, 132, 1 },
16737 {AArch64::EORS_PPzPP, 133, 1 },
16738 {AArch64::EORWrs, 134, 1 },
16739 {AArch64::EORXrs, 135, 1 },
16740 {AArch64::EOR_PPzPP, 136, 1 },
16741 {AArch64::EOR_ZI, 137, 3 },
16742 {AArch64::EXTRWrri, 140, 1 },
16743 {AArch64::EXTRXrri, 141, 1 },
16744 {AArch64::FCPY_ZPmI_D, 142, 1 },
16745 {AArch64::FCPY_ZPmI_H, 143, 1 },
16746 {AArch64::FCPY_ZPmI_S, 144, 1 },
16747 {AArch64::FDUP_ZI_D, 145, 1 },
16748 {AArch64::FDUP_ZI_H, 146, 1 },
16749 {AArch64::FDUP_ZI_S, 147, 1 },
16750 {AArch64::GLD1B_D_IMM_REAL, 148, 1 },
16751 {AArch64::GLD1B_S_IMM_REAL, 149, 1 },
16752 {AArch64::GLD1D_IMM_REAL, 150, 1 },
16753 {AArch64::GLD1H_D_IMM_REAL, 151, 1 },
16754 {AArch64::GLD1H_S_IMM_REAL, 152, 1 },
16755 {AArch64::GLD1SB_D_IMM_REAL, 153, 1 },
16756 {AArch64::GLD1SB_S_IMM_REAL, 154, 1 },
16757 {AArch64::GLD1SH_D_IMM_REAL, 155, 1 },
16758 {AArch64::GLD1SH_S_IMM_REAL, 156, 1 },
16759 {AArch64::GLD1SW_D_IMM_REAL, 157, 1 },
16760 {AArch64::GLD1W_D_IMM_REAL, 158, 1 },
16761 {AArch64::GLD1W_IMM_REAL, 159, 1 },
16762 {AArch64::GLDFF1B_D_IMM_REAL, 160, 1 },
16763 {AArch64::GLDFF1B_S_IMM_REAL, 161, 1 },
16764 {AArch64::GLDFF1D_IMM_REAL, 162, 1 },
16765 {AArch64::GLDFF1H_D_IMM_REAL, 163, 1 },
16766 {AArch64::GLDFF1H_S_IMM_REAL, 164, 1 },
16767 {AArch64::GLDFF1SB_D_IMM_REAL, 165, 1 },
16768 {AArch64::GLDFF1SB_S_IMM_REAL, 166, 1 },
16769 {AArch64::GLDFF1SH_D_IMM_REAL, 167, 1 },
16770 {AArch64::GLDFF1SH_S_IMM_REAL, 168, 1 },
16771 {AArch64::GLDFF1SW_D_IMM_REAL, 169, 1 },
16772 {AArch64::GLDFF1W_D_IMM_REAL, 170, 1 },
16773 {AArch64::GLDFF1W_IMM_REAL, 171, 1 },
16774 {AArch64::HINT, 172, 12 },
16775 {AArch64::INCB_XPiI, 184, 2 },
16776 {AArch64::INCD_XPiI, 186, 2 },
16777 {AArch64::INCD_ZPiI, 188, 2 },
16778 {AArch64::INCH_XPiI, 190, 2 },
16779 {AArch64::INCH_ZPiI, 192, 2 },
16780 {AArch64::INCW_XPiI, 194, 2 },
16781 {AArch64::INCW_ZPiI, 196, 2 },
16782 {AArch64::INSvi16gpr, 198, 1 },
16783 {AArch64::INSvi16lane, 199, 1 },
16784 {AArch64::INSvi32gpr, 200, 1 },
16785 {AArch64::INSvi32lane, 201, 1 },
16786 {AArch64::INSvi64gpr, 202, 1 },
16787 {AArch64::INSvi64lane, 203, 1 },
16788 {AArch64::INSvi8gpr, 204, 1 },
16789 {AArch64::INSvi8lane, 205, 1 },
16790 {AArch64::IRG, 206, 1 },
16791 {AArch64::ISB, 207, 1 },
16792 {AArch64::LD1B_D_IMM_REAL, 208, 1 },
16793 {AArch64::LD1B_H_IMM_REAL, 209, 1 },
16794 {AArch64::LD1B_IMM_REAL, 210, 1 },
16795 {AArch64::LD1B_S_IMM_REAL, 211, 1 },
16796 {AArch64::LD1D_IMM_REAL, 212, 1 },
16797 {AArch64::LD1Fourv16b_POST, 213, 1 },
16798 {AArch64::LD1Fourv1d_POST, 214, 1 },
16799 {AArch64::LD1Fourv2d_POST, 215, 1 },
16800 {AArch64::LD1Fourv2s_POST, 216, 1 },
16801 {AArch64::LD1Fourv4h_POST, 217, 1 },
16802 {AArch64::LD1Fourv4s_POST, 218, 1 },
16803 {AArch64::LD1Fourv8b_POST, 219, 1 },
16804 {AArch64::LD1Fourv8h_POST, 220, 1 },
16805 {AArch64::LD1H_D_IMM_REAL, 221, 1 },
16806 {AArch64::LD1H_IMM_REAL, 222, 1 },
16807 {AArch64::LD1H_S_IMM_REAL, 223, 1 },
16808 {AArch64::LD1Onev16b_POST, 224, 1 },
16809 {AArch64::LD1Onev1d_POST, 225, 1 },
16810 {AArch64::LD1Onev2d_POST, 226, 1 },
16811 {AArch64::LD1Onev2s_POST, 227, 1 },
16812 {AArch64::LD1Onev4h_POST, 228, 1 },
16813 {AArch64::LD1Onev4s_POST, 229, 1 },
16814 {AArch64::LD1Onev8b_POST, 230, 1 },
16815 {AArch64::LD1Onev8h_POST, 231, 1 },
16816 {AArch64::LD1RB_D_IMM, 232, 1 },
16817 {AArch64::LD1RB_H_IMM, 233, 1 },
16818 {AArch64::LD1RB_IMM, 234, 1 },
16819 {AArch64::LD1RB_S_IMM, 235, 1 },
16820 {AArch64::LD1RD_IMM, 236, 1 },
16821 {AArch64::LD1RH_D_IMM, 237, 1 },
16822 {AArch64::LD1RH_IMM, 238, 1 },
16823 {AArch64::LD1RH_S_IMM, 239, 1 },
16824 {AArch64::LD1RO_B_IMM, 240, 1 },
16825 {AArch64::LD1RO_D_IMM, 241, 1 },
16826 {AArch64::LD1RO_H_IMM, 242, 1 },
16827 {AArch64::LD1RO_W_IMM, 243, 1 },
16828 {AArch64::LD1RQ_B_IMM, 244, 1 },
16829 {AArch64::LD1RQ_D_IMM, 245, 1 },
16830 {AArch64::LD1RQ_H_IMM, 246, 1 },
16831 {AArch64::LD1RQ_W_IMM, 247, 1 },
16832 {AArch64::LD1RSB_D_IMM, 248, 1 },
16833 {AArch64::LD1RSB_H_IMM, 249, 1 },
16834 {AArch64::LD1RSB_S_IMM, 250, 1 },
16835 {AArch64::LD1RSH_D_IMM, 251, 1 },
16836 {AArch64::LD1RSH_S_IMM, 252, 1 },
16837 {AArch64::LD1RSW_IMM, 253, 1 },
16838 {AArch64::LD1RW_D_IMM, 254, 1 },
16839 {AArch64::LD1RW_IMM, 255, 1 },
16840 {AArch64::LD1Rv16b_POST, 256, 1 },
16841 {AArch64::LD1Rv1d_POST, 257, 1 },
16842 {AArch64::LD1Rv2d_POST, 258, 1 },
16843 {AArch64::LD1Rv2s_POST, 259, 1 },
16844 {AArch64::LD1Rv4h_POST, 260, 1 },
16845 {AArch64::LD1Rv4s_POST, 261, 1 },
16846 {AArch64::LD1Rv8b_POST, 262, 1 },
16847 {AArch64::LD1Rv8h_POST, 263, 1 },
16848 {AArch64::LD1SB_D_IMM_REAL, 264, 1 },
16849 {AArch64::LD1SB_H_IMM_REAL, 265, 1 },
16850 {AArch64::LD1SB_S_IMM_REAL, 266, 1 },
16851 {AArch64::LD1SH_D_IMM_REAL, 267, 1 },
16852 {AArch64::LD1SH_S_IMM_REAL, 268, 1 },
16853 {AArch64::LD1SW_D_IMM_REAL, 269, 1 },
16854 {AArch64::LD1Threev16b_POST, 270, 1 },
16855 {AArch64::LD1Threev1d_POST, 271, 1 },
16856 {AArch64::LD1Threev2d_POST, 272, 1 },
16857 {AArch64::LD1Threev2s_POST, 273, 1 },
16858 {AArch64::LD1Threev4h_POST, 274, 1 },
16859 {AArch64::LD1Threev4s_POST, 275, 1 },
16860 {AArch64::LD1Threev8b_POST, 276, 1 },
16861 {AArch64::LD1Threev8h_POST, 277, 1 },
16862 {AArch64::LD1Twov16b_POST, 278, 1 },
16863 {AArch64::LD1Twov1d_POST, 279, 1 },
16864 {AArch64::LD1Twov2d_POST, 280, 1 },
16865 {AArch64::LD1Twov2s_POST, 281, 1 },
16866 {AArch64::LD1Twov4h_POST, 282, 1 },
16867 {AArch64::LD1Twov4s_POST, 283, 1 },
16868 {AArch64::LD1Twov8b_POST, 284, 1 },
16869 {AArch64::LD1Twov8h_POST, 285, 1 },
16870 {AArch64::LD1W_D_IMM_REAL, 286, 1 },
16871 {AArch64::LD1W_IMM_REAL, 287, 1 },
16872 {AArch64::LD1i16_POST, 288, 1 },
16873 {AArch64::LD1i32_POST, 289, 1 },
16874 {AArch64::LD1i64_POST, 290, 1 },
16875 {AArch64::LD1i8_POST, 291, 1 },
16876 {AArch64::LD2B_IMM, 292, 1 },
16877 {AArch64::LD2D_IMM, 293, 1 },
16878 {AArch64::LD2H_IMM, 294, 1 },
16879 {AArch64::LD2Rv16b_POST, 295, 1 },
16880 {AArch64::LD2Rv1d_POST, 296, 1 },
16881 {AArch64::LD2Rv2d_POST, 297, 1 },
16882 {AArch64::LD2Rv2s_POST, 298, 1 },
16883 {AArch64::LD2Rv4h_POST, 299, 1 },
16884 {AArch64::LD2Rv4s_POST, 300, 1 },
16885 {AArch64::LD2Rv8b_POST, 301, 1 },
16886 {AArch64::LD2Rv8h_POST, 302, 1 },
16887 {AArch64::LD2Twov16b_POST, 303, 1 },
16888 {AArch64::LD2Twov2d_POST, 304, 1 },
16889 {AArch64::LD2Twov2s_POST, 305, 1 },
16890 {AArch64::LD2Twov4h_POST, 306, 1 },
16891 {AArch64::LD2Twov4s_POST, 307, 1 },
16892 {AArch64::LD2Twov8b_POST, 308, 1 },
16893 {AArch64::LD2Twov8h_POST, 309, 1 },
16894 {AArch64::LD2W_IMM, 310, 1 },
16895 {AArch64::LD2i16_POST, 311, 1 },
16896 {AArch64::LD2i32_POST, 312, 1 },
16897 {AArch64::LD2i64_POST, 313, 1 },
16898 {AArch64::LD2i8_POST, 314, 1 },
16899 {AArch64::LD3B_IMM, 315, 1 },
16900 {AArch64::LD3D_IMM, 316, 1 },
16901 {AArch64::LD3H_IMM, 317, 1 },
16902 {AArch64::LD3Rv16b_POST, 318, 1 },
16903 {AArch64::LD3Rv1d_POST, 319, 1 },
16904 {AArch64::LD3Rv2d_POST, 320, 1 },
16905 {AArch64::LD3Rv2s_POST, 321, 1 },
16906 {AArch64::LD3Rv4h_POST, 322, 1 },
16907 {AArch64::LD3Rv4s_POST, 323, 1 },
16908 {AArch64::LD3Rv8b_POST, 324, 1 },
16909 {AArch64::LD3Rv8h_POST, 325, 1 },
16910 {AArch64::LD3Threev16b_POST, 326, 1 },
16911 {AArch64::LD3Threev2d_POST, 327, 1 },
16912 {AArch64::LD3Threev2s_POST, 328, 1 },
16913 {AArch64::LD3Threev4h_POST, 329, 1 },
16914 {AArch64::LD3Threev4s_POST, 330, 1 },
16915 {AArch64::LD3Threev8b_POST, 331, 1 },
16916 {AArch64::LD3Threev8h_POST, 332, 1 },
16917 {AArch64::LD3W_IMM, 333, 1 },
16918 {AArch64::LD3i16_POST, 334, 1 },
16919 {AArch64::LD3i32_POST, 335, 1 },
16920 {AArch64::LD3i64_POST, 336, 1 },
16921 {AArch64::LD3i8_POST, 337, 1 },
16922 {AArch64::LD4B_IMM, 338, 1 },
16923 {AArch64::LD4D_IMM, 339, 1 },
16924 {AArch64::LD4Fourv16b_POST, 340, 1 },
16925 {AArch64::LD4Fourv2d_POST, 341, 1 },
16926 {AArch64::LD4Fourv2s_POST, 342, 1 },
16927 {AArch64::LD4Fourv4h_POST, 343, 1 },
16928 {AArch64::LD4Fourv4s_POST, 344, 1 },
16929 {AArch64::LD4Fourv8b_POST, 345, 1 },
16930 {AArch64::LD4Fourv8h_POST, 346, 1 },
16931 {AArch64::LD4H_IMM, 347, 1 },
16932 {AArch64::LD4Rv16b_POST, 348, 1 },
16933 {AArch64::LD4Rv1d_POST, 349, 1 },
16934 {AArch64::LD4Rv2d_POST, 350, 1 },
16935 {AArch64::LD4Rv2s_POST, 351, 1 },
16936 {AArch64::LD4Rv4h_POST, 352, 1 },
16937 {AArch64::LD4Rv4s_POST, 353, 1 },
16938 {AArch64::LD4Rv8b_POST, 354, 1 },
16939 {AArch64::LD4Rv8h_POST, 355, 1 },
16940 {AArch64::LD4W_IMM, 356, 1 },
16941 {AArch64::LD4i16_POST, 357, 1 },
16942 {AArch64::LD4i32_POST, 358, 1 },
16943 {AArch64::LD4i64_POST, 359, 1 },
16944 {AArch64::LD4i8_POST, 360, 1 },
16945 {AArch64::LDADDB, 361, 1 },
16946 {AArch64::LDADDH, 362, 1 },
16947 {AArch64::LDADDLB, 363, 1 },
16948 {AArch64::LDADDLH, 364, 1 },
16949 {AArch64::LDADDLW, 365, 1 },
16950 {AArch64::LDADDLX, 366, 1 },
16951 {AArch64::LDADDW, 367, 1 },
16952 {AArch64::LDADDX, 368, 1 },
16953 {AArch64::LDAPURBi, 369, 1 },
16954 {AArch64::LDAPURHi, 370, 1 },
16955 {AArch64::LDAPURSBWi, 371, 1 },
16956 {AArch64::LDAPURSBXi, 372, 1 },
16957 {AArch64::LDAPURSHWi, 373, 1 },
16958 {AArch64::LDAPURSHXi, 374, 1 },
16959 {AArch64::LDAPURSWi, 375, 1 },
16960 {AArch64::LDAPURXi, 376, 1 },
16961 {AArch64::LDAPURi, 377, 1 },
16962 {AArch64::LDCLRB, 378, 1 },
16963 {AArch64::LDCLRH, 379, 1 },
16964 {AArch64::LDCLRLB, 380, 1 },
16965 {AArch64::LDCLRLH, 381, 1 },
16966 {AArch64::LDCLRLW, 382, 1 },
16967 {AArch64::LDCLRLX, 383, 1 },
16968 {AArch64::LDCLRW, 384, 1 },
16969 {AArch64::LDCLRX, 385, 1 },
16970 {AArch64::LDEORB, 386, 1 },
16971 {AArch64::LDEORH, 387, 1 },
16972 {AArch64::LDEORLB, 388, 1 },
16973 {AArch64::LDEORLH, 389, 1 },
16974 {AArch64::LDEORLW, 390, 1 },
16975 {AArch64::LDEORLX, 391, 1 },
16976 {AArch64::LDEORW, 392, 1 },
16977 {AArch64::LDEORX, 393, 1 },
16978 {AArch64::LDFF1B_D_REAL, 394, 1 },
16979 {AArch64::LDFF1B_H_REAL, 395, 1 },
16980 {AArch64::LDFF1B_REAL, 396, 1 },
16981 {AArch64::LDFF1B_S_REAL, 397, 1 },
16982 {AArch64::LDFF1D_REAL, 398, 1 },
16983 {AArch64::LDFF1H_D_REAL, 399, 1 },
16984 {AArch64::LDFF1H_REAL, 400, 1 },
16985 {AArch64::LDFF1H_S_REAL, 401, 1 },
16986 {AArch64::LDFF1SB_D_REAL, 402, 1 },
16987 {AArch64::LDFF1SB_H_REAL, 403, 1 },
16988 {AArch64::LDFF1SB_S_REAL, 404, 1 },
16989 {AArch64::LDFF1SH_D_REAL, 405, 1 },
16990 {AArch64::LDFF1SH_S_REAL, 406, 1 },
16991 {AArch64::LDFF1SW_D_REAL, 407, 1 },
16992 {AArch64::LDFF1W_D_REAL, 408, 1 },
16993 {AArch64::LDFF1W_REAL, 409, 1 },
16994 {AArch64::LDG, 410, 1 },
16995 {AArch64::LDNF1B_D_IMM_REAL, 411, 1 },
16996 {AArch64::LDNF1B_H_IMM_REAL, 412, 1 },
16997 {AArch64::LDNF1B_IMM_REAL, 413, 1 },
16998 {AArch64::LDNF1B_S_IMM_REAL, 414, 1 },
16999 {AArch64::LDNF1D_IMM_REAL, 415, 1 },
17000 {AArch64::LDNF1H_D_IMM_REAL, 416, 1 },
17001 {AArch64::LDNF1H_IMM_REAL, 417, 1 },
17002 {AArch64::LDNF1H_S_IMM_REAL, 418, 1 },
17003 {AArch64::LDNF1SB_D_IMM_REAL, 419, 1 },
17004 {AArch64::LDNF1SB_H_IMM_REAL, 420, 1 },
17005 {AArch64::LDNF1SB_S_IMM_REAL, 421, 1 },
17006 {AArch64::LDNF1SH_D_IMM_REAL, 422, 1 },
17007 {AArch64::LDNF1SH_S_IMM_REAL, 423, 1 },
17008 {AArch64::LDNF1SW_D_IMM_REAL, 424, 1 },
17009 {AArch64::LDNF1W_D_IMM_REAL, 425, 1 },
17010 {AArch64::LDNF1W_IMM_REAL, 426, 1 },
17011 {AArch64::LDNPDi, 427, 1 },
17012 {AArch64::LDNPQi, 428, 1 },
17013 {AArch64::LDNPSi, 429, 1 },
17014 {AArch64::LDNPWi, 430, 1 },
17015 {AArch64::LDNPXi, 431, 1 },
17016 {AArch64::LDNT1B_ZRI, 432, 1 },
17017 {AArch64::LDNT1B_ZZR_D_REAL, 433, 1 },
17018 {AArch64::LDNT1B_ZZR_S_REAL, 434, 1 },
17019 {AArch64::LDNT1D_ZRI, 435, 1 },
17020 {AArch64::LDNT1D_ZZR_D_REAL, 436, 1 },
17021 {AArch64::LDNT1H_ZRI, 437, 1 },
17022 {AArch64::LDNT1H_ZZR_D_REAL, 438, 1 },
17023 {AArch64::LDNT1H_ZZR_S_REAL, 439, 1 },
17024 {AArch64::LDNT1SB_ZZR_D_REAL, 440, 1 },
17025 {AArch64::LDNT1SB_ZZR_S_REAL, 441, 1 },
17026 {AArch64::LDNT1SH_ZZR_D_REAL, 442, 1 },
17027 {AArch64::LDNT1SH_ZZR_S_REAL, 443, 1 },
17028 {AArch64::LDNT1SW_ZZR_D_REAL, 444, 1 },
17029 {AArch64::LDNT1W_ZRI, 445, 1 },
17030 {AArch64::LDNT1W_ZZR_D_REAL, 446, 1 },
17031 {AArch64::LDNT1W_ZZR_S_REAL, 447, 1 },
17032 {AArch64::LDPDi, 448, 1 },
17033 {AArch64::LDPQi, 449, 1 },
17034 {AArch64::LDPSWi, 450, 1 },
17035 {AArch64::LDPSi, 451, 1 },
17036 {AArch64::LDPWi, 452, 1 },
17037 {AArch64::LDPXi, 453, 1 },
17038 {AArch64::LDRAAindexed, 454, 1 },
17039 {AArch64::LDRABindexed, 455, 1 },
17040 {AArch64::LDRBBroX, 456, 1 },
17041 {AArch64::LDRBBui, 457, 1 },
17042 {AArch64::LDRBroX, 458, 1 },
17043 {AArch64::LDRBui, 459, 1 },
17044 {AArch64::LDRDroX, 460, 1 },
17045 {AArch64::LDRDui, 461, 1 },
17046 {AArch64::LDRHHroX, 462, 1 },
17047 {AArch64::LDRHHui, 463, 1 },
17048 {AArch64::LDRHroX, 464, 1 },
17049 {AArch64::LDRHui, 465, 1 },
17050 {AArch64::LDRQroX, 466, 1 },
17051 {AArch64::LDRQui, 467, 1 },
17052 {AArch64::LDRSBWroX, 468, 1 },
17053 {AArch64::LDRSBWui, 469, 1 },
17054 {AArch64::LDRSBXroX, 470, 1 },
17055 {AArch64::LDRSBXui, 471, 1 },
17056 {AArch64::LDRSHWroX, 472, 1 },
17057 {AArch64::LDRSHWui, 473, 1 },
17058 {AArch64::LDRSHXroX, 474, 1 },
17059 {AArch64::LDRSHXui, 475, 1 },
17060 {AArch64::LDRSWroX, 476, 1 },
17061 {AArch64::LDRSWui, 477, 1 },
17062 {AArch64::LDRSroX, 478, 1 },
17063 {AArch64::LDRSui, 479, 1 },
17064 {AArch64::LDRWroX, 480, 1 },
17065 {AArch64::LDRWui, 481, 1 },
17066 {AArch64::LDRXroX, 482, 1 },
17067 {AArch64::LDRXui, 483, 1 },
17068 {AArch64::LDR_PXI, 484, 1 },
17069 {AArch64::LDR_ZXI, 485, 1 },
17070 {AArch64::LDSETB, 486, 1 },
17071 {AArch64::LDSETH, 487, 1 },
17072 {AArch64::LDSETLB, 488, 1 },
17073 {AArch64::LDSETLH, 489, 1 },
17074 {AArch64::LDSETLW, 490, 1 },
17075 {AArch64::LDSETLX, 491, 1 },
17076 {AArch64::LDSETW, 492, 1 },
17077 {AArch64::LDSETX, 493, 1 },
17078 {AArch64::LDSMAXB, 494, 1 },
17079 {AArch64::LDSMAXH, 495, 1 },
17080 {AArch64::LDSMAXLB, 496, 1 },
17081 {AArch64::LDSMAXLH, 497, 1 },
17082 {AArch64::LDSMAXLW, 498, 1 },
17083 {AArch64::LDSMAXLX, 499, 1 },
17084 {AArch64::LDSMAXW, 500, 1 },
17085 {AArch64::LDSMAXX, 501, 1 },
17086 {AArch64::LDSMINB, 502, 1 },
17087 {AArch64::LDSMINH, 503, 1 },
17088 {AArch64::LDSMINLB, 504, 1 },
17089 {AArch64::LDSMINLH, 505, 1 },
17090 {AArch64::LDSMINLW, 506, 1 },
17091 {AArch64::LDSMINLX, 507, 1 },
17092 {AArch64::LDSMINW, 508, 1 },
17093 {AArch64::LDSMINX, 509, 1 },
17094 {AArch64::LDTRBi, 510, 1 },
17095 {AArch64::LDTRHi, 511, 1 },
17096 {AArch64::LDTRSBWi, 512, 1 },
17097 {AArch64::LDTRSBXi, 513, 1 },
17098 {AArch64::LDTRSHWi, 514, 1 },
17099 {AArch64::LDTRSHXi, 515, 1 },
17100 {AArch64::LDTRSWi, 516, 1 },
17101 {AArch64::LDTRWi, 517, 1 },
17102 {AArch64::LDTRXi, 518, 1 },
17103 {AArch64::LDUMAXB, 519, 1 },
17104 {AArch64::LDUMAXH, 520, 1 },
17105 {AArch64::LDUMAXLB, 521, 1 },
17106 {AArch64::LDUMAXLH, 522, 1 },
17107 {AArch64::LDUMAXLW, 523, 1 },
17108 {AArch64::LDUMAXLX, 524, 1 },
17109 {AArch64::LDUMAXW, 525, 1 },
17110 {AArch64::LDUMAXX, 526, 1 },
17111 {AArch64::LDUMINB, 527, 1 },
17112 {AArch64::LDUMINH, 528, 1 },
17113 {AArch64::LDUMINLB, 529, 1 },
17114 {AArch64::LDUMINLH, 530, 1 },
17115 {AArch64::LDUMINLW, 531, 1 },
17116 {AArch64::LDUMINLX, 532, 1 },
17117 {AArch64::LDUMINW, 533, 1 },
17118 {AArch64::LDUMINX, 534, 1 },
17119 {AArch64::LDURBBi, 535, 1 },
17120 {AArch64::LDURBi, 536, 1 },
17121 {AArch64::LDURDi, 537, 1 },
17122 {AArch64::LDURHHi, 538, 1 },
17123 {AArch64::LDURHi, 539, 1 },
17124 {AArch64::LDURQi, 540, 1 },
17125 {AArch64::LDURSBWi, 541, 1 },
17126 {AArch64::LDURSBXi, 542, 1 },
17127 {AArch64::LDURSHWi, 543, 1 },
17128 {AArch64::LDURSHXi, 544, 1 },
17129 {AArch64::LDURSWi, 545, 1 },
17130 {AArch64::LDURSi, 546, 1 },
17131 {AArch64::LDURWi, 547, 1 },
17132 {AArch64::LDURXi, 548, 1 },
17133 {AArch64::MADDWrrr, 549, 1 },
17134 {AArch64::MADDXrrr, 550, 1 },
17135 {AArch64::MSUBWrrr, 551, 1 },
17136 {AArch64::MSUBXrrr, 552, 1 },
17137 {AArch64::NOTv16i8, 553, 1 },
17138 {AArch64::NOTv8i8, 554, 1 },
17139 {AArch64::ORNWrs, 555, 3 },
17140 {AArch64::ORNXrs, 558, 3 },
17141 {AArch64::ORRS_PPzPP, 561, 1 },
17142 {AArch64::ORRWrs, 562, 2 },
17143 {AArch64::ORRXrs, 564, 2 },
17144 {AArch64::ORR_PPzPP, 566, 1 },
17145 {AArch64::ORR_ZI, 567, 3 },
17146 {AArch64::ORR_ZZZ, 570, 1 },
17147 {AArch64::ORRv16i8, 571, 1 },
17148 {AArch64::ORRv8i8, 572, 1 },
17149 {AArch64::PACIA1716, 573, 1 },
17150 {AArch64::PACIASP, 574, 1 },
17151 {AArch64::PACIAZ, 575, 1 },
17152 {AArch64::PACIB1716, 576, 1 },
17153 {AArch64::PACIBSP, 577, 1 },
17154 {AArch64::PACIBZ, 578, 1 },
17155 {AArch64::PRFB_D_PZI, 579, 1 },
17156 {AArch64::PRFB_PRI, 580, 1 },
17157 {AArch64::PRFB_S_PZI, 581, 1 },
17158 {AArch64::PRFD_D_PZI, 582, 1 },
17159 {AArch64::PRFD_PRI, 583, 1 },
17160 {AArch64::PRFD_S_PZI, 584, 1 },
17161 {AArch64::PRFH_D_PZI, 585, 1 },
17162 {AArch64::PRFH_PRI, 586, 1 },
17163 {AArch64::PRFH_S_PZI, 587, 1 },
17164 {AArch64::PRFMroX, 588, 1 },
17165 {AArch64::PRFMui, 589, 1 },
17166 {AArch64::PRFUMi, 590, 1 },
17167 {AArch64::PRFW_D_PZI, 591, 1 },
17168 {AArch64::PRFW_PRI, 592, 1 },
17169 {AArch64::PRFW_S_PZI, 593, 1 },
17170 {AArch64::PTRUES_B, 594, 1 },
17171 {AArch64::PTRUES_D, 595, 1 },
17172 {AArch64::PTRUES_H, 596, 1 },
17173 {AArch64::PTRUES_S, 597, 1 },
17174 {AArch64::PTRUE_B, 598, 1 },
17175 {AArch64::PTRUE_D, 599, 1 },
17176 {AArch64::PTRUE_H, 600, 1 },
17177 {AArch64::PTRUE_S, 601, 1 },
17178 {AArch64::RET, 602, 1 },
17179 {AArch64::SBCSWr, 603, 1 },
17180 {AArch64::SBCSXr, 604, 1 },
17181 {AArch64::SBCWr, 605, 1 },
17182 {AArch64::SBCXr, 606, 1 },
17183 {AArch64::SBFMWri, 607, 3 },
17184 {AArch64::SBFMXri, 610, 4 },
17185 {AArch64::SEL_PPPP, 614, 1 },
17186 {AArch64::SEL_ZPZZ_B, 615, 1 },
17187 {AArch64::SEL_ZPZZ_D, 616, 1 },
17188 {AArch64::SEL_ZPZZ_H, 617, 1 },
17189 {AArch64::SEL_ZPZZ_S, 618, 1 },
17190 {AArch64::SMADDLrrr, 619, 1 },
17191 {AArch64::SMSUBLrrr, 620, 1 },
17192 {AArch64::SQDECB_XPiI, 621, 2 },
17193 {AArch64::SQDECB_XPiWdI, 623, 2 },
17194 {AArch64::SQDECD_XPiI, 625, 2 },
17195 {AArch64::SQDECD_XPiWdI, 627, 2 },
17196 {AArch64::SQDECD_ZPiI, 629, 2 },
17197 {AArch64::SQDECH_XPiI, 631, 2 },
17198 {AArch64::SQDECH_XPiWdI, 633, 2 },
17199 {AArch64::SQDECH_ZPiI, 635, 2 },
17200 {AArch64::SQDECW_XPiI, 637, 2 },
17201 {AArch64::SQDECW_XPiWdI, 639, 2 },
17202 {AArch64::SQDECW_ZPiI, 641, 2 },
17203 {AArch64::SQINCB_XPiI, 643, 2 },
17204 {AArch64::SQINCB_XPiWdI, 645, 2 },
17205 {AArch64::SQINCD_XPiI, 647, 2 },
17206 {AArch64::SQINCD_XPiWdI, 649, 2 },
17207 {AArch64::SQINCD_ZPiI, 651, 2 },
17208 {AArch64::SQINCH_XPiI, 653, 2 },
17209 {AArch64::SQINCH_XPiWdI, 655, 2 },
17210 {AArch64::SQINCH_ZPiI, 657, 2 },
17211 {AArch64::SQINCW_XPiI, 659, 2 },
17212 {AArch64::SQINCW_XPiWdI, 661, 2 },
17213 {AArch64::SQINCW_ZPiI, 663, 2 },
17214 {AArch64::SST1B_D_IMM, 665, 1 },
17215 {AArch64::SST1B_S_IMM, 666, 1 },
17216 {AArch64::SST1D_IMM, 667, 1 },
17217 {AArch64::SST1H_D_IMM, 668, 1 },
17218 {AArch64::SST1H_S_IMM, 669, 1 },
17219 {AArch64::SST1W_D_IMM, 670, 1 },
17220 {AArch64::SST1W_IMM, 671, 1 },
17221 {AArch64::ST1B_D_IMM, 672, 1 },
17222 {AArch64::ST1B_H_IMM, 673, 1 },
17223 {AArch64::ST1B_IMM, 674, 1 },
17224 {AArch64::ST1B_S_IMM, 675, 1 },
17225 {AArch64::ST1D_IMM, 676, 1 },
17226 {AArch64::ST1Fourv16b_POST, 677, 1 },
17227 {AArch64::ST1Fourv1d_POST, 678, 1 },
17228 {AArch64::ST1Fourv2d_POST, 679, 1 },
17229 {AArch64::ST1Fourv2s_POST, 680, 1 },
17230 {AArch64::ST1Fourv4h_POST, 681, 1 },
17231 {AArch64::ST1Fourv4s_POST, 682, 1 },
17232 {AArch64::ST1Fourv8b_POST, 683, 1 },
17233 {AArch64::ST1Fourv8h_POST, 684, 1 },
17234 {AArch64::ST1H_D_IMM, 685, 1 },
17235 {AArch64::ST1H_IMM, 686, 1 },
17236 {AArch64::ST1H_S_IMM, 687, 1 },
17237 {AArch64::ST1Onev16b_POST, 688, 1 },
17238 {AArch64::ST1Onev1d_POST, 689, 1 },
17239 {AArch64::ST1Onev2d_POST, 690, 1 },
17240 {AArch64::ST1Onev2s_POST, 691, 1 },
17241 {AArch64::ST1Onev4h_POST, 692, 1 },
17242 {AArch64::ST1Onev4s_POST, 693, 1 },
17243 {AArch64::ST1Onev8b_POST, 694, 1 },
17244 {AArch64::ST1Onev8h_POST, 695, 1 },
17245 {AArch64::ST1Threev16b_POST, 696, 1 },
17246 {AArch64::ST1Threev1d_POST, 697, 1 },
17247 {AArch64::ST1Threev2d_POST, 698, 1 },
17248 {AArch64::ST1Threev2s_POST, 699, 1 },
17249 {AArch64::ST1Threev4h_POST, 700, 1 },
17250 {AArch64::ST1Threev4s_POST, 701, 1 },
17251 {AArch64::ST1Threev8b_POST, 702, 1 },
17252 {AArch64::ST1Threev8h_POST, 703, 1 },
17253 {AArch64::ST1Twov16b_POST, 704, 1 },
17254 {AArch64::ST1Twov1d_POST, 705, 1 },
17255 {AArch64::ST1Twov2d_POST, 706, 1 },
17256 {AArch64::ST1Twov2s_POST, 707, 1 },
17257 {AArch64::ST1Twov4h_POST, 708, 1 },
17258 {AArch64::ST1Twov4s_POST, 709, 1 },
17259 {AArch64::ST1Twov8b_POST, 710, 1 },
17260 {AArch64::ST1Twov8h_POST, 711, 1 },
17261 {AArch64::ST1W_D_IMM, 712, 1 },
17262 {AArch64::ST1W_IMM, 713, 1 },
17263 {AArch64::ST1i16_POST, 714, 1 },
17264 {AArch64::ST1i32_POST, 715, 1 },
17265 {AArch64::ST1i64_POST, 716, 1 },
17266 {AArch64::ST1i8_POST, 717, 1 },
17267 {AArch64::ST2B_IMM, 718, 1 },
17268 {AArch64::ST2D_IMM, 719, 1 },
17269 {AArch64::ST2GOffset, 720, 1 },
17270 {AArch64::ST2H_IMM, 721, 1 },
17271 {AArch64::ST2Twov16b_POST, 722, 1 },
17272 {AArch64::ST2Twov2d_POST, 723, 1 },
17273 {AArch64::ST2Twov2s_POST, 724, 1 },
17274 {AArch64::ST2Twov4h_POST, 725, 1 },
17275 {AArch64::ST2Twov4s_POST, 726, 1 },
17276 {AArch64::ST2Twov8b_POST, 727, 1 },
17277 {AArch64::ST2Twov8h_POST, 728, 1 },
17278 {AArch64::ST2W_IMM, 729, 1 },
17279 {AArch64::ST2i16_POST, 730, 1 },
17280 {AArch64::ST2i32_POST, 731, 1 },
17281 {AArch64::ST2i64_POST, 732, 1 },
17282 {AArch64::ST2i8_POST, 733, 1 },
17283 {AArch64::ST3B_IMM, 734, 1 },
17284 {AArch64::ST3D_IMM, 735, 1 },
17285 {AArch64::ST3H_IMM, 736, 1 },
17286 {AArch64::ST3Threev16b_POST, 737, 1 },
17287 {AArch64::ST3Threev2d_POST, 738, 1 },
17288 {AArch64::ST3Threev2s_POST, 739, 1 },
17289 {AArch64::ST3Threev4h_POST, 740, 1 },
17290 {AArch64::ST3Threev4s_POST, 741, 1 },
17291 {AArch64::ST3Threev8b_POST, 742, 1 },
17292 {AArch64::ST3Threev8h_POST, 743, 1 },
17293 {AArch64::ST3W_IMM, 744, 1 },
17294 {AArch64::ST3i16_POST, 745, 1 },
17295 {AArch64::ST3i32_POST, 746, 1 },
17296 {AArch64::ST3i64_POST, 747, 1 },
17297 {AArch64::ST3i8_POST, 748, 1 },
17298 {AArch64::ST4B_IMM, 749, 1 },
17299 {AArch64::ST4D_IMM, 750, 1 },
17300 {AArch64::ST4Fourv16b_POST, 751, 1 },
17301 {AArch64::ST4Fourv2d_POST, 752, 1 },
17302 {AArch64::ST4Fourv2s_POST, 753, 1 },
17303 {AArch64::ST4Fourv4h_POST, 754, 1 },
17304 {AArch64::ST4Fourv4s_POST, 755, 1 },
17305 {AArch64::ST4Fourv8b_POST, 756, 1 },
17306 {AArch64::ST4Fourv8h_POST, 757, 1 },
17307 {AArch64::ST4H_IMM, 758, 1 },
17308 {AArch64::ST4W_IMM, 759, 1 },
17309 {AArch64::ST4i16_POST, 760, 1 },
17310 {AArch64::ST4i32_POST, 761, 1 },
17311 {AArch64::ST4i64_POST, 762, 1 },
17312 {AArch64::ST4i8_POST, 763, 1 },
17313 {AArch64::STGOffset, 764, 1 },
17314 {AArch64::STGPi, 765, 1 },
17315 {AArch64::STLURBi, 766, 1 },
17316 {AArch64::STLURHi, 767, 1 },
17317 {AArch64::STLURWi, 768, 1 },
17318 {AArch64::STLURXi, 769, 1 },
17319 {AArch64::STNPDi, 770, 1 },
17320 {AArch64::STNPQi, 771, 1 },
17321 {AArch64::STNPSi, 772, 1 },
17322 {AArch64::STNPWi, 773, 1 },
17323 {AArch64::STNPXi, 774, 1 },
17324 {AArch64::STNT1B_ZRI, 775, 1 },
17325 {AArch64::STNT1B_ZZR_D_REAL, 776, 1 },
17326 {AArch64::STNT1B_ZZR_S_REAL, 777, 1 },
17327 {AArch64::STNT1D_ZRI, 778, 1 },
17328 {AArch64::STNT1D_ZZR_D_REAL, 779, 1 },
17329 {AArch64::STNT1H_ZRI, 780, 1 },
17330 {AArch64::STNT1H_ZZR_D_REAL, 781, 1 },
17331 {AArch64::STNT1H_ZZR_S_REAL, 782, 1 },
17332 {AArch64::STNT1W_ZRI, 783, 1 },
17333 {AArch64::STNT1W_ZZR_D_REAL, 784, 1 },
17334 {AArch64::STNT1W_ZZR_S_REAL, 785, 1 },
17335 {AArch64::STPDi, 786, 1 },
17336 {AArch64::STPQi, 787, 1 },
17337 {AArch64::STPSi, 788, 1 },
17338 {AArch64::STPWi, 789, 1 },
17339 {AArch64::STPXi, 790, 1 },
17340 {AArch64::STRBBroX, 791, 1 },
17341 {AArch64::STRBBui, 792, 1 },
17342 {AArch64::STRBroX, 793, 1 },
17343 {AArch64::STRBui, 794, 1 },
17344 {AArch64::STRDroX, 795, 1 },
17345 {AArch64::STRDui, 796, 1 },
17346 {AArch64::STRHHroX, 797, 1 },
17347 {AArch64::STRHHui, 798, 1 },
17348 {AArch64::STRHroX, 799, 1 },
17349 {AArch64::STRHui, 800, 1 },
17350 {AArch64::STRQroX, 801, 1 },
17351 {AArch64::STRQui, 802, 1 },
17352 {AArch64::STRSroX, 803, 1 },
17353 {AArch64::STRSui, 804, 1 },
17354 {AArch64::STRWroX, 805, 1 },
17355 {AArch64::STRWui, 806, 1 },
17356 {AArch64::STRXroX, 807, 1 },
17357 {AArch64::STRXui, 808, 1 },
17358 {AArch64::STR_PXI, 809, 1 },
17359 {AArch64::STR_ZXI, 810, 1 },
17360 {AArch64::STTRBi, 811, 1 },
17361 {AArch64::STTRHi, 812, 1 },
17362 {AArch64::STTRWi, 813, 1 },
17363 {AArch64::STTRXi, 814, 1 },
17364 {AArch64::STURBBi, 815, 1 },
17365 {AArch64::STURBi, 816, 1 },
17366 {AArch64::STURDi, 817, 1 },
17367 {AArch64::STURHHi, 818, 1 },
17368 {AArch64::STURHi, 819, 1 },
17369 {AArch64::STURQi, 820, 1 },
17370 {AArch64::STURSi, 821, 1 },
17371 {AArch64::STURWi, 822, 1 },
17372 {AArch64::STURXi, 823, 1 },
17373 {AArch64::STZ2GOffset, 824, 1 },
17374 {AArch64::STZGOffset, 825, 1 },
17375 {AArch64::SUBSWri, 826, 1 },
17376 {AArch64::SUBSWrs, 827, 5 },
17377 {AArch64::SUBSWrx, 832, 3 },
17378 {AArch64::SUBSXri, 835, 1 },
17379 {AArch64::SUBSXrs, 836, 5 },
17380 {AArch64::SUBSXrx, 841, 1 },
17381 {AArch64::SUBSXrx64, 842, 3 },
17382 {AArch64::SUBWrs, 845, 3 },
17383 {AArch64::SUBWrx, 848, 2 },
17384 {AArch64::SUBXrs, 850, 3 },
17385 {AArch64::SUBXrx64, 853, 2 },
17386 {AArch64::SYSxt, 855, 1 },
17387 {AArch64::UBFMWri, 856, 3 },
17388 {AArch64::UBFMXri, 859, 4 },
17389 {AArch64::UMADDLrrr, 863, 1 },
17390 {AArch64::UMOVvi32, 864, 1 },
17391 {AArch64::UMOVvi64, 865, 1 },
17392 {AArch64::UMSUBLrrr, 866, 1 },
17393 {AArch64::UQDECB_WPiI, 867, 2 },
17394 {AArch64::UQDECB_XPiI, 869, 2 },
17395 {AArch64::UQDECD_WPiI, 871, 2 },
17396 {AArch64::UQDECD_XPiI, 873, 2 },
17397 {AArch64::UQDECD_ZPiI, 875, 2 },
17398 {AArch64::UQDECH_WPiI, 877, 2 },
17399 {AArch64::UQDECH_XPiI, 879, 2 },
17400 {AArch64::UQDECH_ZPiI, 881, 2 },
17401 {AArch64::UQDECW_WPiI, 883, 2 },
17402 {AArch64::UQDECW_XPiI, 885, 2 },
17403 {AArch64::UQDECW_ZPiI, 887, 2 },
17404 {AArch64::UQINCB_WPiI, 889, 2 },
17405 {AArch64::UQINCB_XPiI, 891, 2 },
17406 {AArch64::UQINCD_WPiI, 893, 2 },
17407 {AArch64::UQINCD_XPiI, 895, 2 },
17408 {AArch64::UQINCD_ZPiI, 897, 2 },
17409 {AArch64::UQINCH_WPiI, 899, 2 },
17410 {AArch64::UQINCH_XPiI, 901, 2 },
17411 {AArch64::UQINCH_ZPiI, 903, 2 },
17412 {AArch64::UQINCW_WPiI, 905, 2 },
17413 {AArch64::UQINCW_XPiI, 907, 2 },
17414 {AArch64::UQINCW_ZPiI, 909, 2 },
17415 {AArch64::XPACLRI, 911, 1 },
17416 };
17417
17418 static const AliasPattern Patterns[] = {
17419 // AArch64::ADDSWri - 0
17420 {0, 0, 4, 2 },
17421 // AArch64::ADDSWrs - 1
17422 {13, 2, 4, 4 },
17423 {24, 6, 4, 3 },
17424 {39, 9, 4, 4 },
17425 // AArch64::ADDSWrx - 4
17426 {13, 13, 4, 4 },
17427 {55, 17, 4, 3 },
17428 {39, 20, 4, 4 },
17429 // AArch64::ADDSXri - 7
17430 {0, 24, 4, 2 },
17431 // AArch64::ADDSXrs - 8
17432 {13, 26, 4, 4 },
17433 {24, 30, 4, 3 },
17434 {39, 33, 4, 4 },
17435 // AArch64::ADDSXrx - 11
17436 {55, 37, 4, 3 },
17437 // AArch64::ADDSXrx64 - 12
17438 {13, 40, 4, 4 },
17439 {55, 44, 4, 3 },
17440 {39, 47, 4, 4 },
17441 // AArch64::ADDWri - 15
17442 {70, 51, 4, 4 },
17443 {70, 55, 4, 4 },
17444 // AArch64::ADDWrs - 17
17445 {81, 59, 4, 4 },
17446 // AArch64::ADDWrx - 18
17447 {81, 63, 4, 4 },
17448 {81, 67, 4, 4 },
17449 // AArch64::ADDXri - 20
17450 {70, 71, 4, 4 },
17451 {70, 75, 4, 4 },
17452 // AArch64::ADDXrs - 22
17453 {81, 79, 4, 4 },
17454 // AArch64::ADDXrx64 - 23
17455 {81, 83, 4, 4 },
17456 {81, 87, 4, 4 },
17457 // AArch64::ANDSWri - 25
17458 {96, 91, 3, 2 },
17459 // AArch64::ANDSWrs - 26
17460 {109, 93, 4, 4 },
17461 {120, 97, 4, 3 },
17462 {135, 100, 4, 4 },
17463 // AArch64::ANDSXri - 29
17464 {151, 104, 3, 2 },
17465 // AArch64::ANDSXrs - 30
17466 {109, 106, 4, 4 },
17467 {120, 110, 4, 3 },
17468 {135, 113, 4, 4 },
17469 // AArch64::ANDS_PPzPP - 33
17470 {164, 117, 4, 5 },
17471 // AArch64::ANDWrs - 34
17472 {188, 122, 4, 4 },
17473 // AArch64::ANDXrs - 35
17474 {188, 126, 4, 4 },
17475 // AArch64::AND_PPzPP - 36
17476 {203, 130, 4, 5 },
17477 // AArch64::AND_ZI - 37
17478 {226, 135, 3, 4 },
17479 {247, 139, 3, 4 },
17480 {268, 143, 3, 4 },
17481 // AArch64::AUTIA1716 - 40
17482 {289, 147, 0, 1 },
17483 // AArch64::AUTIASP - 41
17484 {299, 148, 0, 1 },
17485 // AArch64::AUTIAZ - 42
17486 {307, 149, 0, 1 },
17487 // AArch64::AUTIB1716 - 43
17488 {314, 150, 0, 1 },
17489 // AArch64::AUTIBSP - 44
17490 {324, 151, 0, 1 },
17491 // AArch64::AUTIBZ - 45
17492 {332, 152, 0, 1 },
17493 // AArch64::BICSWrs - 46
17494 {339, 153, 4, 4 },
17495 // AArch64::BICSXrs - 47
17496 {339, 157, 4, 4 },
17497 // AArch64::BICWrs - 48
17498 {355, 161, 4, 4 },
17499 // AArch64::BICXrs - 49
17500 {355, 165, 4, 4 },
17501 // AArch64::CLREX - 50
17502 {370, 169, 1, 1 },
17503 // AArch64::CNTB_XPiI - 51
17504 {376, 170, 3, 4 },
17505 {384, 174, 3, 4 },
17506 // AArch64::CNTD_XPiI - 53
17507 {398, 178, 3, 4 },
17508 {406, 182, 3, 4 },
17509 // AArch64::CNTH_XPiI - 55
17510 {420, 186, 3, 4 },
17511 {428, 190, 3, 4 },
17512 // AArch64::CNTW_XPiI - 57
17513 {442, 194, 3, 4 },
17514 {450, 198, 3, 4 },
17515 // AArch64::CPY_ZPmI_B - 59
17516 {464, 202, 5, 4 },
17517 // AArch64::CPY_ZPmI_D - 60
17518 {487, 206, 5, 4 },
17519 // AArch64::CPY_ZPmI_H - 61
17520 {510, 210, 5, 4 },
17521 // AArch64::CPY_ZPmI_S - 62
17522 {533, 214, 5, 4 },
17523 // AArch64::CPY_ZPmR_B - 63
17524 {556, 218, 4, 5 },
17525 // AArch64::CPY_ZPmR_D - 64
17526 {577, 223, 4, 5 },
17527 // AArch64::CPY_ZPmR_H - 65
17528 {598, 228, 4, 5 },
17529 // AArch64::CPY_ZPmR_S - 66
17530 {619, 233, 4, 5 },
17531 // AArch64::CPY_ZPmV_B - 67
17532 {556, 238, 4, 5 },
17533 // AArch64::CPY_ZPmV_D - 68
17534 {577, 243, 4, 5 },
17535 // AArch64::CPY_ZPmV_H - 69
17536 {598, 248, 4, 5 },
17537 // AArch64::CPY_ZPmV_S - 70
17538 {619, 253, 4, 5 },
17539 // AArch64::CPY_ZPzI_B - 71
17540 {640, 258, 4, 3 },
17541 // AArch64::CPY_ZPzI_D - 72
17542 {663, 261, 4, 3 },
17543 // AArch64::CPY_ZPzI_H - 73
17544 {686, 264, 4, 3 },
17545 // AArch64::CPY_ZPzI_S - 74
17546 {709, 267, 4, 3 },
17547 // AArch64::CSINCWr - 75
17548 {732, 270, 4, 4 },
17549 {746, 274, 4, 4 },
17550 // AArch64::CSINCXr - 77
17551 {732, 278, 4, 4 },
17552 {746, 282, 4, 4 },
17553 // AArch64::CSINVWr - 79
17554 {764, 286, 4, 4 },
17555 {779, 290, 4, 4 },
17556 // AArch64::CSINVXr - 81
17557 {764, 294, 4, 4 },
17558 {779, 298, 4, 4 },
17559 // AArch64::CSNEGWr - 83
17560 {797, 302, 4, 4 },
17561 // AArch64::CSNEGXr - 84
17562 {797, 306, 4, 4 },
17563 // AArch64::DCPS1 - 85
17564 {815, 310, 1, 1 },
17565 // AArch64::DCPS2 - 86
17566 {821, 311, 1, 1 },
17567 // AArch64::DCPS3 - 87
17568 {827, 312, 1, 1 },
17569 // AArch64::DECB_XPiI - 88
17570 {833, 313, 4, 5 },
17571 {841, 318, 4, 5 },
17572 // AArch64::DECD_XPiI - 90
17573 {855, 323, 4, 5 },
17574 {863, 328, 4, 5 },
17575 // AArch64::DECD_ZPiI - 92
17576 {877, 333, 4, 5 },
17577 {887, 338, 4, 5 },
17578 // AArch64::DECH_XPiI - 94
17579 {903, 343, 4, 5 },
17580 {911, 348, 4, 5 },
17581 // AArch64::DECH_ZPiI - 96
17582 {925, 353, 4, 5 },
17583 {935, 358, 4, 5 },
17584 // AArch64::DECW_XPiI - 98
17585 {951, 363, 4, 5 },
17586 {959, 368, 4, 5 },
17587 // AArch64::DECW_ZPiI - 100
17588 {973, 373, 4, 5 },
17589 {983, 378, 4, 5 },
17590 // AArch64::DSB - 102
17591 {999, 383, 1, 1 },
17592 {1004, 384, 1, 1 },
17593 // AArch64::DUPM_ZI - 104
17594 {1010, 385, 2, 3 },
17595 {1025, 388, 2, 3 },
17596 {1040, 391, 2, 3 },
17597 {1055, 394, 2, 3 },
17598 {1071, 397, 2, 3 },
17599 {1087, 400, 2, 3 },
17600 // AArch64::DUP_ZI_B - 110
17601 {1103, 403, 3, 2 },
17602 // AArch64::DUP_ZI_D - 111
17603 {1118, 405, 3, 2 },
17604 {1133, 407, 3, 4 },
17605 // AArch64::DUP_ZI_H - 113
17606 {1149, 411, 3, 2 },
17607 {1164, 413, 3, 4 },
17608 // AArch64::DUP_ZI_S - 115
17609 {1180, 417, 3, 2 },
17610 {1195, 419, 3, 4 },
17611 // AArch64::DUP_ZR_B - 117
17612 {1211, 423, 2, 3 },
17613 // AArch64::DUP_ZR_D - 118
17614 {1224, 426, 2, 3 },
17615 // AArch64::DUP_ZR_H - 119
17616 {1237, 429, 2, 3 },
17617 // AArch64::DUP_ZR_S - 120
17618 {1250, 432, 2, 3 },
17619 // AArch64::DUP_ZZI_B - 121
17620 {1263, 435, 3, 4 },
17621 {1278, 439, 3, 3 },
17622 // AArch64::DUP_ZZI_D - 123
17623 {1297, 442, 3, 4 },
17624 {1312, 446, 3, 3 },
17625 // AArch64::DUP_ZZI_H - 125
17626 {1331, 449, 3, 4 },
17627 {1346, 453, 3, 3 },
17628 // AArch64::DUP_ZZI_Q - 127
17629 {1365, 456, 3, 4 },
17630 {1380, 460, 3, 3 },
17631 // AArch64::DUP_ZZI_S - 129
17632 {1399, 463, 3, 4 },
17633 {1414, 467, 3, 3 },
17634 // AArch64::EONWrs - 131
17635 {1433, 470, 4, 4 },
17636 // AArch64::EONXrs - 132
17637 {1433, 474, 4, 4 },
17638 // AArch64::EORS_PPzPP - 133
17639 {1448, 478, 4, 5 },
17640 // AArch64::EORWrs - 134
17641 {1472, 483, 4, 4 },
17642 // AArch64::EORXrs - 135
17643 {1472, 487, 4, 4 },
17644 // AArch64::EOR_PPzPP - 136
17645 {1487, 491, 4, 5 },
17646 // AArch64::EOR_ZI - 137
17647 {1510, 496, 3, 4 },
17648 {1531, 500, 3, 4 },
17649 {1552, 504, 3, 4 },
17650 // AArch64::EXTRWrri - 140
17651 {1573, 508, 4, 3 },
17652 // AArch64::EXTRXrri - 141
17653 {1573, 511, 4, 3 },
17654 // AArch64::FCPY_ZPmI_D - 142
17655 {1588, 514, 4, 4 },
17656 // AArch64::FCPY_ZPmI_H - 143
17657 {1612, 518, 4, 4 },
17658 // AArch64::FCPY_ZPmI_S - 144
17659 {1636, 522, 4, 4 },
17660 // AArch64::FDUP_ZI_D - 145
17661 {1660, 526, 2, 2 },
17662 // AArch64::FDUP_ZI_H - 146
17663 {1676, 528, 2, 2 },
17664 // AArch64::FDUP_ZI_S - 147
17665 {1692, 530, 2, 2 },
17666 // AArch64::GLD1B_D_IMM_REAL - 148
17667 {1708, 532, 4, 5 },
17668 // AArch64::GLD1B_S_IMM_REAL - 149
17669 {1734, 537, 4, 5 },
17670 // AArch64::GLD1D_IMM_REAL - 150
17671 {1760, 542, 4, 5 },
17672 // AArch64::GLD1H_D_IMM_REAL - 151
17673 {1786, 547, 4, 5 },
17674 // AArch64::GLD1H_S_IMM_REAL - 152
17675 {1812, 552, 4, 5 },
17676 // AArch64::GLD1SB_D_IMM_REAL - 153
17677 {1838, 557, 4, 5 },
17678 // AArch64::GLD1SB_S_IMM_REAL - 154
17679 {1865, 562, 4, 5 },
17680 // AArch64::GLD1SH_D_IMM_REAL - 155
17681 {1892, 567, 4, 5 },
17682 // AArch64::GLD1SH_S_IMM_REAL - 156
17683 {1919, 572, 4, 5 },
17684 // AArch64::GLD1SW_D_IMM_REAL - 157
17685 {1946, 577, 4, 5 },
17686 // AArch64::GLD1W_D_IMM_REAL - 158
17687 {1973, 582, 4, 5 },
17688 // AArch64::GLD1W_IMM_REAL - 159
17689 {1999, 587, 4, 5 },
17690 // AArch64::GLDFF1B_D_IMM_REAL - 160
17691 {2025, 592, 4, 5 },
17692 // AArch64::GLDFF1B_S_IMM_REAL - 161
17693 {2053, 597, 4, 5 },
17694 // AArch64::GLDFF1D_IMM_REAL - 162
17695 {2081, 602, 4, 5 },
17696 // AArch64::GLDFF1H_D_IMM_REAL - 163
17697 {2109, 607, 4, 5 },
17698 // AArch64::GLDFF1H_S_IMM_REAL - 164
17699 {2137, 612, 4, 5 },
17700 // AArch64::GLDFF1SB_D_IMM_REAL - 165
17701 {2165, 617, 4, 5 },
17702 // AArch64::GLDFF1SB_S_IMM_REAL - 166
17703 {2194, 622, 4, 5 },
17704 // AArch64::GLDFF1SH_D_IMM_REAL - 167
17705 {2223, 627, 4, 5 },
17706 // AArch64::GLDFF1SH_S_IMM_REAL - 168
17707 {2252, 632, 4, 5 },
17708 // AArch64::GLDFF1SW_D_IMM_REAL - 169
17709 {2281, 637, 4, 5 },
17710 // AArch64::GLDFF1W_D_IMM_REAL - 170
17711 {2310, 642, 4, 5 },
17712 // AArch64::GLDFF1W_IMM_REAL - 171
17713 {2338, 647, 4, 5 },
17714 // AArch64::HINT - 172
17715 {2366, 652, 1, 1 },
17716 {2370, 653, 1, 1 },
17717 {2376, 654, 1, 1 },
17718 {2380, 655, 1, 1 },
17719 {2384, 656, 1, 1 },
17720 {2388, 657, 1, 1 },
17721 {2393, 658, 1, 1 },
17722 {2397, 659, 1, 2 },
17723 {2401, 661, 1, 1 },
17724 {2406, 662, 1, 2 },
17725 {2410, 664, 1, 2 },
17726 {2419, 666, 1, 2 },
17727 // AArch64::INCB_XPiI - 184
17728 {2428, 668, 4, 5 },
17729 {2436, 673, 4, 5 },
17730 // AArch64::INCD_XPiI - 186
17731 {2450, 678, 4, 5 },
17732 {2458, 683, 4, 5 },
17733 // AArch64::INCD_ZPiI - 188
17734 {2472, 688, 4, 5 },
17735 {2482, 693, 4, 5 },
17736 // AArch64::INCH_XPiI - 190
17737 {2498, 698, 4, 5 },
17738 {2506, 703, 4, 5 },
17739 // AArch64::INCH_ZPiI - 192
17740 {2520, 708, 4, 5 },
17741 {2530, 713, 4, 5 },
17742 // AArch64::INCW_XPiI - 194
17743 {2546, 718, 4, 5 },
17744 {2554, 723, 4, 5 },
17745 // AArch64::INCW_ZPiI - 196
17746 {2568, 728, 4, 5 },
17747 {2578, 733, 4, 5 },
17748 // AArch64::INSvi16gpr - 198
17749 {2594, 738, 4, 5 },
17750 // AArch64::INSvi16lane - 199
17751 {2613, 743, 5, 5 },
17752 // AArch64::INSvi32gpr - 200
17753 {2638, 748, 4, 5 },
17754 // AArch64::INSvi32lane - 201
17755 {2657, 753, 5, 5 },
17756 // AArch64::INSvi64gpr - 202
17757 {2682, 758, 4, 5 },
17758 // AArch64::INSvi64lane - 203
17759 {2701, 763, 5, 5 },
17760 // AArch64::INSvi8gpr - 204
17761 {2726, 768, 4, 5 },
17762 // AArch64::INSvi8lane - 205
17763 {2745, 773, 5, 5 },
17764 // AArch64::IRG - 206
17765 {2770, 778, 3, 4 },
17766 // AArch64::ISB - 207
17767 {2781, 782, 1, 1 },
17768 // AArch64::LD1B_D_IMM_REAL - 208
17769 {2785, 783, 4, 5 },
17770 // AArch64::LD1B_H_IMM_REAL - 209
17771 {2809, 788, 4, 5 },
17772 // AArch64::LD1B_IMM_REAL - 210
17773 {2833, 793, 4, 5 },
17774 // AArch64::LD1B_S_IMM_REAL - 211
17775 {2857, 798, 4, 5 },
17776 // AArch64::LD1D_IMM_REAL - 212
17777 {2881, 803, 4, 5 },
17778 // AArch64::LD1Fourv16b_POST - 213
17779 {2905, 808, 4, 5 },
17780 // AArch64::LD1Fourv1d_POST - 214
17781 {2925, 813, 4, 5 },
17782 // AArch64::LD1Fourv2d_POST - 215
17783 {2945, 818, 4, 5 },
17784 // AArch64::LD1Fourv2s_POST - 216
17785 {2965, 823, 4, 5 },
17786 // AArch64::LD1Fourv4h_POST - 217
17787 {2985, 828, 4, 5 },
17788 // AArch64::LD1Fourv4s_POST - 218
17789 {3005, 833, 4, 5 },
17790 // AArch64::LD1Fourv8b_POST - 219
17791 {3025, 838, 4, 5 },
17792 // AArch64::LD1Fourv8h_POST - 220
17793 {3045, 843, 4, 5 },
17794 // AArch64::LD1H_D_IMM_REAL - 221
17795 {3065, 848, 4, 5 },
17796 // AArch64::LD1H_IMM_REAL - 222
17797 {3089, 853, 4, 5 },
17798 // AArch64::LD1H_S_IMM_REAL - 223
17799 {3113, 858, 4, 5 },
17800 // AArch64::LD1Onev16b_POST - 224
17801 {3137, 863, 4, 5 },
17802 // AArch64::LD1Onev1d_POST - 225
17803 {3157, 868, 4, 5 },
17804 // AArch64::LD1Onev2d_POST - 226
17805 {3176, 873, 4, 5 },
17806 // AArch64::LD1Onev2s_POST - 227
17807 {3196, 878, 4, 5 },
17808 // AArch64::LD1Onev4h_POST - 228
17809 {3215, 883, 4, 5 },
17810 // AArch64::LD1Onev4s_POST - 229
17811 {3234, 888, 4, 5 },
17812 // AArch64::LD1Onev8b_POST - 230
17813 {3254, 893, 4, 5 },
17814 // AArch64::LD1Onev8h_POST - 231
17815 {3273, 898, 4, 5 },
17816 // AArch64::LD1RB_D_IMM - 232
17817 {3293, 903, 4, 5 },
17818 // AArch64::LD1RB_H_IMM - 233
17819 {3318, 908, 4, 5 },
17820 // AArch64::LD1RB_IMM - 234
17821 {3343, 913, 4, 5 },
17822 // AArch64::LD1RB_S_IMM - 235
17823 {3368, 918, 4, 5 },
17824 // AArch64::LD1RD_IMM - 236
17825 {3393, 923, 4, 5 },
17826 // AArch64::LD1RH_D_IMM - 237
17827 {3418, 928, 4, 5 },
17828 // AArch64::LD1RH_IMM - 238
17829 {3443, 933, 4, 5 },
17830 // AArch64::LD1RH_S_IMM - 239
17831 {3468, 938, 4, 5 },
17832 // AArch64::LD1RO_B_IMM - 240
17833 {3493, 943, 4, 6 },
17834 // AArch64::LD1RO_D_IMM - 241
17835 {3519, 949, 4, 6 },
17836 // AArch64::LD1RO_H_IMM - 242
17837 {3545, 955, 4, 6 },
17838 // AArch64::LD1RO_W_IMM - 243
17839 {3571, 961, 4, 6 },
17840 // AArch64::LD1RQ_B_IMM - 244
17841 {3597, 967, 4, 5 },
17842 // AArch64::LD1RQ_D_IMM - 245
17843 {3623, 972, 4, 5 },
17844 // AArch64::LD1RQ_H_IMM - 246
17845 {3649, 977, 4, 5 },
17846 // AArch64::LD1RQ_W_IMM - 247
17847 {3675, 982, 4, 5 },
17848 // AArch64::LD1RSB_D_IMM - 248
17849 {3701, 987, 4, 5 },
17850 // AArch64::LD1RSB_H_IMM - 249
17851 {3727, 992, 4, 5 },
17852 // AArch64::LD1RSB_S_IMM - 250
17853 {3753, 997, 4, 5 },
17854 // AArch64::LD1RSH_D_IMM - 251
17855 {3779, 1002, 4, 5 },
17856 // AArch64::LD1RSH_S_IMM - 252
17857 {3805, 1007, 4, 5 },
17858 // AArch64::LD1RSW_IMM - 253
17859 {3831, 1012, 4, 5 },
17860 // AArch64::LD1RW_D_IMM - 254
17861 {3857, 1017, 4, 5 },
17862 // AArch64::LD1RW_IMM - 255
17863 {3882, 1022, 4, 5 },
17864 // AArch64::LD1Rv16b_POST - 256
17865 {3907, 1027, 4, 5 },
17866 // AArch64::LD1Rv1d_POST - 257
17867 {3927, 1032, 4, 5 },
17868 // AArch64::LD1Rv2d_POST - 258
17869 {3947, 1037, 4, 5 },
17870 // AArch64::LD1Rv2s_POST - 259
17871 {3967, 1042, 4, 5 },
17872 // AArch64::LD1Rv4h_POST - 260
17873 {3987, 1047, 4, 5 },
17874 // AArch64::LD1Rv4s_POST - 261
17875 {4007, 1052, 4, 5 },
17876 // AArch64::LD1Rv8b_POST - 262
17877 {4027, 1057, 4, 5 },
17878 // AArch64::LD1Rv8h_POST - 263
17879 {4047, 1062, 4, 5 },
17880 // AArch64::LD1SB_D_IMM_REAL - 264
17881 {4067, 1067, 4, 5 },
17882 // AArch64::LD1SB_H_IMM_REAL - 265
17883 {4092, 1072, 4, 5 },
17884 // AArch64::LD1SB_S_IMM_REAL - 266
17885 {4117, 1077, 4, 5 },
17886 // AArch64::LD1SH_D_IMM_REAL - 267
17887 {4142, 1082, 4, 5 },
17888 // AArch64::LD1SH_S_IMM_REAL - 268
17889 {4167, 1087, 4, 5 },
17890 // AArch64::LD1SW_D_IMM_REAL - 269
17891 {4192, 1092, 4, 5 },
17892 // AArch64::LD1Threev16b_POST - 270
17893 {4217, 1097, 4, 5 },
17894 // AArch64::LD1Threev1d_POST - 271
17895 {4237, 1102, 4, 5 },
17896 // AArch64::LD1Threev2d_POST - 272
17897 {4257, 1107, 4, 5 },
17898 // AArch64::LD1Threev2s_POST - 273
17899 {4277, 1112, 4, 5 },
17900 // AArch64::LD1Threev4h_POST - 274
17901 {4297, 1117, 4, 5 },
17902 // AArch64::LD1Threev4s_POST - 275
17903 {4317, 1122, 4, 5 },
17904 // AArch64::LD1Threev8b_POST - 276
17905 {4337, 1127, 4, 5 },
17906 // AArch64::LD1Threev8h_POST - 277
17907 {4357, 1132, 4, 5 },
17908 // AArch64::LD1Twov16b_POST - 278
17909 {4377, 1137, 4, 5 },
17910 // AArch64::LD1Twov1d_POST - 279
17911 {4397, 1142, 4, 5 },
17912 // AArch64::LD1Twov2d_POST - 280
17913 {4417, 1147, 4, 5 },
17914 // AArch64::LD1Twov2s_POST - 281
17915 {4437, 1152, 4, 5 },
17916 // AArch64::LD1Twov4h_POST - 282
17917 {4457, 1157, 4, 5 },
17918 // AArch64::LD1Twov4s_POST - 283
17919 {4477, 1162, 4, 5 },
17920 // AArch64::LD1Twov8b_POST - 284
17921 {4497, 1167, 4, 5 },
17922 // AArch64::LD1Twov8h_POST - 285
17923 {4517, 1172, 4, 5 },
17924 // AArch64::LD1W_D_IMM_REAL - 286
17925 {4537, 1177, 4, 5 },
17926 // AArch64::LD1W_IMM_REAL - 287
17927 {4561, 1182, 4, 5 },
17928 // AArch64::LD1i16_POST - 288
17929 {4585, 1187, 6, 7 },
17930 // AArch64::LD1i32_POST - 289
17931 {4608, 1194, 6, 7 },
17932 // AArch64::LD1i64_POST - 290
17933 {4631, 1201, 6, 7 },
17934 // AArch64::LD1i8_POST - 291
17935 {4654, 1208, 6, 7 },
17936 // AArch64::LD2B_IMM - 292
17937 {4677, 1215, 4, 5 },
17938 // AArch64::LD2D_IMM - 293
17939 {4701, 1220, 4, 5 },
17940 // AArch64::LD2H_IMM - 294
17941 {4725, 1225, 4, 5 },
17942 // AArch64::LD2Rv16b_POST - 295
17943 {4749, 1230, 4, 5 },
17944 // AArch64::LD2Rv1d_POST - 296
17945 {4769, 1235, 4, 5 },
17946 // AArch64::LD2Rv2d_POST - 297
17947 {4790, 1240, 4, 5 },
17948 // AArch64::LD2Rv2s_POST - 298
17949 {4811, 1245, 4, 5 },
17950 // AArch64::LD2Rv4h_POST - 299
17951 {4831, 1250, 4, 5 },
17952 // AArch64::LD2Rv4s_POST - 300
17953 {4851, 1255, 4, 5 },
17954 // AArch64::LD2Rv8b_POST - 301
17955 {4871, 1260, 4, 5 },
17956 // AArch64::LD2Rv8h_POST - 302
17957 {4891, 1265, 4, 5 },
17958 // AArch64::LD2Twov16b_POST - 303
17959 {4911, 1270, 4, 5 },
17960 // AArch64::LD2Twov2d_POST - 304
17961 {4931, 1275, 4, 5 },
17962 // AArch64::LD2Twov2s_POST - 305
17963 {4951, 1280, 4, 5 },
17964 // AArch64::LD2Twov4h_POST - 306
17965 {4971, 1285, 4, 5 },
17966 // AArch64::LD2Twov4s_POST - 307
17967 {4991, 1290, 4, 5 },
17968 // AArch64::LD2Twov8b_POST - 308
17969 {5011, 1295, 4, 5 },
17970 // AArch64::LD2Twov8h_POST - 309
17971 {5031, 1300, 4, 5 },
17972 // AArch64::LD2W_IMM - 310
17973 {5051, 1305, 4, 5 },
17974 // AArch64::LD2i16_POST - 311
17975 {5075, 1310, 6, 7 },
17976 // AArch64::LD2i32_POST - 312
17977 {5098, 1317, 6, 7 },
17978 // AArch64::LD2i64_POST - 313
17979 {5121, 1324, 6, 7 },
17980 // AArch64::LD2i8_POST - 314
17981 {5145, 1331, 6, 7 },
17982 // AArch64::LD3B_IMM - 315
17983 {5168, 1338, 4, 5 },
17984 // AArch64::LD3D_IMM - 316
17985 {5192, 1343, 4, 5 },
17986 // AArch64::LD3H_IMM - 317
17987 {5216, 1348, 4, 5 },
17988 // AArch64::LD3Rv16b_POST - 318
17989 {5240, 1353, 4, 5 },
17990 // AArch64::LD3Rv1d_POST - 319
17991 {5260, 1358, 4, 5 },
17992 // AArch64::LD3Rv2d_POST - 320
17993 {5281, 1363, 4, 5 },
17994 // AArch64::LD3Rv2s_POST - 321
17995 {5302, 1368, 4, 5 },
17996 // AArch64::LD3Rv4h_POST - 322
17997 {5323, 1373, 4, 5 },
17998 // AArch64::LD3Rv4s_POST - 323
17999 {5343, 1378, 4, 5 },
18000 // AArch64::LD3Rv8b_POST - 324
18001 {5364, 1383, 4, 5 },
18002 // AArch64::LD3Rv8h_POST - 325
18003 {5384, 1388, 4, 5 },
18004 // AArch64::LD3Threev16b_POST - 326
18005 {5404, 1393, 4, 5 },
18006 // AArch64::LD3Threev2d_POST - 327
18007 {5424, 1398, 4, 5 },
18008 // AArch64::LD3Threev2s_POST - 328
18009 {5444, 1403, 4, 5 },
18010 // AArch64::LD3Threev4h_POST - 329
18011 {5464, 1408, 4, 5 },
18012 // AArch64::LD3Threev4s_POST - 330
18013 {5484, 1413, 4, 5 },
18014 // AArch64::LD3Threev8b_POST - 331
18015 {5504, 1418, 4, 5 },
18016 // AArch64::LD3Threev8h_POST - 332
18017 {5524, 1423, 4, 5 },
18018 // AArch64::LD3W_IMM - 333
18019 {5544, 1428, 4, 5 },
18020 // AArch64::LD3i16_POST - 334
18021 {5568, 1433, 6, 7 },
18022 // AArch64::LD3i32_POST - 335
18023 {5591, 1440, 6, 7 },
18024 // AArch64::LD3i64_POST - 336
18025 {5615, 1447, 6, 7 },
18026 // AArch64::LD3i8_POST - 337
18027 {5639, 1454, 6, 7 },
18028 // AArch64::LD4B_IMM - 338
18029 {5662, 1461, 4, 5 },
18030 // AArch64::LD4D_IMM - 339
18031 {5686, 1466, 4, 5 },
18032 // AArch64::LD4Fourv16b_POST - 340
18033 {5710, 1471, 4, 5 },
18034 // AArch64::LD4Fourv2d_POST - 341
18035 {5730, 1476, 4, 5 },
18036 // AArch64::LD4Fourv2s_POST - 342
18037 {5750, 1481, 4, 5 },
18038 // AArch64::LD4Fourv4h_POST - 343
18039 {5770, 1486, 4, 5 },
18040 // AArch64::LD4Fourv4s_POST - 344
18041 {5790, 1491, 4, 5 },
18042 // AArch64::LD4Fourv8b_POST - 345
18043 {5810, 1496, 4, 5 },
18044 // AArch64::LD4Fourv8h_POST - 346
18045 {5830, 1501, 4, 5 },
18046 // AArch64::LD4H_IMM - 347
18047 {5850, 1506, 4, 5 },
18048 // AArch64::LD4Rv16b_POST - 348
18049 {5874, 1511, 4, 5 },
18050 // AArch64::LD4Rv1d_POST - 349
18051 {5894, 1516, 4, 5 },
18052 // AArch64::LD4Rv2d_POST - 350
18053 {5915, 1521, 4, 5 },
18054 // AArch64::LD4Rv2s_POST - 351
18055 {5936, 1526, 4, 5 },
18056 // AArch64::LD4Rv4h_POST - 352
18057 {5957, 1531, 4, 5 },
18058 // AArch64::LD4Rv4s_POST - 353
18059 {5977, 1536, 4, 5 },
18060 // AArch64::LD4Rv8b_POST - 354
18061 {5998, 1541, 4, 5 },
18062 // AArch64::LD4Rv8h_POST - 355
18063 {6018, 1546, 4, 5 },
18064 // AArch64::LD4W_IMM - 356
18065 {6038, 1551, 4, 5 },
18066 // AArch64::LD4i16_POST - 357
18067 {6062, 1556, 6, 7 },
18068 // AArch64::LD4i32_POST - 358
18069 {6085, 1563, 6, 7 },
18070 // AArch64::LD4i64_POST - 359
18071 {6109, 1570, 6, 7 },
18072 // AArch64::LD4i8_POST - 360
18073 {6133, 1577, 6, 7 },
18074 // AArch64::LDADDB - 361
18075 {6156, 1584, 3, 4 },
18076 // AArch64::LDADDH - 362
18077 {6172, 1588, 3, 4 },
18078 // AArch64::LDADDLB - 363
18079 {6188, 1592, 3, 4 },
18080 // AArch64::LDADDLH - 364
18081 {6205, 1596, 3, 4 },
18082 // AArch64::LDADDLW - 365
18083 {6222, 1600, 3, 4 },
18084 // AArch64::LDADDLX - 366
18085 {6222, 1604, 3, 4 },
18086 // AArch64::LDADDW - 367
18087 {6238, 1608, 3, 4 },
18088 // AArch64::LDADDX - 368
18089 {6238, 1612, 3, 4 },
18090 // AArch64::LDAPURBi - 369
18091 {6253, 1616, 3, 4 },
18092 // AArch64::LDAPURHi - 370
18093 {6270, 1620, 3, 4 },
18094 // AArch64::LDAPURSBWi - 371
18095 {6287, 1624, 3, 4 },
18096 // AArch64::LDAPURSBXi - 372
18097 {6287, 1628, 3, 4 },
18098 // AArch64::LDAPURSHWi - 373
18099 {6305, 1632, 3, 4 },
18100 // AArch64::LDAPURSHXi - 374
18101 {6305, 1636, 3, 4 },
18102 // AArch64::LDAPURSWi - 375
18103 {6323, 1640, 3, 4 },
18104 // AArch64::LDAPURXi - 376
18105 {6341, 1644, 3, 4 },
18106 // AArch64::LDAPURi - 377
18107 {6341, 1648, 3, 4 },
18108 // AArch64::LDCLRB - 378
18109 {6357, 1652, 3, 4 },
18110 // AArch64::LDCLRH - 379
18111 {6373, 1656, 3, 4 },
18112 // AArch64::LDCLRLB - 380
18113 {6389, 1660, 3, 4 },
18114 // AArch64::LDCLRLH - 381
18115 {6406, 1664, 3, 4 },
18116 // AArch64::LDCLRLW - 382
18117 {6423, 1668, 3, 4 },
18118 // AArch64::LDCLRLX - 383
18119 {6423, 1672, 3, 4 },
18120 // AArch64::LDCLRW - 384
18121 {6439, 1676, 3, 4 },
18122 // AArch64::LDCLRX - 385
18123 {6439, 1680, 3, 4 },
18124 // AArch64::LDEORB - 386
18125 {6454, 1684, 3, 4 },
18126 // AArch64::LDEORH - 387
18127 {6470, 1688, 3, 4 },
18128 // AArch64::LDEORLB - 388
18129 {6486, 1692, 3, 4 },
18130 // AArch64::LDEORLH - 389
18131 {6503, 1696, 3, 4 },
18132 // AArch64::LDEORLW - 390
18133 {6520, 1700, 3, 4 },
18134 // AArch64::LDEORLX - 391
18135 {6520, 1704, 3, 4 },
18136 // AArch64::LDEORW - 392
18137 {6536, 1708, 3, 4 },
18138 // AArch64::LDEORX - 393
18139 {6536, 1712, 3, 4 },
18140 // AArch64::LDFF1B_D_REAL - 394
18141 {6551, 1716, 4, 5 },
18142 // AArch64::LDFF1B_H_REAL - 395
18143 {6577, 1721, 4, 5 },
18144 // AArch64::LDFF1B_REAL - 396
18145 {6603, 1726, 4, 5 },
18146 // AArch64::LDFF1B_S_REAL - 397
18147 {6629, 1731, 4, 5 },
18148 // AArch64::LDFF1D_REAL - 398
18149 {6655, 1736, 4, 5 },
18150 // AArch64::LDFF1H_D_REAL - 399
18151 {6681, 1741, 4, 5 },
18152 // AArch64::LDFF1H_REAL - 400
18153 {6707, 1746, 4, 5 },
18154 // AArch64::LDFF1H_S_REAL - 401
18155 {6733, 1751, 4, 5 },
18156 // AArch64::LDFF1SB_D_REAL - 402
18157 {6759, 1756, 4, 5 },
18158 // AArch64::LDFF1SB_H_REAL - 403
18159 {6786, 1761, 4, 5 },
18160 // AArch64::LDFF1SB_S_REAL - 404
18161 {6813, 1766, 4, 5 },
18162 // AArch64::LDFF1SH_D_REAL - 405
18163 {6840, 1771, 4, 5 },
18164 // AArch64::LDFF1SH_S_REAL - 406
18165 {6867, 1776, 4, 5 },
18166 // AArch64::LDFF1SW_D_REAL - 407
18167 {6894, 1781, 4, 5 },
18168 // AArch64::LDFF1W_D_REAL - 408
18169 {6921, 1786, 4, 5 },
18170 // AArch64::LDFF1W_REAL - 409
18171 {6947, 1791, 4, 5 },
18172 // AArch64::LDG - 410
18173 {6973, 1796, 4, 5 },
18174 // AArch64::LDNF1B_D_IMM_REAL - 411
18175 {6986, 1801, 4, 5 },
18176 // AArch64::LDNF1B_H_IMM_REAL - 412
18177 {7012, 1806, 4, 5 },
18178 // AArch64::LDNF1B_IMM_REAL - 413
18179 {7038, 1811, 4, 5 },
18180 // AArch64::LDNF1B_S_IMM_REAL - 414
18181 {7064, 1816, 4, 5 },
18182 // AArch64::LDNF1D_IMM_REAL - 415
18183 {7090, 1821, 4, 5 },
18184 // AArch64::LDNF1H_D_IMM_REAL - 416
18185 {7116, 1826, 4, 5 },
18186 // AArch64::LDNF1H_IMM_REAL - 417
18187 {7142, 1831, 4, 5 },
18188 // AArch64::LDNF1H_S_IMM_REAL - 418
18189 {7168, 1836, 4, 5 },
18190 // AArch64::LDNF1SB_D_IMM_REAL - 419
18191 {7194, 1841, 4, 5 },
18192 // AArch64::LDNF1SB_H_IMM_REAL - 420
18193 {7221, 1846, 4, 5 },
18194 // AArch64::LDNF1SB_S_IMM_REAL - 421
18195 {7248, 1851, 4, 5 },
18196 // AArch64::LDNF1SH_D_IMM_REAL - 422
18197 {7275, 1856, 4, 5 },
18198 // AArch64::LDNF1SH_S_IMM_REAL - 423
18199 {7302, 1861, 4, 5 },
18200 // AArch64::LDNF1SW_D_IMM_REAL - 424
18201 {7329, 1866, 4, 5 },
18202 // AArch64::LDNF1W_D_IMM_REAL - 425
18203 {7356, 1871, 4, 5 },
18204 // AArch64::LDNF1W_IMM_REAL - 426
18205 {7382, 1876, 4, 5 },
18206 // AArch64::LDNPDi - 427
18207 {7408, 1881, 4, 4 },
18208 // AArch64::LDNPQi - 428
18209 {7408, 1885, 4, 4 },
18210 // AArch64::LDNPSi - 429
18211 {7408, 1889, 4, 4 },
18212 // AArch64::LDNPWi - 430
18213 {7408, 1893, 4, 4 },
18214 // AArch64::LDNPXi - 431
18215 {7408, 1897, 4, 4 },
18216 // AArch64::LDNT1B_ZRI - 432
18217 {7426, 1901, 4, 5 },
18218 // AArch64::LDNT1B_ZZR_D_REAL - 433
18219 {7452, 1906, 4, 5 },
18220 // AArch64::LDNT1B_ZZR_S_REAL - 434
18221 {7480, 1911, 4, 5 },
18222 // AArch64::LDNT1D_ZRI - 435
18223 {7508, 1916, 4, 5 },
18224 // AArch64::LDNT1D_ZZR_D_REAL - 436
18225 {7534, 1921, 4, 5 },
18226 // AArch64::LDNT1H_ZRI - 437
18227 {7562, 1926, 4, 5 },
18228 // AArch64::LDNT1H_ZZR_D_REAL - 438
18229 {7588, 1931, 4, 5 },
18230 // AArch64::LDNT1H_ZZR_S_REAL - 439
18231 {7616, 1936, 4, 5 },
18232 // AArch64::LDNT1SB_ZZR_D_REAL - 440
18233 {7644, 1941, 4, 5 },
18234 // AArch64::LDNT1SB_ZZR_S_REAL - 441
18235 {7673, 1946, 4, 5 },
18236 // AArch64::LDNT1SH_ZZR_D_REAL - 442
18237 {7702, 1951, 4, 5 },
18238 // AArch64::LDNT1SH_ZZR_S_REAL - 443
18239 {7731, 1956, 4, 5 },
18240 // AArch64::LDNT1SW_ZZR_D_REAL - 444
18241 {7760, 1961, 4, 5 },
18242 // AArch64::LDNT1W_ZRI - 445
18243 {7789, 1966, 4, 5 },
18244 // AArch64::LDNT1W_ZZR_D_REAL - 446
18245 {7815, 1971, 4, 5 },
18246 // AArch64::LDNT1W_ZZR_S_REAL - 447
18247 {7843, 1976, 4, 5 },
18248 // AArch64::LDPDi - 448
18249 {7871, 1981, 4, 4 },
18250 // AArch64::LDPQi - 449
18251 {7871, 1985, 4, 4 },
18252 // AArch64::LDPSWi - 450
18253 {7888, 1989, 4, 4 },
18254 // AArch64::LDPSi - 451
18255 {7871, 1993, 4, 4 },
18256 // AArch64::LDPWi - 452
18257 {7871, 1997, 4, 4 },
18258 // AArch64::LDPXi - 453
18259 {7871, 2001, 4, 4 },
18260 // AArch64::LDRAAindexed - 454
18261 {7907, 2005, 3, 4 },
18262 // AArch64::LDRABindexed - 455
18263 {7922, 2009, 3, 4 },
18264 // AArch64::LDRBBroX - 456
18265 {7937, 2013, 5, 5 },
18266 // AArch64::LDRBBui - 457
18267 {7955, 2018, 3, 3 },
18268 // AArch64::LDRBroX - 458
18269 {7969, 2021, 5, 5 },
18270 // AArch64::LDRBui - 459
18271 {7986, 2026, 3, 3 },
18272 // AArch64::LDRDroX - 460
18273 {7969, 2029, 5, 5 },
18274 // AArch64::LDRDui - 461
18275 {7986, 2034, 3, 3 },
18276 // AArch64::LDRHHroX - 462
18277 {7999, 2037, 5, 5 },
18278 // AArch64::LDRHHui - 463
18279 {8017, 2042, 3, 3 },
18280 // AArch64::LDRHroX - 464
18281 {7969, 2045, 5, 5 },
18282 // AArch64::LDRHui - 465
18283 {7986, 2050, 3, 3 },
18284 // AArch64::LDRQroX - 466
18285 {7969, 2053, 5, 5 },
18286 // AArch64::LDRQui - 467
18287 {7986, 2058, 3, 3 },
18288 // AArch64::LDRSBWroX - 468
18289 {8031, 2061, 5, 5 },
18290 // AArch64::LDRSBWui - 469
18291 {8050, 2066, 3, 3 },
18292 // AArch64::LDRSBXroX - 470
18293 {8031, 2069, 5, 5 },
18294 // AArch64::LDRSBXui - 471
18295 {8050, 2074, 3, 3 },
18296 // AArch64::LDRSHWroX - 472
18297 {8065, 2077, 5, 5 },
18298 // AArch64::LDRSHWui - 473
18299 {8084, 2082, 3, 3 },
18300 // AArch64::LDRSHXroX - 474
18301 {8065, 2085, 5, 5 },
18302 // AArch64::LDRSHXui - 475
18303 {8084, 2090, 3, 3 },
18304 // AArch64::LDRSWroX - 476
18305 {8099, 2093, 5, 5 },
18306 // AArch64::LDRSWui - 477
18307 {8118, 2098, 3, 3 },
18308 // AArch64::LDRSroX - 478
18309 {7969, 2101, 5, 5 },
18310 // AArch64::LDRSui - 479
18311 {7986, 2106, 3, 3 },
18312 // AArch64::LDRWroX - 480
18313 {7969, 2109, 5, 5 },
18314 // AArch64::LDRWui - 481
18315 {7986, 2114, 3, 3 },
18316 // AArch64::LDRXroX - 482
18317 {7969, 2117, 5, 5 },
18318 // AArch64::LDRXui - 483
18319 {7986, 2122, 3, 3 },
18320 // AArch64::LDR_PXI - 484
18321 {8133, 2125, 3, 4 },
18322 // AArch64::LDR_ZXI - 485
18323 {8133, 2129, 3, 4 },
18324 // AArch64::LDSETB - 486
18325 {8148, 2133, 3, 4 },
18326 // AArch64::LDSETH - 487
18327 {8164, 2137, 3, 4 },
18328 // AArch64::LDSETLB - 488
18329 {8180, 2141, 3, 4 },
18330 // AArch64::LDSETLH - 489
18331 {8197, 2145, 3, 4 },
18332 // AArch64::LDSETLW - 490
18333 {8214, 2149, 3, 4 },
18334 // AArch64::LDSETLX - 491
18335 {8214, 2153, 3, 4 },
18336 // AArch64::LDSETW - 492
18337 {8230, 2157, 3, 4 },
18338 // AArch64::LDSETX - 493
18339 {8230, 2161, 3, 4 },
18340 // AArch64::LDSMAXB - 494
18341 {8245, 2165, 3, 4 },
18342 // AArch64::LDSMAXH - 495
18343 {8262, 2169, 3, 4 },
18344 // AArch64::LDSMAXLB - 496
18345 {8279, 2173, 3, 4 },
18346 // AArch64::LDSMAXLH - 497
18347 {8297, 2177, 3, 4 },
18348 // AArch64::LDSMAXLW - 498
18349 {8315, 2181, 3, 4 },
18350 // AArch64::LDSMAXLX - 499
18351 {8315, 2185, 3, 4 },
18352 // AArch64::LDSMAXW - 500
18353 {8332, 2189, 3, 4 },
18354 // AArch64::LDSMAXX - 501
18355 {8332, 2193, 3, 4 },
18356 // AArch64::LDSMINB - 502
18357 {8348, 2197, 3, 4 },
18358 // AArch64::LDSMINH - 503
18359 {8365, 2201, 3, 4 },
18360 // AArch64::LDSMINLB - 504
18361 {8382, 2205, 3, 4 },
18362 // AArch64::LDSMINLH - 505
18363 {8400, 2209, 3, 4 },
18364 // AArch64::LDSMINLW - 506
18365 {8418, 2213, 3, 4 },
18366 // AArch64::LDSMINLX - 507
18367 {8418, 2217, 3, 4 },
18368 // AArch64::LDSMINW - 508
18369 {8435, 2221, 3, 4 },
18370 // AArch64::LDSMINX - 509
18371 {8435, 2225, 3, 4 },
18372 // AArch64::LDTRBi - 510
18373 {8451, 2229, 3, 3 },
18374 // AArch64::LDTRHi - 511
18375 {8466, 2232, 3, 3 },
18376 // AArch64::LDTRSBWi - 512
18377 {8481, 2235, 3, 3 },
18378 // AArch64::LDTRSBXi - 513
18379 {8481, 2238, 3, 3 },
18380 // AArch64::LDTRSHWi - 514
18381 {8497, 2241, 3, 3 },
18382 // AArch64::LDTRSHXi - 515
18383 {8497, 2244, 3, 3 },
18384 // AArch64::LDTRSWi - 516
18385 {8513, 2247, 3, 3 },
18386 // AArch64::LDTRWi - 517
18387 {8529, 2250, 3, 3 },
18388 // AArch64::LDTRXi - 518
18389 {8529, 2253, 3, 3 },
18390 // AArch64::LDUMAXB - 519
18391 {8543, 2256, 3, 4 },
18392 // AArch64::LDUMAXH - 520
18393 {8560, 2260, 3, 4 },
18394 // AArch64::LDUMAXLB - 521
18395 {8577, 2264, 3, 4 },
18396 // AArch64::LDUMAXLH - 522
18397 {8595, 2268, 3, 4 },
18398 // AArch64::LDUMAXLW - 523
18399 {8613, 2272, 3, 4 },
18400 // AArch64::LDUMAXLX - 524
18401 {8613, 2276, 3, 4 },
18402 // AArch64::LDUMAXW - 525
18403 {8630, 2280, 3, 4 },
18404 // AArch64::LDUMAXX - 526
18405 {8630, 2284, 3, 4 },
18406 // AArch64::LDUMINB - 527
18407 {8646, 2288, 3, 4 },
18408 // AArch64::LDUMINH - 528
18409 {8663, 2292, 3, 4 },
18410 // AArch64::LDUMINLB - 529
18411 {8680, 2296, 3, 4 },
18412 // AArch64::LDUMINLH - 530
18413 {8698, 2300, 3, 4 },
18414 // AArch64::LDUMINLW - 531
18415 {8716, 2304, 3, 4 },
18416 // AArch64::LDUMINLX - 532
18417 {8716, 2308, 3, 4 },
18418 // AArch64::LDUMINW - 533
18419 {8733, 2312, 3, 4 },
18420 // AArch64::LDUMINX - 534
18421 {8733, 2316, 3, 4 },
18422 // AArch64::LDURBBi - 535
18423 {8749, 2320, 3, 3 },
18424 // AArch64::LDURBi - 536
18425 {8764, 2323, 3, 3 },
18426 // AArch64::LDURDi - 537
18427 {8764, 2326, 3, 3 },
18428 // AArch64::LDURHHi - 538
18429 {8778, 2329, 3, 3 },
18430 // AArch64::LDURHi - 539
18431 {8764, 2332, 3, 3 },
18432 // AArch64::LDURQi - 540
18433 {8764, 2335, 3, 3 },
18434 // AArch64::LDURSBWi - 541
18435 {8793, 2338, 3, 3 },
18436 // AArch64::LDURSBXi - 542
18437 {8793, 2341, 3, 3 },
18438 // AArch64::LDURSHWi - 543
18439 {8809, 2344, 3, 3 },
18440 // AArch64::LDURSHXi - 544
18441 {8809, 2347, 3, 3 },
18442 // AArch64::LDURSWi - 545
18443 {8825, 2350, 3, 3 },
18444 // AArch64::LDURSi - 546
18445 {8764, 2353, 3, 3 },
18446 // AArch64::LDURWi - 547
18447 {8764, 2356, 3, 3 },
18448 // AArch64::LDURXi - 548
18449 {8764, 2359, 3, 3 },
18450 // AArch64::MADDWrrr - 549
18451 {8841, 2362, 4, 4 },
18452 // AArch64::MADDXrrr - 550
18453 {8841, 2366, 4, 4 },
18454 // AArch64::MSUBWrrr - 551
18455 {8856, 2370, 4, 4 },
18456 // AArch64::MSUBXrrr - 552
18457 {8856, 2374, 4, 4 },
18458 // AArch64::NOTv16i8 - 553
18459 {8872, 2378, 2, 2 },
18460 // AArch64::NOTv8i8 - 554
18461 {8891, 2380, 2, 2 },
18462 // AArch64::ORNWrs - 555
18463 {8909, 2382, 4, 4 },
18464 {8920, 2386, 4, 3 },
18465 {8935, 2389, 4, 4 },
18466 // AArch64::ORNXrs - 558
18467 {8909, 2393, 4, 4 },
18468 {8920, 2397, 4, 3 },
18469 {8935, 2400, 4, 4 },
18470 // AArch64::ORRS_PPzPP - 561
18471 {8950, 2404, 4, 5 },
18472 // AArch64::ORRWrs - 562
18473 {8966, 2409, 4, 4 },
18474 {8977, 2413, 4, 4 },
18475 // AArch64::ORRXrs - 564
18476 {8966, 2417, 4, 4 },
18477 {8977, 2421, 4, 4 },
18478 // AArch64::ORR_PPzPP - 566
18479 {8992, 2425, 4, 5 },
18480 // AArch64::ORR_ZI - 567
18481 {9007, 2430, 3, 4 },
18482 {9028, 2434, 3, 4 },
18483 {9049, 2438, 3, 4 },
18484 // AArch64::ORR_ZZZ - 570
18485 {9070, 2442, 3, 4 },
18486 // AArch64::ORRv16i8 - 571
18487 {9085, 2446, 3, 3 },
18488 // AArch64::ORRv8i8 - 572
18489 {9104, 2449, 3, 3 },
18490 // AArch64::PACIA1716 - 573
18491 {9122, 2452, 0, 1 },
18492 // AArch64::PACIASP - 574
18493 {9132, 2453, 0, 1 },
18494 // AArch64::PACIAZ - 575
18495 {9140, 2454, 0, 1 },
18496 // AArch64::PACIB1716 - 576
18497 {9147, 2455, 0, 1 },
18498 // AArch64::PACIBSP - 577
18499 {9157, 2456, 0, 1 },
18500 // AArch64::PACIBZ - 578
18501 {9165, 2457, 0, 1 },
18502 // AArch64::PRFB_D_PZI - 579
18503 {9172, 2458, 4, 5 },
18504 // AArch64::PRFB_PRI - 580
18505 {9196, 2463, 4, 5 },
18506 // AArch64::PRFB_S_PZI - 581
18507 {9218, 2468, 4, 5 },
18508 // AArch64::PRFD_D_PZI - 582
18509 {9242, 2473, 4, 5 },
18510 // AArch64::PRFD_PRI - 583
18511 {9266, 2478, 4, 5 },
18512 // AArch64::PRFD_S_PZI - 584
18513 {9288, 2483, 4, 5 },
18514 // AArch64::PRFH_D_PZI - 585
18515 {9312, 2488, 4, 5 },
18516 // AArch64::PRFH_PRI - 586
18517 {9336, 2493, 4, 5 },
18518 // AArch64::PRFH_S_PZI - 587
18519 {9358, 2498, 4, 5 },
18520 // AArch64::PRFMroX - 588
18521 {9382, 2503, 5, 5 },
18522 // AArch64::PRFMui - 589
18523 {9402, 2508, 3, 3 },
18524 // AArch64::PRFUMi - 590
18525 {9418, 2511, 3, 3 },
18526 // AArch64::PRFW_D_PZI - 591
18527 {9435, 2514, 4, 5 },
18528 // AArch64::PRFW_PRI - 592
18529 {9459, 2519, 4, 5 },
18530 // AArch64::PRFW_S_PZI - 593
18531 {9481, 2524, 4, 5 },
18532 // AArch64::PTRUES_B - 594
18533 {9505, 2529, 2, 3 },
18534 // AArch64::PTRUES_D - 595
18535 {9517, 2532, 2, 3 },
18536 // AArch64::PTRUES_H - 596
18537 {9529, 2535, 2, 3 },
18538 // AArch64::PTRUES_S - 597
18539 {9541, 2538, 2, 3 },
18540 // AArch64::PTRUE_B - 598
18541 {9553, 2541, 2, 3 },
18542 // AArch64::PTRUE_D - 599
18543 {9564, 2544, 2, 3 },
18544 // AArch64::PTRUE_H - 600
18545 {9575, 2547, 2, 3 },
18546 // AArch64::PTRUE_S - 601
18547 {9586, 2550, 2, 3 },
18548 // AArch64::RET - 602
18549 {9597, 2553, 1, 1 },
18550 // AArch64::SBCSWr - 603
18551 {9601, 2554, 3, 3 },
18552 // AArch64::SBCSXr - 604
18553 {9601, 2557, 3, 3 },
18554 // AArch64::SBCWr - 605
18555 {9613, 2560, 3, 3 },
18556 // AArch64::SBCXr - 606
18557 {9613, 2563, 3, 3 },
18558 // AArch64::SBFMWri - 607
18559 {9624, 2566, 4, 4 },
18560 {9639, 2570, 4, 4 },
18561 {9651, 2574, 4, 4 },
18562 // AArch64::SBFMXri - 610
18563 {9624, 2578, 4, 4 },
18564 {9639, 2582, 4, 4 },
18565 {9651, 2586, 4, 4 },
18566 {9663, 2590, 4, 4 },
18567 // AArch64::SEL_PPPP - 614
18568 {9675, 2594, 4, 5 },
18569 // AArch64::SEL_ZPZZ_B - 615
18570 {9675, 2599, 4, 5 },
18571 // AArch64::SEL_ZPZZ_D - 616
18572 {9698, 2604, 4, 5 },
18573 // AArch64::SEL_ZPZZ_H - 617
18574 {9721, 2609, 4, 5 },
18575 // AArch64::SEL_ZPZZ_S - 618
18576 {9744, 2614, 4, 5 },
18577 // AArch64::SMADDLrrr - 619
18578 {9767, 2619, 4, 4 },
18579 // AArch64::SMSUBLrrr - 620
18580 {9784, 2623, 4, 4 },
18581 // AArch64::SQDECB_XPiI - 621
18582 {9802, 2627, 4, 5 },
18583 {9812, 2632, 4, 5 },
18584 // AArch64::SQDECB_XPiWdI - 623
18585 {9828, 2637, 4, 5 },
18586 {9844, 2642, 4, 5 },
18587 // AArch64::SQDECD_XPiI - 625
18588 {9866, 2647, 4, 5 },
18589 {9876, 2652, 4, 5 },
18590 // AArch64::SQDECD_XPiWdI - 627
18591 {9892, 2657, 4, 5 },
18592 {9908, 2662, 4, 5 },
18593 // AArch64::SQDECD_ZPiI - 629
18594 {9930, 2667, 4, 5 },
18595 {9942, 2672, 4, 5 },
18596 // AArch64::SQDECH_XPiI - 631
18597 {9960, 2677, 4, 5 },
18598 {9970, 2682, 4, 5 },
18599 // AArch64::SQDECH_XPiWdI - 633
18600 {9986, 2687, 4, 5 },
18601 {10002, 2692, 4, 5 },
18602 // AArch64::SQDECH_ZPiI - 635
18603 {10024, 2697, 4, 5 },
18604 {10036, 2702, 4, 5 },
18605 // AArch64::SQDECW_XPiI - 637
18606 {10054, 2707, 4, 5 },
18607 {10064, 2712, 4, 5 },
18608 // AArch64::SQDECW_XPiWdI - 639
18609 {10080, 2717, 4, 5 },
18610 {10096, 2722, 4, 5 },
18611 // AArch64::SQDECW_ZPiI - 641
18612 {10118, 2727, 4, 5 },
18613 {10130, 2732, 4, 5 },
18614 // AArch64::SQINCB_XPiI - 643
18615 {10148, 2737, 4, 5 },
18616 {10158, 2742, 4, 5 },
18617 // AArch64::SQINCB_XPiWdI - 645
18618 {10174, 2747, 4, 5 },
18619 {10190, 2752, 4, 5 },
18620 // AArch64::SQINCD_XPiI - 647
18621 {10212, 2757, 4, 5 },
18622 {10222, 2762, 4, 5 },
18623 // AArch64::SQINCD_XPiWdI - 649
18624 {10238, 2767, 4, 5 },
18625 {10254, 2772, 4, 5 },
18626 // AArch64::SQINCD_ZPiI - 651
18627 {10276, 2777, 4, 5 },
18628 {10288, 2782, 4, 5 },
18629 // AArch64::SQINCH_XPiI - 653
18630 {10306, 2787, 4, 5 },
18631 {10316, 2792, 4, 5 },
18632 // AArch64::SQINCH_XPiWdI - 655
18633 {10332, 2797, 4, 5 },
18634 {10348, 2802, 4, 5 },
18635 // AArch64::SQINCH_ZPiI - 657
18636 {10370, 2807, 4, 5 },
18637 {10382, 2812, 4, 5 },
18638 // AArch64::SQINCW_XPiI - 659
18639 {10400, 2817, 4, 5 },
18640 {10410, 2822, 4, 5 },
18641 // AArch64::SQINCW_XPiWdI - 661
18642 {10426, 2827, 4, 5 },
18643 {10442, 2832, 4, 5 },
18644 // AArch64::SQINCW_ZPiI - 663
18645 {10464, 2837, 4, 5 },
18646 {10476, 2842, 4, 5 },
18647 // AArch64::SST1B_D_IMM - 665
18648 {10494, 2847, 4, 5 },
18649 // AArch64::SST1B_S_IMM - 666
18650 {10518, 2852, 4, 5 },
18651 // AArch64::SST1D_IMM - 667
18652 {10542, 2857, 4, 5 },
18653 // AArch64::SST1H_D_IMM - 668
18654 {10566, 2862, 4, 5 },
18655 // AArch64::SST1H_S_IMM - 669
18656 {10590, 2867, 4, 5 },
18657 // AArch64::SST1W_D_IMM - 670
18658 {10614, 2872, 4, 5 },
18659 // AArch64::SST1W_IMM - 671
18660 {10638, 2877, 4, 5 },
18661 // AArch64::ST1B_D_IMM - 672
18662 {10662, 2882, 4, 5 },
18663 // AArch64::ST1B_H_IMM - 673
18664 {10684, 2887, 4, 5 },
18665 // AArch64::ST1B_IMM - 674
18666 {10706, 2892, 4, 5 },
18667 // AArch64::ST1B_S_IMM - 675
18668 {10728, 2897, 4, 5 },
18669 // AArch64::ST1D_IMM - 676
18670 {10750, 2902, 4, 5 },
18671 // AArch64::ST1Fourv16b_POST - 677
18672 {10772, 2907, 4, 5 },
18673 // AArch64::ST1Fourv1d_POST - 678
18674 {10792, 2912, 4, 5 },
18675 // AArch64::ST1Fourv2d_POST - 679
18676 {10812, 2917, 4, 5 },
18677 // AArch64::ST1Fourv2s_POST - 680
18678 {10832, 2922, 4, 5 },
18679 // AArch64::ST1Fourv4h_POST - 681
18680 {10852, 2927, 4, 5 },
18681 // AArch64::ST1Fourv4s_POST - 682
18682 {10872, 2932, 4, 5 },
18683 // AArch64::ST1Fourv8b_POST - 683
18684 {10892, 2937, 4, 5 },
18685 // AArch64::ST1Fourv8h_POST - 684
18686 {10912, 2942, 4, 5 },
18687 // AArch64::ST1H_D_IMM - 685
18688 {10932, 2947, 4, 5 },
18689 // AArch64::ST1H_IMM - 686
18690 {10954, 2952, 4, 5 },
18691 // AArch64::ST1H_S_IMM - 687
18692 {10976, 2957, 4, 5 },
18693 // AArch64::ST1Onev16b_POST - 688
18694 {10998, 2962, 4, 5 },
18695 // AArch64::ST1Onev1d_POST - 689
18696 {11018, 2967, 4, 5 },
18697 // AArch64::ST1Onev2d_POST - 690
18698 {11037, 2972, 4, 5 },
18699 // AArch64::ST1Onev2s_POST - 691
18700 {11057, 2977, 4, 5 },
18701 // AArch64::ST1Onev4h_POST - 692
18702 {11076, 2982, 4, 5 },
18703 // AArch64::ST1Onev4s_POST - 693
18704 {11095, 2987, 4, 5 },
18705 // AArch64::ST1Onev8b_POST - 694
18706 {11115, 2992, 4, 5 },
18707 // AArch64::ST1Onev8h_POST - 695
18708 {11134, 2997, 4, 5 },
18709 // AArch64::ST1Threev16b_POST - 696
18710 {11154, 3002, 4, 5 },
18711 // AArch64::ST1Threev1d_POST - 697
18712 {11174, 3007, 4, 5 },
18713 // AArch64::ST1Threev2d_POST - 698
18714 {11194, 3012, 4, 5 },
18715 // AArch64::ST1Threev2s_POST - 699
18716 {11214, 3017, 4, 5 },
18717 // AArch64::ST1Threev4h_POST - 700
18718 {11234, 3022, 4, 5 },
18719 // AArch64::ST1Threev4s_POST - 701
18720 {11254, 3027, 4, 5 },
18721 // AArch64::ST1Threev8b_POST - 702
18722 {11274, 3032, 4, 5 },
18723 // AArch64::ST1Threev8h_POST - 703
18724 {11294, 3037, 4, 5 },
18725 // AArch64::ST1Twov16b_POST - 704
18726 {11314, 3042, 4, 5 },
18727 // AArch64::ST1Twov1d_POST - 705
18728 {11334, 3047, 4, 5 },
18729 // AArch64::ST1Twov2d_POST - 706
18730 {11354, 3052, 4, 5 },
18731 // AArch64::ST1Twov2s_POST - 707
18732 {11374, 3057, 4, 5 },
18733 // AArch64::ST1Twov4h_POST - 708
18734 {11394, 3062, 4, 5 },
18735 // AArch64::ST1Twov4s_POST - 709
18736 {11414, 3067, 4, 5 },
18737 // AArch64::ST1Twov8b_POST - 710
18738 {11434, 3072, 4, 5 },
18739 // AArch64::ST1Twov8h_POST - 711
18740 {11454, 3077, 4, 5 },
18741 // AArch64::ST1W_D_IMM - 712
18742 {11474, 3082, 4, 5 },
18743 // AArch64::ST1W_IMM - 713
18744 {11496, 3087, 4, 5 },
18745 // AArch64::ST1i16_POST - 714
18746 {11518, 3092, 5, 6 },
18747 // AArch64::ST1i32_POST - 715
18748 {11541, 3098, 5, 6 },
18749 // AArch64::ST1i64_POST - 716
18750 {11564, 3104, 5, 6 },
18751 // AArch64::ST1i8_POST - 717
18752 {11587, 3110, 5, 6 },
18753 // AArch64::ST2B_IMM - 718
18754 {11610, 3116, 4, 5 },
18755 // AArch64::ST2D_IMM - 719
18756 {11632, 3121, 4, 5 },
18757 // AArch64::ST2GOffset - 720
18758 {11654, 3126, 3, 4 },
18759 // AArch64::ST2H_IMM - 721
18760 {11668, 3130, 4, 5 },
18761 // AArch64::ST2Twov16b_POST - 722
18762 {11690, 3135, 4, 5 },
18763 // AArch64::ST2Twov2d_POST - 723
18764 {11710, 3140, 4, 5 },
18765 // AArch64::ST2Twov2s_POST - 724
18766 {11730, 3145, 4, 5 },
18767 // AArch64::ST2Twov4h_POST - 725
18768 {11750, 3150, 4, 5 },
18769 // AArch64::ST2Twov4s_POST - 726
18770 {11770, 3155, 4, 5 },
18771 // AArch64::ST2Twov8b_POST - 727
18772 {11790, 3160, 4, 5 },
18773 // AArch64::ST2Twov8h_POST - 728
18774 {11810, 3165, 4, 5 },
18775 // AArch64::ST2W_IMM - 729
18776 {11830, 3170, 4, 5 },
18777 // AArch64::ST2i16_POST - 730
18778 {11852, 3175, 5, 6 },
18779 // AArch64::ST2i32_POST - 731
18780 {11875, 3181, 5, 6 },
18781 // AArch64::ST2i64_POST - 732
18782 {11898, 3187, 5, 6 },
18783 // AArch64::ST2i8_POST - 733
18784 {11922, 3193, 5, 6 },
18785 // AArch64::ST3B_IMM - 734
18786 {11945, 3199, 4, 5 },
18787 // AArch64::ST3D_IMM - 735
18788 {11967, 3204, 4, 5 },
18789 // AArch64::ST3H_IMM - 736
18790 {11989, 3209, 4, 5 },
18791 // AArch64::ST3Threev16b_POST - 737
18792 {12011, 3214, 4, 5 },
18793 // AArch64::ST3Threev2d_POST - 738
18794 {12031, 3219, 4, 5 },
18795 // AArch64::ST3Threev2s_POST - 739
18796 {12051, 3224, 4, 5 },
18797 // AArch64::ST3Threev4h_POST - 740
18798 {12071, 3229, 4, 5 },
18799 // AArch64::ST3Threev4s_POST - 741
18800 {12091, 3234, 4, 5 },
18801 // AArch64::ST3Threev8b_POST - 742
18802 {12111, 3239, 4, 5 },
18803 // AArch64::ST3Threev8h_POST - 743
18804 {12131, 3244, 4, 5 },
18805 // AArch64::ST3W_IMM - 744
18806 {12151, 3249, 4, 5 },
18807 // AArch64::ST3i16_POST - 745
18808 {12173, 3254, 5, 6 },
18809 // AArch64::ST3i32_POST - 746
18810 {12196, 3260, 5, 6 },
18811 // AArch64::ST3i64_POST - 747
18812 {12220, 3266, 5, 6 },
18813 // AArch64::ST3i8_POST - 748
18814 {12244, 3272, 5, 6 },
18815 // AArch64::ST4B_IMM - 749
18816 {12267, 3278, 4, 5 },
18817 // AArch64::ST4D_IMM - 750
18818 {12289, 3283, 4, 5 },
18819 // AArch64::ST4Fourv16b_POST - 751
18820 {12311, 3288, 4, 5 },
18821 // AArch64::ST4Fourv2d_POST - 752
18822 {12331, 3293, 4, 5 },
18823 // AArch64::ST4Fourv2s_POST - 753
18824 {12351, 3298, 4, 5 },
18825 // AArch64::ST4Fourv4h_POST - 754
18826 {12371, 3303, 4, 5 },
18827 // AArch64::ST4Fourv4s_POST - 755
18828 {12391, 3308, 4, 5 },
18829 // AArch64::ST4Fourv8b_POST - 756
18830 {12411, 3313, 4, 5 },
18831 // AArch64::ST4Fourv8h_POST - 757
18832 {12431, 3318, 4, 5 },
18833 // AArch64::ST4H_IMM - 758
18834 {12451, 3323, 4, 5 },
18835 // AArch64::ST4W_IMM - 759
18836 {12473, 3328, 4, 5 },
18837 // AArch64::ST4i16_POST - 760
18838 {12495, 3333, 5, 6 },
18839 // AArch64::ST4i32_POST - 761
18840 {12518, 3339, 5, 6 },
18841 // AArch64::ST4i64_POST - 762
18842 {12542, 3345, 5, 6 },
18843 // AArch64::ST4i8_POST - 763
18844 {12566, 3351, 5, 6 },
18845 // AArch64::STGOffset - 764
18846 {12589, 3357, 3, 4 },
18847 // AArch64::STGPi - 765
18848 {12602, 3361, 4, 5 },
18849 // AArch64::STLURBi - 766
18850 {12620, 3366, 3, 4 },
18851 // AArch64::STLURHi - 767
18852 {12636, 3370, 3, 4 },
18853 // AArch64::STLURWi - 768
18854 {12652, 3374, 3, 4 },
18855 // AArch64::STLURXi - 769
18856 {12652, 3378, 3, 4 },
18857 // AArch64::STNPDi - 770
18858 {12667, 3382, 4, 4 },
18859 // AArch64::STNPQi - 771
18860 {12667, 3386, 4, 4 },
18861 // AArch64::STNPSi - 772
18862 {12667, 3390, 4, 4 },
18863 // AArch64::STNPWi - 773
18864 {12667, 3394, 4, 4 },
18865 // AArch64::STNPXi - 774
18866 {12667, 3398, 4, 4 },
18867 // AArch64::STNT1B_ZRI - 775
18868 {12685, 3402, 4, 5 },
18869 // AArch64::STNT1B_ZZR_D_REAL - 776
18870 {12709, 3407, 4, 5 },
18871 // AArch64::STNT1B_ZZR_S_REAL - 777
18872 {12735, 3412, 4, 5 },
18873 // AArch64::STNT1D_ZRI - 778
18874 {12761, 3417, 4, 5 },
18875 // AArch64::STNT1D_ZZR_D_REAL - 779
18876 {12785, 3422, 4, 5 },
18877 // AArch64::STNT1H_ZRI - 780
18878 {12811, 3427, 4, 5 },
18879 // AArch64::STNT1H_ZZR_D_REAL - 781
18880 {12835, 3432, 4, 5 },
18881 // AArch64::STNT1H_ZZR_S_REAL - 782
18882 {12861, 3437, 4, 5 },
18883 // AArch64::STNT1W_ZRI - 783
18884 {12887, 3442, 4, 5 },
18885 // AArch64::STNT1W_ZZR_D_REAL - 784
18886 {12911, 3447, 4, 5 },
18887 // AArch64::STNT1W_ZZR_S_REAL - 785
18888 {12937, 3452, 4, 5 },
18889 // AArch64::STPDi - 786
18890 {12963, 3457, 4, 4 },
18891 // AArch64::STPQi - 787
18892 {12963, 3461, 4, 4 },
18893 // AArch64::STPSi - 788
18894 {12963, 3465, 4, 4 },
18895 // AArch64::STPWi - 789
18896 {12963, 3469, 4, 4 },
18897 // AArch64::STPXi - 790
18898 {12963, 3473, 4, 4 },
18899 // AArch64::STRBBroX - 791
18900 {12980, 3477, 5, 5 },
18901 // AArch64::STRBBui - 792
18902 {12998, 3482, 3, 3 },
18903 // AArch64::STRBroX - 793
18904 {13012, 3485, 5, 5 },
18905 // AArch64::STRBui - 794
18906 {13029, 3490, 3, 3 },
18907 // AArch64::STRDroX - 795
18908 {13012, 3493, 5, 5 },
18909 // AArch64::STRDui - 796
18910 {13029, 3498, 3, 3 },
18911 // AArch64::STRHHroX - 797
18912 {13042, 3501, 5, 5 },
18913 // AArch64::STRHHui - 798
18914 {13060, 3506, 3, 3 },
18915 // AArch64::STRHroX - 799
18916 {13012, 3509, 5, 5 },
18917 // AArch64::STRHui - 800
18918 {13029, 3514, 3, 3 },
18919 // AArch64::STRQroX - 801
18920 {13012, 3517, 5, 5 },
18921 // AArch64::STRQui - 802
18922 {13029, 3522, 3, 3 },
18923 // AArch64::STRSroX - 803
18924 {13012, 3525, 5, 5 },
18925 // AArch64::STRSui - 804
18926 {13029, 3530, 3, 3 },
18927 // AArch64::STRWroX - 805
18928 {13012, 3533, 5, 5 },
18929 // AArch64::STRWui - 806
18930 {13029, 3538, 3, 3 },
18931 // AArch64::STRXroX - 807
18932 {13012, 3541, 5, 5 },
18933 // AArch64::STRXui - 808
18934 {13029, 3546, 3, 3 },
18935 // AArch64::STR_PXI - 809
18936 {13074, 3549, 3, 4 },
18937 // AArch64::STR_ZXI - 810
18938 {13074, 3553, 3, 4 },
18939 // AArch64::STTRBi - 811
18940 {13089, 3557, 3, 3 },
18941 // AArch64::STTRHi - 812
18942 {13104, 3560, 3, 3 },
18943 // AArch64::STTRWi - 813
18944 {13119, 3563, 3, 3 },
18945 // AArch64::STTRXi - 814
18946 {13119, 3566, 3, 3 },
18947 // AArch64::STURBBi - 815
18948 {13133, 3569, 3, 3 },
18949 // AArch64::STURBi - 816
18950 {13148, 3572, 3, 3 },
18951 // AArch64::STURDi - 817
18952 {13148, 3575, 3, 3 },
18953 // AArch64::STURHHi - 818
18954 {13162, 3578, 3, 3 },
18955 // AArch64::STURHi - 819
18956 {13148, 3581, 3, 3 },
18957 // AArch64::STURQi - 820
18958 {13148, 3584, 3, 3 },
18959 // AArch64::STURSi - 821
18960 {13148, 3587, 3, 3 },
18961 // AArch64::STURWi - 822
18962 {13148, 3590, 3, 3 },
18963 // AArch64::STURXi - 823
18964 {13148, 3593, 3, 3 },
18965 // AArch64::STZ2GOffset - 824
18966 {13177, 3596, 3, 4 },
18967 // AArch64::STZGOffset - 825
18968 {13192, 3600, 3, 4 },
18969 // AArch64::SUBSWri - 826
18970 {13206, 3604, 4, 2 },
18971 // AArch64::SUBSWrs - 827
18972 {13219, 3606, 4, 4 },
18973 {13230, 3610, 4, 3 },
18974 {13245, 3613, 4, 4 },
18975 {13257, 3617, 4, 3 },
18976 {13273, 3620, 4, 4 },
18977 // AArch64::SUBSWrx - 832
18978 {13219, 3624, 4, 4 },
18979 {13289, 3628, 4, 3 },
18980 {13273, 3631, 4, 4 },
18981 // AArch64::SUBSXri - 835
18982 {13206, 3635, 4, 2 },
18983 // AArch64::SUBSXrs - 836
18984 {13219, 3637, 4, 4 },
18985 {13230, 3641, 4, 3 },
18986 {13245, 3644, 4, 4 },
18987 {13257, 3648, 4, 3 },
18988 {13273, 3651, 4, 4 },
18989 // AArch64::SUBSXrx - 841
18990 {13289, 3655, 4, 3 },
18991 // AArch64::SUBSXrx64 - 842
18992 {13219, 3658, 4, 4 },
18993 {13289, 3662, 4, 3 },
18994 {13273, 3665, 4, 4 },
18995 // AArch64::SUBWrs - 845
18996 {13304, 3669, 4, 4 },
18997 {13315, 3673, 4, 3 },
18998 {13330, 3676, 4, 4 },
18999 // AArch64::SUBWrx - 848
19000 {13330, 3680, 4, 4 },
19001 {13330, 3684, 4, 4 },
19002 // AArch64::SUBXrs - 850
19003 {13304, 3688, 4, 4 },
19004 {13315, 3692, 4, 3 },
19005 {13330, 3695, 4, 4 },
19006 // AArch64::SUBXrx64 - 853
19007 {13330, 3699, 4, 4 },
19008 {13330, 3703, 4, 4 },
19009 // AArch64::SYSxt - 855
19010 {13345, 3707, 5, 5 },
19011 // AArch64::UBFMWri - 856
19012 {13368, 3712, 4, 4 },
19013 {13383, 3716, 4, 4 },
19014 {13395, 3720, 4, 4 },
19015 // AArch64::UBFMXri - 859
19016 {13368, 3724, 4, 4 },
19017 {13383, 3728, 4, 4 },
19018 {13395, 3732, 4, 4 },
19019 {13407, 3736, 4, 4 },
19020 // AArch64::UMADDLrrr - 863
19021 {13419, 3740, 4, 4 },
19022 // AArch64::UMOVvi32 - 864
19023 {13436, 3744, 3, 3 },
19024 // AArch64::UMOVvi64 - 865
19025 {13455, 3747, 3, 3 },
19026 // AArch64::UMSUBLrrr - 866
19027 {13474, 3750, 4, 4 },
19028 // AArch64::UQDECB_WPiI - 867
19029 {13492, 3754, 4, 5 },
19030 {13502, 3759, 4, 5 },
19031 // AArch64::UQDECB_XPiI - 869
19032 {13492, 3764, 4, 5 },
19033 {13502, 3769, 4, 5 },
19034 // AArch64::UQDECD_WPiI - 871
19035 {13518, 3774, 4, 5 },
19036 {13528, 3779, 4, 5 },
19037 // AArch64::UQDECD_XPiI - 873
19038 {13518, 3784, 4, 5 },
19039 {13528, 3789, 4, 5 },
19040 // AArch64::UQDECD_ZPiI - 875
19041 {13544, 3794, 4, 5 },
19042 {13556, 3799, 4, 5 },
19043 // AArch64::UQDECH_WPiI - 877
19044 {13574, 3804, 4, 5 },
19045 {13584, 3809, 4, 5 },
19046 // AArch64::UQDECH_XPiI - 879
19047 {13574, 3814, 4, 5 },
19048 {13584, 3819, 4, 5 },
19049 // AArch64::UQDECH_ZPiI - 881
19050 {13600, 3824, 4, 5 },
19051 {13612, 3829, 4, 5 },
19052 // AArch64::UQDECW_WPiI - 883
19053 {13630, 3834, 4, 5 },
19054 {13640, 3839, 4, 5 },
19055 // AArch64::UQDECW_XPiI - 885
19056 {13630, 3844, 4, 5 },
19057 {13640, 3849, 4, 5 },
19058 // AArch64::UQDECW_ZPiI - 887
19059 {13656, 3854, 4, 5 },
19060 {13668, 3859, 4, 5 },
19061 // AArch64::UQINCB_WPiI - 889
19062 {13686, 3864, 4, 5 },
19063 {13696, 3869, 4, 5 },
19064 // AArch64::UQINCB_XPiI - 891
19065 {13686, 3874, 4, 5 },
19066 {13696, 3879, 4, 5 },
19067 // AArch64::UQINCD_WPiI - 893
19068 {13712, 3884, 4, 5 },
19069 {13722, 3889, 4, 5 },
19070 // AArch64::UQINCD_XPiI - 895
19071 {13712, 3894, 4, 5 },
19072 {13722, 3899, 4, 5 },
19073 // AArch64::UQINCD_ZPiI - 897
19074 {13738, 3904, 4, 5 },
19075 {13750, 3909, 4, 5 },
19076 // AArch64::UQINCH_WPiI - 899
19077 {13768, 3914, 4, 5 },
19078 {13778, 3919, 4, 5 },
19079 // AArch64::UQINCH_XPiI - 901
19080 {13768, 3924, 4, 5 },
19081 {13778, 3929, 4, 5 },
19082 // AArch64::UQINCH_ZPiI - 903
19083 {13794, 3934, 4, 5 },
19084 {13806, 3939, 4, 5 },
19085 // AArch64::UQINCW_WPiI - 905
19086 {13824, 3944, 4, 5 },
19087 {13834, 3949, 4, 5 },
19088 // AArch64::UQINCW_XPiI - 907
19089 {13824, 3954, 4, 5 },
19090 {13834, 3959, 4, 5 },
19091 // AArch64::UQINCW_ZPiI - 909
19092 {13850, 3964, 4, 5 },
19093 {13862, 3969, 4, 5 },
19094 // AArch64::XPACLRI - 911
19095 {13880, 3974, 0, 1 },
19096 };
19097
19098 static const AliasPatternCond Conds[] = {
19099 // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 0
19100 {AliasPatternCond::K_Reg, AArch64::WZR},
19101 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
19102 // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 2
19103 {AliasPatternCond::K_Reg, AArch64::WZR},
19104 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19105 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19106 {AliasPatternCond::K_Imm, uint32_t(0)},
19107 // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - 6
19108 {AliasPatternCond::K_Reg, AArch64::WZR},
19109 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19110 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19111 // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 9
19112 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19113 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19114 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19115 {AliasPatternCond::K_Imm, uint32_t(0)},
19116 // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - 13
19117 {AliasPatternCond::K_Reg, AArch64::WZR},
19118 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
19119 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19120 {AliasPatternCond::K_Imm, uint32_t(16)},
19121 // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - 17
19122 {AliasPatternCond::K_Reg, AArch64::WZR},
19123 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
19124 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19125 // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 20
19126 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19127 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
19128 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19129 {AliasPatternCond::K_Imm, uint32_t(16)},
19130 // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 24
19131 {AliasPatternCond::K_Reg, AArch64::XZR},
19132 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19133 // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 26
19134 {AliasPatternCond::K_Reg, AArch64::XZR},
19135 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19136 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19137 {AliasPatternCond::K_Imm, uint32_t(0)},
19138 // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - 30
19139 {AliasPatternCond::K_Reg, AArch64::XZR},
19140 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19141 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19142 // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 33
19143 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19144 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19145 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19146 {AliasPatternCond::K_Imm, uint32_t(0)},
19147 // (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - 37
19148 {AliasPatternCond::K_Reg, AArch64::XZR},
19149 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19150 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19151 // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 40
19152 {AliasPatternCond::K_Reg, AArch64::XZR},
19153 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
19154 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19155 {AliasPatternCond::K_Imm, uint32_t(24)},
19156 // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 44
19157 {AliasPatternCond::K_Reg, AArch64::XZR},
19158 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19159 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19160 // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 47
19161 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19162 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
19163 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19164 {AliasPatternCond::K_Imm, uint32_t(24)},
19165 // (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0) - 51
19166 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
19167 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
19168 {AliasPatternCond::K_Imm, uint32_t(0)},
19169 {AliasPatternCond::K_Imm, uint32_t(0)},
19170 // (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0) - 55
19171 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
19172 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
19173 {AliasPatternCond::K_Imm, uint32_t(0)},
19174 {AliasPatternCond::K_Imm, uint32_t(0)},
19175 // (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 59
19176 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19177 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19178 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19179 {AliasPatternCond::K_Imm, uint32_t(0)},
19180 // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - 63
19181 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
19182 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
19183 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19184 {AliasPatternCond::K_Imm, uint32_t(16)},
19185 // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 67
19186 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
19187 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
19188 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19189 {AliasPatternCond::K_Imm, uint32_t(16)},
19190 // (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0) - 71
19191 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
19192 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19193 {AliasPatternCond::K_Imm, uint32_t(0)},
19194 {AliasPatternCond::K_Imm, uint32_t(0)},
19195 // (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0) - 75
19196 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19197 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
19198 {AliasPatternCond::K_Imm, uint32_t(0)},
19199 {AliasPatternCond::K_Imm, uint32_t(0)},
19200 // (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 79
19201 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19202 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19203 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19204 {AliasPatternCond::K_Imm, uint32_t(0)},
19205 // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 83
19206 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
19207 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19208 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19209 {AliasPatternCond::K_Imm, uint32_t(24)},
19210 // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 87
19211 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19212 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
19213 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19214 {AliasPatternCond::K_Imm, uint32_t(24)},
19215 // (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) - 91
19216 {AliasPatternCond::K_Reg, AArch64::WZR},
19217 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19218 // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 93
19219 {AliasPatternCond::K_Reg, AArch64::WZR},
19220 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19221 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19222 {AliasPatternCond::K_Imm, uint32_t(0)},
19223 // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh) - 97
19224 {AliasPatternCond::K_Reg, AArch64::WZR},
19225 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19226 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19227 // (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 100
19228 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19229 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19230 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19231 {AliasPatternCond::K_Imm, uint32_t(0)},
19232 // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) - 104
19233 {AliasPatternCond::K_Reg, AArch64::XZR},
19234 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19235 // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 106
19236 {AliasPatternCond::K_Reg, AArch64::XZR},
19237 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19238 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19239 {AliasPatternCond::K_Imm, uint32_t(0)},
19240 // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh) - 110
19241 {AliasPatternCond::K_Reg, AArch64::XZR},
19242 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19243 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19244 // (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 113
19245 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19246 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19247 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19248 {AliasPatternCond::K_Imm, uint32_t(0)},
19249 // (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 117
19250 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19251 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19252 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19253 {AliasPatternCond::K_TiedReg, 2},
19254 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19255 // (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 122
19256 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19257 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19258 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19259 {AliasPatternCond::K_Imm, uint32_t(0)},
19260 // (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 126
19261 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19262 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19263 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19264 {AliasPatternCond::K_Imm, uint32_t(0)},
19265 // (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 130
19266 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19267 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19268 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19269 {AliasPatternCond::K_TiedReg, 2},
19270 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19271 // (AND_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 135
19272 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19273 {AliasPatternCond::K_Ignore, 0},
19274 {AliasPatternCond::K_Custom, 1},
19275 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19276 // (AND_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 139
19277 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19278 {AliasPatternCond::K_Ignore, 0},
19279 {AliasPatternCond::K_Custom, 2},
19280 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19281 // (AND_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 143
19282 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19283 {AliasPatternCond::K_Ignore, 0},
19284 {AliasPatternCond::K_Custom, 3},
19285 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19286 // (AUTIA1716) - 147
19287 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
19288 // (AUTIASP) - 148
19289 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
19290 // (AUTIAZ) - 149
19291 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
19292 // (AUTIB1716) - 150
19293 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
19294 // (AUTIBSP) - 151
19295 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
19296 // (AUTIBZ) - 152
19297 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
19298 // (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 153
19299 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19300 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19301 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19302 {AliasPatternCond::K_Imm, uint32_t(0)},
19303 // (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 157
19304 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19305 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19306 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19307 {AliasPatternCond::K_Imm, uint32_t(0)},
19308 // (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 161
19309 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19310 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19311 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19312 {AliasPatternCond::K_Imm, uint32_t(0)},
19313 // (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 165
19314 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19315 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19316 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19317 {AliasPatternCond::K_Imm, uint32_t(0)},
19318 // (CLREX 15) - 169
19319 {AliasPatternCond::K_Imm, uint32_t(15)},
19320 // (CNTB_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 170
19321 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19322 {AliasPatternCond::K_Imm, uint32_t(31)},
19323 {AliasPatternCond::K_Imm, uint32_t(1)},
19324 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19325 // (CNTB_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 174
19326 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19327 {AliasPatternCond::K_Ignore, 0},
19328 {AliasPatternCond::K_Imm, uint32_t(1)},
19329 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19330 // (CNTD_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 178
19331 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19332 {AliasPatternCond::K_Imm, uint32_t(31)},
19333 {AliasPatternCond::K_Imm, uint32_t(1)},
19334 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19335 // (CNTD_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 182
19336 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19337 {AliasPatternCond::K_Ignore, 0},
19338 {AliasPatternCond::K_Imm, uint32_t(1)},
19339 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19340 // (CNTH_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 186
19341 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19342 {AliasPatternCond::K_Imm, uint32_t(31)},
19343 {AliasPatternCond::K_Imm, uint32_t(1)},
19344 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19345 // (CNTH_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 190
19346 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19347 {AliasPatternCond::K_Ignore, 0},
19348 {AliasPatternCond::K_Imm, uint32_t(1)},
19349 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19350 // (CNTW_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 194
19351 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19352 {AliasPatternCond::K_Imm, uint32_t(31)},
19353 {AliasPatternCond::K_Imm, uint32_t(1)},
19354 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19355 // (CNTW_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 198
19356 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19357 {AliasPatternCond::K_Ignore, 0},
19358 {AliasPatternCond::K_Imm, uint32_t(1)},
19359 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19360 // (CPY_ZPmI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 202
19361 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19362 {AliasPatternCond::K_Ignore, 0},
19363 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19364 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19365 // (CPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 206
19366 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19367 {AliasPatternCond::K_Ignore, 0},
19368 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19369 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19370 // (CPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 210
19371 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19372 {AliasPatternCond::K_Ignore, 0},
19373 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19374 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19375 // (CPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 214
19376 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19377 {AliasPatternCond::K_Ignore, 0},
19378 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19379 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19380 // (CPY_ZPmR_B ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 218
19381 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19382 {AliasPatternCond::K_Ignore, 0},
19383 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19384 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
19385 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19386 // (CPY_ZPmR_D ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn) - 223
19387 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19388 {AliasPatternCond::K_Ignore, 0},
19389 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19390 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19391 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19392 // (CPY_ZPmR_H ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 228
19393 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19394 {AliasPatternCond::K_Ignore, 0},
19395 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19396 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
19397 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19398 // (CPY_ZPmR_S ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 233
19399 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19400 {AliasPatternCond::K_Ignore, 0},
19401 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19402 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
19403 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19404 // (CPY_ZPmV_B ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn) - 238
19405 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19406 {AliasPatternCond::K_Ignore, 0},
19407 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19408 {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID},
19409 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19410 // (CPY_ZPmV_D ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn) - 243
19411 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19412 {AliasPatternCond::K_Ignore, 0},
19413 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19414 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
19415 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19416 // (CPY_ZPmV_H ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn) - 248
19417 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19418 {AliasPatternCond::K_Ignore, 0},
19419 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19420 {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID},
19421 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19422 // (CPY_ZPmV_S ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn) - 253
19423 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19424 {AliasPatternCond::K_Ignore, 0},
19425 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19426 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
19427 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19428 // (CPY_ZPzI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 258
19429 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19430 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19431 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19432 // (CPY_ZPzI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 261
19433 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19434 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19435 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19436 // (CPY_ZPzI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 264
19437 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19438 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19439 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19440 // (CPY_ZPzI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 267
19441 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19442 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19443 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19444 // (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 270
19445 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19446 {AliasPatternCond::K_Reg, AArch64::WZR},
19447 {AliasPatternCond::K_Reg, AArch64::WZR},
19448 {AliasPatternCond::K_Custom, 4},
19449 // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 274
19450 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19451 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19452 {AliasPatternCond::K_TiedReg, 1},
19453 {AliasPatternCond::K_Custom, 4},
19454 // (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 278
19455 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19456 {AliasPatternCond::K_Reg, AArch64::XZR},
19457 {AliasPatternCond::K_Reg, AArch64::XZR},
19458 {AliasPatternCond::K_Custom, 4},
19459 // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 282
19460 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19461 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19462 {AliasPatternCond::K_TiedReg, 1},
19463 {AliasPatternCond::K_Custom, 4},
19464 // (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 286
19465 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19466 {AliasPatternCond::K_Reg, AArch64::WZR},
19467 {AliasPatternCond::K_Reg, AArch64::WZR},
19468 {AliasPatternCond::K_Custom, 4},
19469 // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 290
19470 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19471 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19472 {AliasPatternCond::K_TiedReg, 1},
19473 {AliasPatternCond::K_Custom, 4},
19474 // (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 294
19475 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19476 {AliasPatternCond::K_Reg, AArch64::XZR},
19477 {AliasPatternCond::K_Reg, AArch64::XZR},
19478 {AliasPatternCond::K_Custom, 4},
19479 // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 298
19480 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19481 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19482 {AliasPatternCond::K_TiedReg, 1},
19483 {AliasPatternCond::K_Custom, 4},
19484 // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 302
19485 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19486 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19487 {AliasPatternCond::K_TiedReg, 1},
19488 {AliasPatternCond::K_Custom, 4},
19489 // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 306
19490 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19491 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19492 {AliasPatternCond::K_TiedReg, 1},
19493 {AliasPatternCond::K_Custom, 4},
19494 // (DCPS1 0) - 310
19495 {AliasPatternCond::K_Imm, uint32_t(0)},
19496 // (DCPS2 0) - 311
19497 {AliasPatternCond::K_Imm, uint32_t(0)},
19498 // (DCPS3 0) - 312
19499 {AliasPatternCond::K_Imm, uint32_t(0)},
19500 // (DECB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 313
19501 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19502 {AliasPatternCond::K_Ignore, 0},
19503 {AliasPatternCond::K_Imm, uint32_t(31)},
19504 {AliasPatternCond::K_Imm, uint32_t(1)},
19505 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19506 // (DECB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 318
19507 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19508 {AliasPatternCond::K_Ignore, 0},
19509 {AliasPatternCond::K_Ignore, 0},
19510 {AliasPatternCond::K_Imm, uint32_t(1)},
19511 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19512 // (DECD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 323
19513 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19514 {AliasPatternCond::K_Ignore, 0},
19515 {AliasPatternCond::K_Imm, uint32_t(31)},
19516 {AliasPatternCond::K_Imm, uint32_t(1)},
19517 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19518 // (DECD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 328
19519 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19520 {AliasPatternCond::K_Ignore, 0},
19521 {AliasPatternCond::K_Ignore, 0},
19522 {AliasPatternCond::K_Imm, uint32_t(1)},
19523 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19524 // (DECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 333
19525 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19526 {AliasPatternCond::K_Ignore, 0},
19527 {AliasPatternCond::K_Imm, uint32_t(31)},
19528 {AliasPatternCond::K_Imm, uint32_t(1)},
19529 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19530 // (DECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 338
19531 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19532 {AliasPatternCond::K_Ignore, 0},
19533 {AliasPatternCond::K_Ignore, 0},
19534 {AliasPatternCond::K_Imm, uint32_t(1)},
19535 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19536 // (DECH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 343
19537 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19538 {AliasPatternCond::K_Ignore, 0},
19539 {AliasPatternCond::K_Imm, uint32_t(31)},
19540 {AliasPatternCond::K_Imm, uint32_t(1)},
19541 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19542 // (DECH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 348
19543 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19544 {AliasPatternCond::K_Ignore, 0},
19545 {AliasPatternCond::K_Ignore, 0},
19546 {AliasPatternCond::K_Imm, uint32_t(1)},
19547 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19548 // (DECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 353
19549 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19550 {AliasPatternCond::K_Ignore, 0},
19551 {AliasPatternCond::K_Imm, uint32_t(31)},
19552 {AliasPatternCond::K_Imm, uint32_t(1)},
19553 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19554 // (DECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 358
19555 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19556 {AliasPatternCond::K_Ignore, 0},
19557 {AliasPatternCond::K_Ignore, 0},
19558 {AliasPatternCond::K_Imm, uint32_t(1)},
19559 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19560 // (DECW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 363
19561 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19562 {AliasPatternCond::K_Ignore, 0},
19563 {AliasPatternCond::K_Imm, uint32_t(31)},
19564 {AliasPatternCond::K_Imm, uint32_t(1)},
19565 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19566 // (DECW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 368
19567 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19568 {AliasPatternCond::K_Ignore, 0},
19569 {AliasPatternCond::K_Ignore, 0},
19570 {AliasPatternCond::K_Imm, uint32_t(1)},
19571 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19572 // (DECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 373
19573 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19574 {AliasPatternCond::K_Ignore, 0},
19575 {AliasPatternCond::K_Imm, uint32_t(31)},
19576 {AliasPatternCond::K_Imm, uint32_t(1)},
19577 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19578 // (DECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 378
19579 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19580 {AliasPatternCond::K_Ignore, 0},
19581 {AliasPatternCond::K_Ignore, 0},
19582 {AliasPatternCond::K_Imm, uint32_t(1)},
19583 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19584 // (DSB 0) - 383
19585 {AliasPatternCond::K_Imm, uint32_t(0)},
19586 // (DSB 4) - 384
19587 {AliasPatternCond::K_Imm, uint32_t(4)},
19588 // (DUPM_ZI ZPR16:$Zd, sve_preferred_logical_imm16:$imm) - 385
19589 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19590 {AliasPatternCond::K_Custom, 5},
19591 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19592 // (DUPM_ZI ZPR32:$Zd, sve_preferred_logical_imm32:$imm) - 388
19593 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19594 {AliasPatternCond::K_Custom, 6},
19595 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19596 // (DUPM_ZI ZPR64:$Zd, sve_preferred_logical_imm64:$imm) - 391
19597 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19598 {AliasPatternCond::K_Custom, 7},
19599 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19600 // (DUPM_ZI ZPR8:$Zd, sve_logical_imm8:$imm) - 394
19601 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19602 {AliasPatternCond::K_Custom, 1},
19603 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19604 // (DUPM_ZI ZPR16:$Zd, sve_logical_imm16:$imm) - 397
19605 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19606 {AliasPatternCond::K_Custom, 2},
19607 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19608 // (DUPM_ZI ZPR32:$Zd, sve_logical_imm32:$imm) - 400
19609 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19610 {AliasPatternCond::K_Custom, 3},
19611 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19612 // (DUP_ZI_B ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm) - 403
19613 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19614 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19615 // (DUP_ZI_D ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm) - 405
19616 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19617 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19618 // (DUP_ZI_D ZPR64:$Zd, 0, 0) - 407
19619 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19620 {AliasPatternCond::K_Imm, uint32_t(0)},
19621 {AliasPatternCond::K_Imm, uint32_t(0)},
19622 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19623 // (DUP_ZI_H ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm) - 411
19624 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19625 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19626 // (DUP_ZI_H ZPR16:$Zd, 0, 0) - 413
19627 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19628 {AliasPatternCond::K_Imm, uint32_t(0)},
19629 {AliasPatternCond::K_Imm, uint32_t(0)},
19630 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19631 // (DUP_ZI_S ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm) - 417
19632 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19633 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19634 // (DUP_ZI_S ZPR32:$Zd, 0, 0) - 419
19635 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19636 {AliasPatternCond::K_Imm, uint32_t(0)},
19637 {AliasPatternCond::K_Imm, uint32_t(0)},
19638 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19639 // (DUP_ZR_B ZPR8:$Zd, GPR32sp:$Rn) - 423
19640 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19641 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
19642 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19643 // (DUP_ZR_D ZPR64:$Zd, GPR64sp:$Rn) - 426
19644 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19645 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
19646 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19647 // (DUP_ZR_H ZPR16:$Zd, GPR32sp:$Rn) - 429
19648 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19649 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
19650 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19651 // (DUP_ZR_S ZPR32:$Zd, GPR32sp:$Rn) - 432
19652 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19653 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
19654 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19655 // (DUP_ZZI_B ZPR8:$Zd, FPR8asZPR:$Bn, 0) - 435
19656 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19657 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19658 {AliasPatternCond::K_Imm, uint32_t(0)},
19659 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19660 // (DUP_ZZI_B ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx) - 439
19661 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19662 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19663 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19664 // (DUP_ZZI_D ZPR64:$Zd, FPR64asZPR:$Dn, 0) - 442
19665 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19666 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19667 {AliasPatternCond::K_Imm, uint32_t(0)},
19668 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19669 // (DUP_ZZI_D ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx) - 446
19670 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19671 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19672 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19673 // (DUP_ZZI_H ZPR16:$Zd, FPR16asZPR:$Hn, 0) - 449
19674 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19675 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19676 {AliasPatternCond::K_Imm, uint32_t(0)},
19677 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19678 // (DUP_ZZI_H ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx) - 453
19679 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19680 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19681 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19682 // (DUP_ZZI_Q ZPR128:$Zd, FPR128asZPR:$Qn, 0) - 456
19683 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19684 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19685 {AliasPatternCond::K_Imm, uint32_t(0)},
19686 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19687 // (DUP_ZZI_Q ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx) - 460
19688 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19689 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19690 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19691 // (DUP_ZZI_S ZPR32:$Zd, FPR32asZPR:$Sn, 0) - 463
19692 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19693 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19694 {AliasPatternCond::K_Imm, uint32_t(0)},
19695 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19696 // (DUP_ZZI_S ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx) - 467
19697 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19698 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19699 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19700 // (EONWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 470
19701 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19702 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19703 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19704 {AliasPatternCond::K_Imm, uint32_t(0)},
19705 // (EONXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 474
19706 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19707 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19708 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19709 {AliasPatternCond::K_Imm, uint32_t(0)},
19710 // (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 478
19711 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19712 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19713 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19714 {AliasPatternCond::K_TiedReg, 1},
19715 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19716 // (EORWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 483
19717 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19718 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19719 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19720 {AliasPatternCond::K_Imm, uint32_t(0)},
19721 // (EORXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 487
19722 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19723 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19724 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19725 {AliasPatternCond::K_Imm, uint32_t(0)},
19726 // (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 491
19727 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19728 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19729 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19730 {AliasPatternCond::K_TiedReg, 1},
19731 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19732 // (EOR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 496
19733 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19734 {AliasPatternCond::K_Ignore, 0},
19735 {AliasPatternCond::K_Custom, 1},
19736 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19737 // (EOR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 500
19738 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19739 {AliasPatternCond::K_Ignore, 0},
19740 {AliasPatternCond::K_Custom, 2},
19741 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19742 // (EOR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 504
19743 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19744 {AliasPatternCond::K_Ignore, 0},
19745 {AliasPatternCond::K_Custom, 3},
19746 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19747 // (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) - 508
19748 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19749 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
19750 {AliasPatternCond::K_TiedReg, 1},
19751 // (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) - 511
19752 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19753 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19754 {AliasPatternCond::K_TiedReg, 1},
19755 // (FCPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8) - 514
19756 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19757 {AliasPatternCond::K_Ignore, 0},
19758 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19759 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19760 // (FCPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8) - 518
19761 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19762 {AliasPatternCond::K_Ignore, 0},
19763 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19764 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19765 // (FCPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8) - 522
19766 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19767 {AliasPatternCond::K_Ignore, 0},
19768 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
19769 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19770 // (FDUP_ZI_D ZPR64:$Zd, fpimm64:$imm8) - 526
19771 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19772 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19773 // (FDUP_ZI_H ZPR16:$Zd, fpimm16:$imm8) - 528
19774 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19775 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19776 // (FDUP_ZI_S ZPR32:$Zd, fpimm32:$imm8) - 530
19777 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19778 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19779 // (GLD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 532
19780 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19781 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19782 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19783 {AliasPatternCond::K_Imm, uint32_t(0)},
19784 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19785 // (GLD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 537
19786 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19787 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19788 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19789 {AliasPatternCond::K_Imm, uint32_t(0)},
19790 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19791 // (GLD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 542
19792 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19793 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19794 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19795 {AliasPatternCond::K_Imm, uint32_t(0)},
19796 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19797 // (GLD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 547
19798 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19799 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19800 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19801 {AliasPatternCond::K_Imm, uint32_t(0)},
19802 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19803 // (GLD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 552
19804 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19805 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19806 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19807 {AliasPatternCond::K_Imm, uint32_t(0)},
19808 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19809 // (GLD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 557
19810 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19811 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19812 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19813 {AliasPatternCond::K_Imm, uint32_t(0)},
19814 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19815 // (GLD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 562
19816 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19817 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19818 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19819 {AliasPatternCond::K_Imm, uint32_t(0)},
19820 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19821 // (GLD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 567
19822 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19823 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19824 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19825 {AliasPatternCond::K_Imm, uint32_t(0)},
19826 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19827 // (GLD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 572
19828 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19829 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19830 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19831 {AliasPatternCond::K_Imm, uint32_t(0)},
19832 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19833 // (GLD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 577
19834 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19835 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19836 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19837 {AliasPatternCond::K_Imm, uint32_t(0)},
19838 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19839 // (GLD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 582
19840 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19841 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19842 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19843 {AliasPatternCond::K_Imm, uint32_t(0)},
19844 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19845 // (GLD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 587
19846 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19847 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19848 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19849 {AliasPatternCond::K_Imm, uint32_t(0)},
19850 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19851 // (GLDFF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 592
19852 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19853 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19854 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19855 {AliasPatternCond::K_Imm, uint32_t(0)},
19856 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19857 // (GLDFF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 597
19858 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19859 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19860 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19861 {AliasPatternCond::K_Imm, uint32_t(0)},
19862 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19863 // (GLDFF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 602
19864 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19865 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19866 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19867 {AliasPatternCond::K_Imm, uint32_t(0)},
19868 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19869 // (GLDFF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 607
19870 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19871 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19872 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19873 {AliasPatternCond::K_Imm, uint32_t(0)},
19874 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19875 // (GLDFF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 612
19876 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19877 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19878 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19879 {AliasPatternCond::K_Imm, uint32_t(0)},
19880 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19881 // (GLDFF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 617
19882 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19883 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19884 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19885 {AliasPatternCond::K_Imm, uint32_t(0)},
19886 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19887 // (GLDFF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 622
19888 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19889 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19890 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19891 {AliasPatternCond::K_Imm, uint32_t(0)},
19892 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19893 // (GLDFF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 627
19894 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19895 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19896 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19897 {AliasPatternCond::K_Imm, uint32_t(0)},
19898 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19899 // (GLDFF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 632
19900 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19901 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19902 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19903 {AliasPatternCond::K_Imm, uint32_t(0)},
19904 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19905 // (GLDFF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 637
19906 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19907 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19908 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19909 {AliasPatternCond::K_Imm, uint32_t(0)},
19910 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19911 // (GLDFF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 642
19912 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19913 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19914 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19915 {AliasPatternCond::K_Imm, uint32_t(0)},
19916 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19917 // (GLDFF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 647
19918 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19919 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
19920 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19921 {AliasPatternCond::K_Imm, uint32_t(0)},
19922 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19923 // (HINT { 0, 0, 0 }) - 652
19924 {AliasPatternCond::K_Imm, uint32_t(0)},
19925 // (HINT { 0, 0, 1 }) - 653
19926 {AliasPatternCond::K_Imm, uint32_t(1)},
19927 // (HINT { 0, 1, 0 }) - 654
19928 {AliasPatternCond::K_Imm, uint32_t(2)},
19929 // (HINT { 0, 1, 1 }) - 655
19930 {AliasPatternCond::K_Imm, uint32_t(3)},
19931 // (HINT { 1, 0, 0 }) - 656
19932 {AliasPatternCond::K_Imm, uint32_t(4)},
19933 // (HINT { 1, 0, 1 }) - 657
19934 {AliasPatternCond::K_Imm, uint32_t(5)},
19935 // (HINT { 1, 1, 0 }) - 658
19936 {AliasPatternCond::K_Imm, uint32_t(6)},
19937 // (HINT { 1, 0, 0, 0, 0 }) - 659
19938 {AliasPatternCond::K_Imm, uint32_t(16)},
19939 {AliasPatternCond::K_Feature, AArch64::FeatureRAS},
19940 // (HINT 20) - 661
19941 {AliasPatternCond::K_Imm, uint32_t(20)},
19942 // (HINT 32) - 662
19943 {AliasPatternCond::K_Imm, uint32_t(32)},
19944 {AliasPatternCond::K_Feature, AArch64::FeatureBranchTargetId},
19945 // (HINT btihint_op:$op) - 664
19946 {AliasPatternCond::K_Custom, 8},
19947 {AliasPatternCond::K_Feature, AArch64::FeatureBranchTargetId},
19948 // (HINT psbhint_op:$op) - 666
19949 {AliasPatternCond::K_Custom, 9},
19950 {AliasPatternCond::K_Feature, AArch64::FeatureSPE},
19951 // (INCB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 668
19952 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19953 {AliasPatternCond::K_Ignore, 0},
19954 {AliasPatternCond::K_Imm, uint32_t(31)},
19955 {AliasPatternCond::K_Imm, uint32_t(1)},
19956 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19957 // (INCB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 673
19958 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19959 {AliasPatternCond::K_Ignore, 0},
19960 {AliasPatternCond::K_Ignore, 0},
19961 {AliasPatternCond::K_Imm, uint32_t(1)},
19962 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19963 // (INCD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 678
19964 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19965 {AliasPatternCond::K_Ignore, 0},
19966 {AliasPatternCond::K_Imm, uint32_t(31)},
19967 {AliasPatternCond::K_Imm, uint32_t(1)},
19968 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19969 // (INCD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 683
19970 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19971 {AliasPatternCond::K_Ignore, 0},
19972 {AliasPatternCond::K_Ignore, 0},
19973 {AliasPatternCond::K_Imm, uint32_t(1)},
19974 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19975 // (INCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 688
19976 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19977 {AliasPatternCond::K_Ignore, 0},
19978 {AliasPatternCond::K_Imm, uint32_t(31)},
19979 {AliasPatternCond::K_Imm, uint32_t(1)},
19980 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19981 // (INCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 693
19982 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
19983 {AliasPatternCond::K_Ignore, 0},
19984 {AliasPatternCond::K_Ignore, 0},
19985 {AliasPatternCond::K_Imm, uint32_t(1)},
19986 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19987 // (INCH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 698
19988 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19989 {AliasPatternCond::K_Ignore, 0},
19990 {AliasPatternCond::K_Imm, uint32_t(31)},
19991 {AliasPatternCond::K_Imm, uint32_t(1)},
19992 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19993 // (INCH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 703
19994 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
19995 {AliasPatternCond::K_Ignore, 0},
19996 {AliasPatternCond::K_Ignore, 0},
19997 {AliasPatternCond::K_Imm, uint32_t(1)},
19998 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
19999 // (INCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 708
20000 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20001 {AliasPatternCond::K_Ignore, 0},
20002 {AliasPatternCond::K_Imm, uint32_t(31)},
20003 {AliasPatternCond::K_Imm, uint32_t(1)},
20004 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20005 // (INCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 713
20006 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20007 {AliasPatternCond::K_Ignore, 0},
20008 {AliasPatternCond::K_Ignore, 0},
20009 {AliasPatternCond::K_Imm, uint32_t(1)},
20010 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20011 // (INCW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 718
20012 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20013 {AliasPatternCond::K_Ignore, 0},
20014 {AliasPatternCond::K_Imm, uint32_t(31)},
20015 {AliasPatternCond::K_Imm, uint32_t(1)},
20016 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20017 // (INCW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 723
20018 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20019 {AliasPatternCond::K_Ignore, 0},
20020 {AliasPatternCond::K_Ignore, 0},
20021 {AliasPatternCond::K_Imm, uint32_t(1)},
20022 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20023 // (INCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 728
20024 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20025 {AliasPatternCond::K_Ignore, 0},
20026 {AliasPatternCond::K_Imm, uint32_t(31)},
20027 {AliasPatternCond::K_Imm, uint32_t(1)},
20028 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20029 // (INCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 733
20030 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20031 {AliasPatternCond::K_Ignore, 0},
20032 {AliasPatternCond::K_Ignore, 0},
20033 {AliasPatternCond::K_Imm, uint32_t(1)},
20034 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20035 // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) - 738
20036 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20037 {AliasPatternCond::K_Ignore, 0},
20038 {AliasPatternCond::K_Ignore, 0},
20039 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20040 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20041 // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) - 743
20042 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20043 {AliasPatternCond::K_Ignore, 0},
20044 {AliasPatternCond::K_Ignore, 0},
20045 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20046 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20047 // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) - 748
20048 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20049 {AliasPatternCond::K_Ignore, 0},
20050 {AliasPatternCond::K_Ignore, 0},
20051 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20052 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20053 // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) - 753
20054 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20055 {AliasPatternCond::K_Ignore, 0},
20056 {AliasPatternCond::K_Ignore, 0},
20057 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20058 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20059 // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) - 758
20060 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20061 {AliasPatternCond::K_Ignore, 0},
20062 {AliasPatternCond::K_Ignore, 0},
20063 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
20064 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20065 // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) - 763
20066 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20067 {AliasPatternCond::K_Ignore, 0},
20068 {AliasPatternCond::K_Ignore, 0},
20069 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20070 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20071 // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) - 768
20072 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20073 {AliasPatternCond::K_Ignore, 0},
20074 {AliasPatternCond::K_Ignore, 0},
20075 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
20076 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20077 // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) - 773
20078 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20079 {AliasPatternCond::K_Ignore, 0},
20080 {AliasPatternCond::K_Ignore, 0},
20081 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20082 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20083 // (IRG GPR64sp:$dst, GPR64sp:$src, XZR) - 778
20084 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20085 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20086 {AliasPatternCond::K_Reg, AArch64::XZR},
20087 {AliasPatternCond::K_Feature, AArch64::FeatureMTE},
20088 // (ISB 15) - 782
20089 {AliasPatternCond::K_Imm, uint32_t(15)},
20090 // (LD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 783
20091 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20092 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20093 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20094 {AliasPatternCond::K_Imm, uint32_t(0)},
20095 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20096 // (LD1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 788
20097 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20098 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20099 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20100 {AliasPatternCond::K_Imm, uint32_t(0)},
20101 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20102 // (LD1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 793
20103 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20104 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20105 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20106 {AliasPatternCond::K_Imm, uint32_t(0)},
20107 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20108 // (LD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 798
20109 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20110 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20111 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20112 {AliasPatternCond::K_Imm, uint32_t(0)},
20113 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20114 // (LD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 803
20115 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20116 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20117 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20118 {AliasPatternCond::K_Imm, uint32_t(0)},
20119 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20120 // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 808
20121 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20122 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20123 {AliasPatternCond::K_Ignore, 0},
20124 {AliasPatternCond::K_Reg, AArch64::XZR},
20125 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20126 // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 813
20127 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20128 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20129 {AliasPatternCond::K_Ignore, 0},
20130 {AliasPatternCond::K_Reg, AArch64::XZR},
20131 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20132 // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 818
20133 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20134 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20135 {AliasPatternCond::K_Ignore, 0},
20136 {AliasPatternCond::K_Reg, AArch64::XZR},
20137 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20138 // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 823
20139 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20140 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20141 {AliasPatternCond::K_Ignore, 0},
20142 {AliasPatternCond::K_Reg, AArch64::XZR},
20143 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20144 // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 828
20145 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20146 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20147 {AliasPatternCond::K_Ignore, 0},
20148 {AliasPatternCond::K_Reg, AArch64::XZR},
20149 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20150 // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 833
20151 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20152 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20153 {AliasPatternCond::K_Ignore, 0},
20154 {AliasPatternCond::K_Reg, AArch64::XZR},
20155 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20156 // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 838
20157 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20158 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20159 {AliasPatternCond::K_Ignore, 0},
20160 {AliasPatternCond::K_Reg, AArch64::XZR},
20161 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20162 // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 843
20163 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20164 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20165 {AliasPatternCond::K_Ignore, 0},
20166 {AliasPatternCond::K_Reg, AArch64::XZR},
20167 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20168 // (LD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 848
20169 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20170 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20171 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20172 {AliasPatternCond::K_Imm, uint32_t(0)},
20173 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20174 // (LD1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 853
20175 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20176 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20177 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20178 {AliasPatternCond::K_Imm, uint32_t(0)},
20179 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20180 // (LD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 858
20181 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20182 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20183 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20184 {AliasPatternCond::K_Imm, uint32_t(0)},
20185 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20186 // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 863
20187 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20188 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20189 {AliasPatternCond::K_Ignore, 0},
20190 {AliasPatternCond::K_Reg, AArch64::XZR},
20191 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20192 // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 868
20193 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20194 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
20195 {AliasPatternCond::K_Ignore, 0},
20196 {AliasPatternCond::K_Reg, AArch64::XZR},
20197 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20198 // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 873
20199 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20200 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20201 {AliasPatternCond::K_Ignore, 0},
20202 {AliasPatternCond::K_Reg, AArch64::XZR},
20203 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20204 // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 878
20205 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20206 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
20207 {AliasPatternCond::K_Ignore, 0},
20208 {AliasPatternCond::K_Reg, AArch64::XZR},
20209 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20210 // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 883
20211 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20212 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
20213 {AliasPatternCond::K_Ignore, 0},
20214 {AliasPatternCond::K_Reg, AArch64::XZR},
20215 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20216 // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 888
20217 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20218 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20219 {AliasPatternCond::K_Ignore, 0},
20220 {AliasPatternCond::K_Reg, AArch64::XZR},
20221 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20222 // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 893
20223 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20224 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
20225 {AliasPatternCond::K_Ignore, 0},
20226 {AliasPatternCond::K_Reg, AArch64::XZR},
20227 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20228 // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 898
20229 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20230 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20231 {AliasPatternCond::K_Ignore, 0},
20232 {AliasPatternCond::K_Reg, AArch64::XZR},
20233 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20234 // (LD1RB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 903
20235 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20236 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20237 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20238 {AliasPatternCond::K_Imm, uint32_t(0)},
20239 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20240 // (LD1RB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 908
20241 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20242 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20243 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20244 {AliasPatternCond::K_Imm, uint32_t(0)},
20245 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20246 // (LD1RB_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 913
20247 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20248 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20249 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20250 {AliasPatternCond::K_Imm, uint32_t(0)},
20251 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20252 // (LD1RB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 918
20253 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20254 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20255 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20256 {AliasPatternCond::K_Imm, uint32_t(0)},
20257 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20258 // (LD1RD_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 923
20259 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20260 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20261 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20262 {AliasPatternCond::K_Imm, uint32_t(0)},
20263 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20264 // (LD1RH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 928
20265 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20266 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20267 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20268 {AliasPatternCond::K_Imm, uint32_t(0)},
20269 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20270 // (LD1RH_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 933
20271 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20272 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20273 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20274 {AliasPatternCond::K_Imm, uint32_t(0)},
20275 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20276 // (LD1RH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 938
20277 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20278 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20279 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20280 {AliasPatternCond::K_Imm, uint32_t(0)},
20281 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20282 // (LD1RO_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 943
20283 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20284 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20285 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20286 {AliasPatternCond::K_Imm, uint32_t(0)},
20287 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20288 {AliasPatternCond::K_Feature, AArch64::FeatureMatMulFP64},
20289 // (LD1RO_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 949
20290 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20291 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20292 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20293 {AliasPatternCond::K_Imm, uint32_t(0)},
20294 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20295 {AliasPatternCond::K_Feature, AArch64::FeatureMatMulFP64},
20296 // (LD1RO_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 955
20297 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20298 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20299 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20300 {AliasPatternCond::K_Imm, uint32_t(0)},
20301 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20302 {AliasPatternCond::K_Feature, AArch64::FeatureMatMulFP64},
20303 // (LD1RO_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 961
20304 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20305 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20306 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20307 {AliasPatternCond::K_Imm, uint32_t(0)},
20308 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20309 {AliasPatternCond::K_Feature, AArch64::FeatureMatMulFP64},
20310 // (LD1RQ_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 967
20311 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20312 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20313 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20314 {AliasPatternCond::K_Imm, uint32_t(0)},
20315 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20316 // (LD1RQ_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 972
20317 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20318 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20319 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20320 {AliasPatternCond::K_Imm, uint32_t(0)},
20321 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20322 // (LD1RQ_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 977
20323 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20324 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20325 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20326 {AliasPatternCond::K_Imm, uint32_t(0)},
20327 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20328 // (LD1RQ_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 982
20329 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20330 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20331 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20332 {AliasPatternCond::K_Imm, uint32_t(0)},
20333 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20334 // (LD1RSB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 987
20335 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20336 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20337 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20338 {AliasPatternCond::K_Imm, uint32_t(0)},
20339 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20340 // (LD1RSB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 992
20341 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20342 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20343 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20344 {AliasPatternCond::K_Imm, uint32_t(0)},
20345 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20346 // (LD1RSB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 997
20347 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20348 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20349 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20350 {AliasPatternCond::K_Imm, uint32_t(0)},
20351 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20352 // (LD1RSH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1002
20353 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20354 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20355 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20356 {AliasPatternCond::K_Imm, uint32_t(0)},
20357 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20358 // (LD1RSH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1007
20359 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20360 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20361 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20362 {AliasPatternCond::K_Imm, uint32_t(0)},
20363 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20364 // (LD1RSW_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1012
20365 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20366 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20367 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20368 {AliasPatternCond::K_Imm, uint32_t(0)},
20369 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20370 // (LD1RW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1017
20371 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20372 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20373 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20374 {AliasPatternCond::K_Imm, uint32_t(0)},
20375 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20376 // (LD1RW_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1022
20377 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20378 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20379 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20380 {AliasPatternCond::K_Imm, uint32_t(0)},
20381 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20382 // (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1027
20383 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20384 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20385 {AliasPatternCond::K_Ignore, 0},
20386 {AliasPatternCond::K_Reg, AArch64::XZR},
20387 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20388 // (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1032
20389 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20390 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
20391 {AliasPatternCond::K_Ignore, 0},
20392 {AliasPatternCond::K_Reg, AArch64::XZR},
20393 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20394 // (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1037
20395 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20396 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20397 {AliasPatternCond::K_Ignore, 0},
20398 {AliasPatternCond::K_Reg, AArch64::XZR},
20399 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20400 // (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1042
20401 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20402 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
20403 {AliasPatternCond::K_Ignore, 0},
20404 {AliasPatternCond::K_Reg, AArch64::XZR},
20405 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20406 // (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1047
20407 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20408 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
20409 {AliasPatternCond::K_Ignore, 0},
20410 {AliasPatternCond::K_Reg, AArch64::XZR},
20411 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20412 // (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1052
20413 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20414 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20415 {AliasPatternCond::K_Ignore, 0},
20416 {AliasPatternCond::K_Reg, AArch64::XZR},
20417 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20418 // (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1057
20419 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20420 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
20421 {AliasPatternCond::K_Ignore, 0},
20422 {AliasPatternCond::K_Reg, AArch64::XZR},
20423 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20424 // (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1062
20425 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20426 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20427 {AliasPatternCond::K_Ignore, 0},
20428 {AliasPatternCond::K_Reg, AArch64::XZR},
20429 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20430 // (LD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1067
20431 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20432 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20433 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20434 {AliasPatternCond::K_Imm, uint32_t(0)},
20435 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20436 // (LD1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1072
20437 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20438 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20439 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20440 {AliasPatternCond::K_Imm, uint32_t(0)},
20441 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20442 // (LD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1077
20443 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20444 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20445 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20446 {AliasPatternCond::K_Imm, uint32_t(0)},
20447 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20448 // (LD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1082
20449 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20450 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20451 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20452 {AliasPatternCond::K_Imm, uint32_t(0)},
20453 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20454 // (LD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1087
20455 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20456 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20457 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20458 {AliasPatternCond::K_Imm, uint32_t(0)},
20459 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20460 // (LD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1092
20461 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20462 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20463 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20464 {AliasPatternCond::K_Imm, uint32_t(0)},
20465 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20466 // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1097
20467 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20468 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20469 {AliasPatternCond::K_Ignore, 0},
20470 {AliasPatternCond::K_Reg, AArch64::XZR},
20471 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20472 // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 1102
20473 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20474 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20475 {AliasPatternCond::K_Ignore, 0},
20476 {AliasPatternCond::K_Reg, AArch64::XZR},
20477 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20478 // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1107
20479 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20480 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20481 {AliasPatternCond::K_Ignore, 0},
20482 {AliasPatternCond::K_Reg, AArch64::XZR},
20483 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20484 // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1112
20485 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20486 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20487 {AliasPatternCond::K_Ignore, 0},
20488 {AliasPatternCond::K_Reg, AArch64::XZR},
20489 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20490 // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1117
20491 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20492 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20493 {AliasPatternCond::K_Ignore, 0},
20494 {AliasPatternCond::K_Reg, AArch64::XZR},
20495 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20496 // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1122
20497 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20498 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20499 {AliasPatternCond::K_Ignore, 0},
20500 {AliasPatternCond::K_Reg, AArch64::XZR},
20501 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20502 // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1127
20503 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20504 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20505 {AliasPatternCond::K_Ignore, 0},
20506 {AliasPatternCond::K_Reg, AArch64::XZR},
20507 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20508 // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1132
20509 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20510 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20511 {AliasPatternCond::K_Ignore, 0},
20512 {AliasPatternCond::K_Reg, AArch64::XZR},
20513 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20514 // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1137
20515 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20516 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20517 {AliasPatternCond::K_Ignore, 0},
20518 {AliasPatternCond::K_Reg, AArch64::XZR},
20519 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20520 // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 1142
20521 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20522 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
20523 {AliasPatternCond::K_Ignore, 0},
20524 {AliasPatternCond::K_Reg, AArch64::XZR},
20525 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20526 // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 1147
20527 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20528 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20529 {AliasPatternCond::K_Ignore, 0},
20530 {AliasPatternCond::K_Reg, AArch64::XZR},
20531 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20532 // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 1152
20533 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20534 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
20535 {AliasPatternCond::K_Ignore, 0},
20536 {AliasPatternCond::K_Reg, AArch64::XZR},
20537 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20538 // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 1157
20539 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20540 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
20541 {AliasPatternCond::K_Ignore, 0},
20542 {AliasPatternCond::K_Reg, AArch64::XZR},
20543 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20544 // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 1162
20545 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20546 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20547 {AliasPatternCond::K_Ignore, 0},
20548 {AliasPatternCond::K_Reg, AArch64::XZR},
20549 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20550 // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 1167
20551 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20552 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
20553 {AliasPatternCond::K_Ignore, 0},
20554 {AliasPatternCond::K_Reg, AArch64::XZR},
20555 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20556 // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 1172
20557 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20558 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20559 {AliasPatternCond::K_Ignore, 0},
20560 {AliasPatternCond::K_Reg, AArch64::XZR},
20561 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20562 // (LD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1177
20563 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20564 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20565 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20566 {AliasPatternCond::K_Imm, uint32_t(0)},
20567 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20568 // (LD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1182
20569 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
20570 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20571 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20572 {AliasPatternCond::K_Imm, uint32_t(0)},
20573 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20574 // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 1187
20575 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20576 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20577 {AliasPatternCond::K_Ignore, 0},
20578 {AliasPatternCond::K_Ignore, 0},
20579 {AliasPatternCond::K_Ignore, 0},
20580 {AliasPatternCond::K_Reg, AArch64::XZR},
20581 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20582 // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 1194
20583 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20584 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20585 {AliasPatternCond::K_Ignore, 0},
20586 {AliasPatternCond::K_Ignore, 0},
20587 {AliasPatternCond::K_Ignore, 0},
20588 {AliasPatternCond::K_Reg, AArch64::XZR},
20589 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20590 // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 1201
20591 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20592 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20593 {AliasPatternCond::K_Ignore, 0},
20594 {AliasPatternCond::K_Ignore, 0},
20595 {AliasPatternCond::K_Ignore, 0},
20596 {AliasPatternCond::K_Reg, AArch64::XZR},
20597 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20598 // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 1208
20599 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20600 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
20601 {AliasPatternCond::K_Ignore, 0},
20602 {AliasPatternCond::K_Ignore, 0},
20603 {AliasPatternCond::K_Ignore, 0},
20604 {AliasPatternCond::K_Reg, AArch64::XZR},
20605 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20606 // (LD2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1215
20607 {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID},
20608 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20609 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20610 {AliasPatternCond::K_Imm, uint32_t(0)},
20611 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20612 // (LD2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1220
20613 {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID},
20614 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20615 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20616 {AliasPatternCond::K_Imm, uint32_t(0)},
20617 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20618 // (LD2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1225
20619 {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID},
20620 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20621 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20622 {AliasPatternCond::K_Imm, uint32_t(0)},
20623 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20624 // (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1230
20625 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20626 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20627 {AliasPatternCond::K_Ignore, 0},
20628 {AliasPatternCond::K_Reg, AArch64::XZR},
20629 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20630 // (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 1235
20631 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20632 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
20633 {AliasPatternCond::K_Ignore, 0},
20634 {AliasPatternCond::K_Reg, AArch64::XZR},
20635 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20636 // (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 1240
20637 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20638 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20639 {AliasPatternCond::K_Ignore, 0},
20640 {AliasPatternCond::K_Reg, AArch64::XZR},
20641 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20642 // (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 1245
20643 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20644 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
20645 {AliasPatternCond::K_Ignore, 0},
20646 {AliasPatternCond::K_Reg, AArch64::XZR},
20647 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20648 // (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 1250
20649 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20650 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
20651 {AliasPatternCond::K_Ignore, 0},
20652 {AliasPatternCond::K_Reg, AArch64::XZR},
20653 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20654 // (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 1255
20655 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20656 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20657 {AliasPatternCond::K_Ignore, 0},
20658 {AliasPatternCond::K_Reg, AArch64::XZR},
20659 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20660 // (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 1260
20661 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20662 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
20663 {AliasPatternCond::K_Ignore, 0},
20664 {AliasPatternCond::K_Reg, AArch64::XZR},
20665 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20666 // (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 1265
20667 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20668 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20669 {AliasPatternCond::K_Ignore, 0},
20670 {AliasPatternCond::K_Reg, AArch64::XZR},
20671 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20672 // (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1270
20673 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20674 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20675 {AliasPatternCond::K_Ignore, 0},
20676 {AliasPatternCond::K_Reg, AArch64::XZR},
20677 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20678 // (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 1275
20679 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20680 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20681 {AliasPatternCond::K_Ignore, 0},
20682 {AliasPatternCond::K_Reg, AArch64::XZR},
20683 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20684 // (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 1280
20685 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20686 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
20687 {AliasPatternCond::K_Ignore, 0},
20688 {AliasPatternCond::K_Reg, AArch64::XZR},
20689 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20690 // (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 1285
20691 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20692 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
20693 {AliasPatternCond::K_Ignore, 0},
20694 {AliasPatternCond::K_Reg, AArch64::XZR},
20695 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20696 // (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 1290
20697 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20698 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20699 {AliasPatternCond::K_Ignore, 0},
20700 {AliasPatternCond::K_Reg, AArch64::XZR},
20701 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20702 // (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 1295
20703 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20704 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
20705 {AliasPatternCond::K_Ignore, 0},
20706 {AliasPatternCond::K_Reg, AArch64::XZR},
20707 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20708 // (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 1300
20709 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20710 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20711 {AliasPatternCond::K_Ignore, 0},
20712 {AliasPatternCond::K_Reg, AArch64::XZR},
20713 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20714 // (LD2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1305
20715 {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID},
20716 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20717 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20718 {AliasPatternCond::K_Imm, uint32_t(0)},
20719 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20720 // (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 1310
20721 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20722 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20723 {AliasPatternCond::K_Ignore, 0},
20724 {AliasPatternCond::K_Ignore, 0},
20725 {AliasPatternCond::K_Ignore, 0},
20726 {AliasPatternCond::K_Reg, AArch64::XZR},
20727 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20728 // (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 1317
20729 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20730 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20731 {AliasPatternCond::K_Ignore, 0},
20732 {AliasPatternCond::K_Ignore, 0},
20733 {AliasPatternCond::K_Ignore, 0},
20734 {AliasPatternCond::K_Reg, AArch64::XZR},
20735 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20736 // (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 1324
20737 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20738 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20739 {AliasPatternCond::K_Ignore, 0},
20740 {AliasPatternCond::K_Ignore, 0},
20741 {AliasPatternCond::K_Ignore, 0},
20742 {AliasPatternCond::K_Reg, AArch64::XZR},
20743 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20744 // (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 1331
20745 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20746 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
20747 {AliasPatternCond::K_Ignore, 0},
20748 {AliasPatternCond::K_Ignore, 0},
20749 {AliasPatternCond::K_Ignore, 0},
20750 {AliasPatternCond::K_Reg, AArch64::XZR},
20751 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20752 // (LD3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1338
20753 {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID},
20754 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20755 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20756 {AliasPatternCond::K_Imm, uint32_t(0)},
20757 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20758 // (LD3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1343
20759 {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID},
20760 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20761 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20762 {AliasPatternCond::K_Imm, uint32_t(0)},
20763 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20764 // (LD3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1348
20765 {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID},
20766 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20767 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20768 {AliasPatternCond::K_Imm, uint32_t(0)},
20769 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20770 // (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1353
20771 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20772 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20773 {AliasPatternCond::K_Ignore, 0},
20774 {AliasPatternCond::K_Reg, AArch64::XZR},
20775 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20776 // (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 1358
20777 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20778 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20779 {AliasPatternCond::K_Ignore, 0},
20780 {AliasPatternCond::K_Reg, AArch64::XZR},
20781 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20782 // (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1363
20783 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20784 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20785 {AliasPatternCond::K_Ignore, 0},
20786 {AliasPatternCond::K_Reg, AArch64::XZR},
20787 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20788 // (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1368
20789 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20790 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20791 {AliasPatternCond::K_Ignore, 0},
20792 {AliasPatternCond::K_Reg, AArch64::XZR},
20793 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20794 // (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1373
20795 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20796 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20797 {AliasPatternCond::K_Ignore, 0},
20798 {AliasPatternCond::K_Reg, AArch64::XZR},
20799 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20800 // (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1378
20801 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20802 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20803 {AliasPatternCond::K_Ignore, 0},
20804 {AliasPatternCond::K_Reg, AArch64::XZR},
20805 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20806 // (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1383
20807 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20808 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20809 {AliasPatternCond::K_Ignore, 0},
20810 {AliasPatternCond::K_Reg, AArch64::XZR},
20811 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20812 // (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1388
20813 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20814 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20815 {AliasPatternCond::K_Ignore, 0},
20816 {AliasPatternCond::K_Reg, AArch64::XZR},
20817 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20818 // (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1393
20819 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20820 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20821 {AliasPatternCond::K_Ignore, 0},
20822 {AliasPatternCond::K_Reg, AArch64::XZR},
20823 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20824 // (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1398
20825 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20826 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20827 {AliasPatternCond::K_Ignore, 0},
20828 {AliasPatternCond::K_Reg, AArch64::XZR},
20829 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20830 // (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1403
20831 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20832 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20833 {AliasPatternCond::K_Ignore, 0},
20834 {AliasPatternCond::K_Reg, AArch64::XZR},
20835 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20836 // (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1408
20837 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20838 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20839 {AliasPatternCond::K_Ignore, 0},
20840 {AliasPatternCond::K_Reg, AArch64::XZR},
20841 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20842 // (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1413
20843 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20844 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20845 {AliasPatternCond::K_Ignore, 0},
20846 {AliasPatternCond::K_Reg, AArch64::XZR},
20847 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20848 // (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1418
20849 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20850 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
20851 {AliasPatternCond::K_Ignore, 0},
20852 {AliasPatternCond::K_Reg, AArch64::XZR},
20853 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20854 // (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1423
20855 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20856 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20857 {AliasPatternCond::K_Ignore, 0},
20858 {AliasPatternCond::K_Reg, AArch64::XZR},
20859 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20860 // (LD3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1428
20861 {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID},
20862 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20863 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20864 {AliasPatternCond::K_Imm, uint32_t(0)},
20865 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20866 // (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 1433
20867 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20868 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20869 {AliasPatternCond::K_Ignore, 0},
20870 {AliasPatternCond::K_Ignore, 0},
20871 {AliasPatternCond::K_Ignore, 0},
20872 {AliasPatternCond::K_Reg, AArch64::XZR},
20873 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20874 // (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 1440
20875 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20876 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20877 {AliasPatternCond::K_Ignore, 0},
20878 {AliasPatternCond::K_Ignore, 0},
20879 {AliasPatternCond::K_Ignore, 0},
20880 {AliasPatternCond::K_Reg, AArch64::XZR},
20881 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20882 // (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 1447
20883 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20884 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20885 {AliasPatternCond::K_Ignore, 0},
20886 {AliasPatternCond::K_Ignore, 0},
20887 {AliasPatternCond::K_Ignore, 0},
20888 {AliasPatternCond::K_Reg, AArch64::XZR},
20889 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20890 // (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 1454
20891 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20892 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
20893 {AliasPatternCond::K_Ignore, 0},
20894 {AliasPatternCond::K_Ignore, 0},
20895 {AliasPatternCond::K_Ignore, 0},
20896 {AliasPatternCond::K_Reg, AArch64::XZR},
20897 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20898 // (LD4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1461
20899 {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID},
20900 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20901 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20902 {AliasPatternCond::K_Imm, uint32_t(0)},
20903 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20904 // (LD4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1466
20905 {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID},
20906 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20907 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20908 {AliasPatternCond::K_Imm, uint32_t(0)},
20909 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20910 // (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1471
20911 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20912 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20913 {AliasPatternCond::K_Ignore, 0},
20914 {AliasPatternCond::K_Reg, AArch64::XZR},
20915 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20916 // (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1476
20917 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20918 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20919 {AliasPatternCond::K_Ignore, 0},
20920 {AliasPatternCond::K_Reg, AArch64::XZR},
20921 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20922 // (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1481
20923 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20924 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20925 {AliasPatternCond::K_Ignore, 0},
20926 {AliasPatternCond::K_Reg, AArch64::XZR},
20927 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20928 // (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1486
20929 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20930 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20931 {AliasPatternCond::K_Ignore, 0},
20932 {AliasPatternCond::K_Reg, AArch64::XZR},
20933 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20934 // (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 1491
20935 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20936 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20937 {AliasPatternCond::K_Ignore, 0},
20938 {AliasPatternCond::K_Reg, AArch64::XZR},
20939 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20940 // (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 1496
20941 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20942 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20943 {AliasPatternCond::K_Ignore, 0},
20944 {AliasPatternCond::K_Reg, AArch64::XZR},
20945 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20946 // (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 1501
20947 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20948 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20949 {AliasPatternCond::K_Ignore, 0},
20950 {AliasPatternCond::K_Reg, AArch64::XZR},
20951 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20952 // (LD4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1506
20953 {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID},
20954 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
20955 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20956 {AliasPatternCond::K_Imm, uint32_t(0)},
20957 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
20958 // (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1511
20959 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20960 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20961 {AliasPatternCond::K_Ignore, 0},
20962 {AliasPatternCond::K_Reg, AArch64::XZR},
20963 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20964 // (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 1516
20965 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20966 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20967 {AliasPatternCond::K_Ignore, 0},
20968 {AliasPatternCond::K_Reg, AArch64::XZR},
20969 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20970 // (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1521
20971 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20972 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20973 {AliasPatternCond::K_Ignore, 0},
20974 {AliasPatternCond::K_Reg, AArch64::XZR},
20975 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20976 // (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1526
20977 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20978 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20979 {AliasPatternCond::K_Ignore, 0},
20980 {AliasPatternCond::K_Reg, AArch64::XZR},
20981 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20982 // (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1531
20983 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20984 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20985 {AliasPatternCond::K_Ignore, 0},
20986 {AliasPatternCond::K_Reg, AArch64::XZR},
20987 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20988 // (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 1536
20989 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20990 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
20991 {AliasPatternCond::K_Ignore, 0},
20992 {AliasPatternCond::K_Reg, AArch64::XZR},
20993 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
20994 // (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 1541
20995 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
20996 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
20997 {AliasPatternCond::K_Ignore, 0},
20998 {AliasPatternCond::K_Reg, AArch64::XZR},
20999 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
21000 // (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 1546
21001 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21002 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
21003 {AliasPatternCond::K_Ignore, 0},
21004 {AliasPatternCond::K_Reg, AArch64::XZR},
21005 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
21006 // (LD4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1551
21007 {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID},
21008 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21009 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21010 {AliasPatternCond::K_Imm, uint32_t(0)},
21011 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21012 // (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 1556
21013 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21014 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
21015 {AliasPatternCond::K_Ignore, 0},
21016 {AliasPatternCond::K_Ignore, 0},
21017 {AliasPatternCond::K_Ignore, 0},
21018 {AliasPatternCond::K_Reg, AArch64::XZR},
21019 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
21020 // (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 1563
21021 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21022 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
21023 {AliasPatternCond::K_Ignore, 0},
21024 {AliasPatternCond::K_Ignore, 0},
21025 {AliasPatternCond::K_Ignore, 0},
21026 {AliasPatternCond::K_Reg, AArch64::XZR},
21027 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
21028 // (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 1570
21029 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21030 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
21031 {AliasPatternCond::K_Ignore, 0},
21032 {AliasPatternCond::K_Ignore, 0},
21033 {AliasPatternCond::K_Ignore, 0},
21034 {AliasPatternCond::K_Reg, AArch64::XZR},
21035 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
21036 // (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 1577
21037 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21038 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
21039 {AliasPatternCond::K_Ignore, 0},
21040 {AliasPatternCond::K_Ignore, 0},
21041 {AliasPatternCond::K_Ignore, 0},
21042 {AliasPatternCond::K_Reg, AArch64::XZR},
21043 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
21044 // (LDADDB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1584
21045 {AliasPatternCond::K_Reg, AArch64::WZR},
21046 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21047 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21048 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21049 // (LDADDH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1588
21050 {AliasPatternCond::K_Reg, AArch64::WZR},
21051 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21052 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21053 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21054 // (LDADDLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1592
21055 {AliasPatternCond::K_Reg, AArch64::WZR},
21056 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21057 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21058 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21059 // (LDADDLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1596
21060 {AliasPatternCond::K_Reg, AArch64::WZR},
21061 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21062 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21063 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21064 // (LDADDLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1600
21065 {AliasPatternCond::K_Reg, AArch64::WZR},
21066 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21067 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21068 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21069 // (LDADDLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1604
21070 {AliasPatternCond::K_Reg, AArch64::XZR},
21071 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21072 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21073 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21074 // (LDADDW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1608
21075 {AliasPatternCond::K_Reg, AArch64::WZR},
21076 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21077 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21078 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21079 // (LDADDX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1612
21080 {AliasPatternCond::K_Reg, AArch64::XZR},
21081 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21082 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21083 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21084 // (LDAPURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 1616
21085 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21086 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21087 {AliasPatternCond::K_Imm, uint32_t(0)},
21088 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
21089 // (LDAPURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 1620
21090 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21091 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21092 {AliasPatternCond::K_Imm, uint32_t(0)},
21093 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
21094 // (LDAPURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 1624
21095 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21096 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21097 {AliasPatternCond::K_Imm, uint32_t(0)},
21098 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
21099 // (LDAPURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 1628
21100 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21101 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21102 {AliasPatternCond::K_Imm, uint32_t(0)},
21103 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
21104 // (LDAPURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 1632
21105 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21106 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21107 {AliasPatternCond::K_Imm, uint32_t(0)},
21108 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
21109 // (LDAPURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 1636
21110 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21111 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21112 {AliasPatternCond::K_Imm, uint32_t(0)},
21113 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
21114 // (LDAPURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 1640
21115 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21116 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21117 {AliasPatternCond::K_Imm, uint32_t(0)},
21118 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
21119 // (LDAPURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 1644
21120 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21121 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21122 {AliasPatternCond::K_Imm, uint32_t(0)},
21123 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
21124 // (LDAPURi GPR32:$Rt, GPR64sp:$Rn, 0) - 1648
21125 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21126 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21127 {AliasPatternCond::K_Imm, uint32_t(0)},
21128 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
21129 // (LDCLRB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1652
21130 {AliasPatternCond::K_Reg, AArch64::WZR},
21131 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21132 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21133 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21134 // (LDCLRH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1656
21135 {AliasPatternCond::K_Reg, AArch64::WZR},
21136 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21137 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21138 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21139 // (LDCLRLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1660
21140 {AliasPatternCond::K_Reg, AArch64::WZR},
21141 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21142 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21143 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21144 // (LDCLRLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1664
21145 {AliasPatternCond::K_Reg, AArch64::WZR},
21146 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21147 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21148 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21149 // (LDCLRLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1668
21150 {AliasPatternCond::K_Reg, AArch64::WZR},
21151 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21152 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21153 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21154 // (LDCLRLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1672
21155 {AliasPatternCond::K_Reg, AArch64::XZR},
21156 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21157 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21158 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21159 // (LDCLRW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1676
21160 {AliasPatternCond::K_Reg, AArch64::WZR},
21161 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21162 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21163 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21164 // (LDCLRX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1680
21165 {AliasPatternCond::K_Reg, AArch64::XZR},
21166 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21167 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21168 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21169 // (LDEORB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1684
21170 {AliasPatternCond::K_Reg, AArch64::WZR},
21171 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21172 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21173 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21174 // (LDEORH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1688
21175 {AliasPatternCond::K_Reg, AArch64::WZR},
21176 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21177 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21178 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21179 // (LDEORLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1692
21180 {AliasPatternCond::K_Reg, AArch64::WZR},
21181 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21182 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21183 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21184 // (LDEORLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1696
21185 {AliasPatternCond::K_Reg, AArch64::WZR},
21186 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21187 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21188 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21189 // (LDEORLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1700
21190 {AliasPatternCond::K_Reg, AArch64::WZR},
21191 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21192 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21193 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21194 // (LDEORLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1704
21195 {AliasPatternCond::K_Reg, AArch64::XZR},
21196 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21197 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21198 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21199 // (LDEORW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1708
21200 {AliasPatternCond::K_Reg, AArch64::WZR},
21201 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21202 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21203 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21204 // (LDEORX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1712
21205 {AliasPatternCond::K_Reg, AArch64::XZR},
21206 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21207 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21208 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21209 // (LDFF1B_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1716
21210 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21211 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21212 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21213 {AliasPatternCond::K_Reg, AArch64::XZR},
21214 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21215 // (LDFF1B_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1721
21216 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21217 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21218 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21219 {AliasPatternCond::K_Reg, AArch64::XZR},
21220 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21221 // (LDFF1B_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1726
21222 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21223 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21224 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21225 {AliasPatternCond::K_Reg, AArch64::XZR},
21226 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21227 // (LDFF1B_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1731
21228 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21229 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21230 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21231 {AliasPatternCond::K_Reg, AArch64::XZR},
21232 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21233 // (LDFF1D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1736
21234 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21235 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21236 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21237 {AliasPatternCond::K_Reg, AArch64::XZR},
21238 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21239 // (LDFF1H_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1741
21240 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21241 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21242 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21243 {AliasPatternCond::K_Reg, AArch64::XZR},
21244 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21245 // (LDFF1H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1746
21246 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21247 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21248 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21249 {AliasPatternCond::K_Reg, AArch64::XZR},
21250 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21251 // (LDFF1H_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1751
21252 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21253 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21254 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21255 {AliasPatternCond::K_Reg, AArch64::XZR},
21256 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21257 // (LDFF1SB_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1756
21258 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21259 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21260 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21261 {AliasPatternCond::K_Reg, AArch64::XZR},
21262 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21263 // (LDFF1SB_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1761
21264 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21265 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21266 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21267 {AliasPatternCond::K_Reg, AArch64::XZR},
21268 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21269 // (LDFF1SB_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1766
21270 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21271 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21272 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21273 {AliasPatternCond::K_Reg, AArch64::XZR},
21274 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21275 // (LDFF1SH_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1771
21276 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21277 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21278 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21279 {AliasPatternCond::K_Reg, AArch64::XZR},
21280 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21281 // (LDFF1SH_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1776
21282 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21283 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21284 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21285 {AliasPatternCond::K_Reg, AArch64::XZR},
21286 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21287 // (LDFF1SW_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1781
21288 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21289 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21290 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21291 {AliasPatternCond::K_Reg, AArch64::XZR},
21292 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21293 // (LDFF1W_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1786
21294 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21295 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21296 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21297 {AliasPatternCond::K_Reg, AArch64::XZR},
21298 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21299 // (LDFF1W_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1791
21300 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21301 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21302 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21303 {AliasPatternCond::K_Reg, AArch64::XZR},
21304 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21305 // (LDG GPR64:$Rt, GPR64sp:$Rn, 0) - 1796
21306 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21307 {AliasPatternCond::K_Ignore, 0},
21308 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21309 {AliasPatternCond::K_Imm, uint32_t(0)},
21310 {AliasPatternCond::K_Feature, AArch64::FeatureMTE},
21311 // (LDNF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1801
21312 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21313 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21314 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21315 {AliasPatternCond::K_Imm, uint32_t(0)},
21316 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21317 // (LDNF1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1806
21318 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21319 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21320 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21321 {AliasPatternCond::K_Imm, uint32_t(0)},
21322 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21323 // (LDNF1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1811
21324 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21325 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21326 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21327 {AliasPatternCond::K_Imm, uint32_t(0)},
21328 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21329 // (LDNF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1816
21330 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21331 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21332 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21333 {AliasPatternCond::K_Imm, uint32_t(0)},
21334 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21335 // (LDNF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1821
21336 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21337 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21338 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21339 {AliasPatternCond::K_Imm, uint32_t(0)},
21340 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21341 // (LDNF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1826
21342 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21343 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21344 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21345 {AliasPatternCond::K_Imm, uint32_t(0)},
21346 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21347 // (LDNF1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1831
21348 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21349 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21350 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21351 {AliasPatternCond::K_Imm, uint32_t(0)},
21352 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21353 // (LDNF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1836
21354 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21355 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21356 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21357 {AliasPatternCond::K_Imm, uint32_t(0)},
21358 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21359 // (LDNF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1841
21360 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21361 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21362 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21363 {AliasPatternCond::K_Imm, uint32_t(0)},
21364 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21365 // (LDNF1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1846
21366 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21367 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21368 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21369 {AliasPatternCond::K_Imm, uint32_t(0)},
21370 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21371 // (LDNF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1851
21372 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21373 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21374 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21375 {AliasPatternCond::K_Imm, uint32_t(0)},
21376 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21377 // (LDNF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1856
21378 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21379 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21380 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21381 {AliasPatternCond::K_Imm, uint32_t(0)},
21382 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21383 // (LDNF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1861
21384 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21385 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21386 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21387 {AliasPatternCond::K_Imm, uint32_t(0)},
21388 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21389 // (LDNF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1866
21390 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21391 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21392 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21393 {AliasPatternCond::K_Imm, uint32_t(0)},
21394 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21395 // (LDNF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1871
21396 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21397 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21398 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21399 {AliasPatternCond::K_Imm, uint32_t(0)},
21400 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21401 // (LDNF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1876
21402 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21403 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21404 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21405 {AliasPatternCond::K_Imm, uint32_t(0)},
21406 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21407 // (LDNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 1881
21408 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
21409 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
21410 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21411 {AliasPatternCond::K_Imm, uint32_t(0)},
21412 // (LDNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 1885
21413 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
21414 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
21415 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21416 {AliasPatternCond::K_Imm, uint32_t(0)},
21417 // (LDNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 1889
21418 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
21419 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
21420 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21421 {AliasPatternCond::K_Imm, uint32_t(0)},
21422 // (LDNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 1893
21423 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21424 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21425 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21426 {AliasPatternCond::K_Imm, uint32_t(0)},
21427 // (LDNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 1897
21428 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21429 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21430 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21431 {AliasPatternCond::K_Imm, uint32_t(0)},
21432 // (LDNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1901
21433 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21434 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21435 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21436 {AliasPatternCond::K_Imm, uint32_t(0)},
21437 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21438 // (LDNT1B_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1906
21439 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21440 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21441 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21442 {AliasPatternCond::K_Reg, AArch64::XZR},
21443 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
21444 // (LDNT1B_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 1911
21445 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21446 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21447 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21448 {AliasPatternCond::K_Reg, AArch64::XZR},
21449 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
21450 // (LDNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1916
21451 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21452 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21453 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21454 {AliasPatternCond::K_Imm, uint32_t(0)},
21455 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21456 // (LDNT1D_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1921
21457 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21458 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21459 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21460 {AliasPatternCond::K_Reg, AArch64::XZR},
21461 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
21462 // (LDNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1926
21463 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21464 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21465 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21466 {AliasPatternCond::K_Imm, uint32_t(0)},
21467 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21468 // (LDNT1H_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1931
21469 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21470 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21471 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21472 {AliasPatternCond::K_Reg, AArch64::XZR},
21473 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
21474 // (LDNT1H_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 1936
21475 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21476 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21477 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21478 {AliasPatternCond::K_Reg, AArch64::XZR},
21479 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
21480 // (LDNT1SB_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1941
21481 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21482 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21483 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21484 {AliasPatternCond::K_Reg, AArch64::XZR},
21485 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
21486 // (LDNT1SB_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 1946
21487 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21488 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21489 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21490 {AliasPatternCond::K_Reg, AArch64::XZR},
21491 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
21492 // (LDNT1SH_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1951
21493 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21494 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21495 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21496 {AliasPatternCond::K_Reg, AArch64::XZR},
21497 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
21498 // (LDNT1SH_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 1956
21499 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21500 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21501 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21502 {AliasPatternCond::K_Reg, AArch64::XZR},
21503 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
21504 // (LDNT1SW_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1961
21505 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21506 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21507 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21508 {AliasPatternCond::K_Reg, AArch64::XZR},
21509 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
21510 // (LDNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1966
21511 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21512 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21513 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21514 {AliasPatternCond::K_Imm, uint32_t(0)},
21515 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21516 // (LDNT1W_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1971
21517 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21518 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21519 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21520 {AliasPatternCond::K_Reg, AArch64::XZR},
21521 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
21522 // (LDNT1W_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 1976
21523 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21524 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
21525 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21526 {AliasPatternCond::K_Reg, AArch64::XZR},
21527 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
21528 // (LDPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 1981
21529 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
21530 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
21531 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21532 {AliasPatternCond::K_Imm, uint32_t(0)},
21533 // (LDPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 1985
21534 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
21535 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
21536 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21537 {AliasPatternCond::K_Imm, uint32_t(0)},
21538 // (LDPSWi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 1989
21539 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21540 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21541 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21542 {AliasPatternCond::K_Imm, uint32_t(0)},
21543 // (LDPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 1993
21544 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
21545 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
21546 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21547 {AliasPatternCond::K_Imm, uint32_t(0)},
21548 // (LDPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 1997
21549 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21550 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21551 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21552 {AliasPatternCond::K_Imm, uint32_t(0)},
21553 // (LDPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 2001
21554 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21555 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21556 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21557 {AliasPatternCond::K_Imm, uint32_t(0)},
21558 // (LDRAAindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 2005
21559 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21560 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21561 {AliasPatternCond::K_Imm, uint32_t(0)},
21562 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
21563 // (LDRABindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 2009
21564 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21565 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21566 {AliasPatternCond::K_Imm, uint32_t(0)},
21567 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
21568 // (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2013
21569 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21570 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21571 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21572 {AliasPatternCond::K_Imm, uint32_t(0)},
21573 {AliasPatternCond::K_Imm, uint32_t(0)},
21574 // (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) - 2018
21575 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21576 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21577 {AliasPatternCond::K_Imm, uint32_t(0)},
21578 // (LDRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2021
21579 {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID},
21580 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21581 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21582 {AliasPatternCond::K_Imm, uint32_t(0)},
21583 {AliasPatternCond::K_Imm, uint32_t(0)},
21584 // (LDRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 2026
21585 {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID},
21586 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21587 {AliasPatternCond::K_Imm, uint32_t(0)},
21588 // (LDRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2029
21589 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
21590 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21591 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21592 {AliasPatternCond::K_Imm, uint32_t(0)},
21593 {AliasPatternCond::K_Imm, uint32_t(0)},
21594 // (LDRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 2034
21595 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
21596 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21597 {AliasPatternCond::K_Imm, uint32_t(0)},
21598 // (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2037
21599 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21600 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21601 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21602 {AliasPatternCond::K_Imm, uint32_t(0)},
21603 {AliasPatternCond::K_Imm, uint32_t(0)},
21604 // (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) - 2042
21605 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21606 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21607 {AliasPatternCond::K_Imm, uint32_t(0)},
21608 // (LDRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2045
21609 {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID},
21610 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21611 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21612 {AliasPatternCond::K_Imm, uint32_t(0)},
21613 {AliasPatternCond::K_Imm, uint32_t(0)},
21614 // (LDRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 2050
21615 {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID},
21616 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21617 {AliasPatternCond::K_Imm, uint32_t(0)},
21618 // (LDRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2053
21619 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
21620 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21621 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21622 {AliasPatternCond::K_Imm, uint32_t(0)},
21623 {AliasPatternCond::K_Imm, uint32_t(0)},
21624 // (LDRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 2058
21625 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
21626 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21627 {AliasPatternCond::K_Imm, uint32_t(0)},
21628 // (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2061
21629 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21630 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21631 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21632 {AliasPatternCond::K_Imm, uint32_t(0)},
21633 {AliasPatternCond::K_Imm, uint32_t(0)},
21634 // (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) - 2066
21635 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21636 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21637 {AliasPatternCond::K_Imm, uint32_t(0)},
21638 // (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2069
21639 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21640 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21641 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21642 {AliasPatternCond::K_Imm, uint32_t(0)},
21643 {AliasPatternCond::K_Imm, uint32_t(0)},
21644 // (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) - 2074
21645 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21646 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21647 {AliasPatternCond::K_Imm, uint32_t(0)},
21648 // (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2077
21649 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21650 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21651 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21652 {AliasPatternCond::K_Imm, uint32_t(0)},
21653 {AliasPatternCond::K_Imm, uint32_t(0)},
21654 // (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) - 2082
21655 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21656 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21657 {AliasPatternCond::K_Imm, uint32_t(0)},
21658 // (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2085
21659 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21660 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21661 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21662 {AliasPatternCond::K_Imm, uint32_t(0)},
21663 {AliasPatternCond::K_Imm, uint32_t(0)},
21664 // (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) - 2090
21665 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21666 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21667 {AliasPatternCond::K_Imm, uint32_t(0)},
21668 // (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2093
21669 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21670 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21671 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21672 {AliasPatternCond::K_Imm, uint32_t(0)},
21673 {AliasPatternCond::K_Imm, uint32_t(0)},
21674 // (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) - 2098
21675 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21676 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21677 {AliasPatternCond::K_Imm, uint32_t(0)},
21678 // (LDRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2101
21679 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
21680 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21681 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21682 {AliasPatternCond::K_Imm, uint32_t(0)},
21683 {AliasPatternCond::K_Imm, uint32_t(0)},
21684 // (LDRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 2106
21685 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
21686 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21687 {AliasPatternCond::K_Imm, uint32_t(0)},
21688 // (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2109
21689 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21690 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21691 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21692 {AliasPatternCond::K_Imm, uint32_t(0)},
21693 {AliasPatternCond::K_Imm, uint32_t(0)},
21694 // (LDRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 2114
21695 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21696 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21697 {AliasPatternCond::K_Imm, uint32_t(0)},
21698 // (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2117
21699 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21700 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21701 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21702 {AliasPatternCond::K_Imm, uint32_t(0)},
21703 {AliasPatternCond::K_Imm, uint32_t(0)},
21704 // (LDRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 2122
21705 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21706 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21707 {AliasPatternCond::K_Imm, uint32_t(0)},
21708 // (LDR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) - 2125
21709 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
21710 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21711 {AliasPatternCond::K_Imm, uint32_t(0)},
21712 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21713 // (LDR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 2129
21714 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
21715 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21716 {AliasPatternCond::K_Imm, uint32_t(0)},
21717 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
21718 // (LDSETB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2133
21719 {AliasPatternCond::K_Reg, AArch64::WZR},
21720 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21721 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21722 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21723 // (LDSETH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2137
21724 {AliasPatternCond::K_Reg, AArch64::WZR},
21725 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21726 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21727 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21728 // (LDSETLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2141
21729 {AliasPatternCond::K_Reg, AArch64::WZR},
21730 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21731 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21732 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21733 // (LDSETLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2145
21734 {AliasPatternCond::K_Reg, AArch64::WZR},
21735 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21736 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21737 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21738 // (LDSETLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2149
21739 {AliasPatternCond::K_Reg, AArch64::WZR},
21740 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21741 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21742 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21743 // (LDSETLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2153
21744 {AliasPatternCond::K_Reg, AArch64::XZR},
21745 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21746 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21747 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21748 // (LDSETW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2157
21749 {AliasPatternCond::K_Reg, AArch64::WZR},
21750 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21751 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21752 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21753 // (LDSETX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2161
21754 {AliasPatternCond::K_Reg, AArch64::XZR},
21755 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21756 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21757 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21758 // (LDSMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2165
21759 {AliasPatternCond::K_Reg, AArch64::WZR},
21760 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21761 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21762 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21763 // (LDSMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2169
21764 {AliasPatternCond::K_Reg, AArch64::WZR},
21765 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21766 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21767 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21768 // (LDSMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2173
21769 {AliasPatternCond::K_Reg, AArch64::WZR},
21770 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21771 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21772 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21773 // (LDSMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2177
21774 {AliasPatternCond::K_Reg, AArch64::WZR},
21775 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21776 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21777 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21778 // (LDSMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2181
21779 {AliasPatternCond::K_Reg, AArch64::WZR},
21780 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21781 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21782 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21783 // (LDSMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2185
21784 {AliasPatternCond::K_Reg, AArch64::XZR},
21785 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21786 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21787 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21788 // (LDSMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2189
21789 {AliasPatternCond::K_Reg, AArch64::WZR},
21790 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21791 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21792 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21793 // (LDSMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2193
21794 {AliasPatternCond::K_Reg, AArch64::XZR},
21795 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21796 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21797 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21798 // (LDSMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2197
21799 {AliasPatternCond::K_Reg, AArch64::WZR},
21800 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21801 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21802 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21803 // (LDSMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2201
21804 {AliasPatternCond::K_Reg, AArch64::WZR},
21805 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21806 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21807 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21808 // (LDSMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2205
21809 {AliasPatternCond::K_Reg, AArch64::WZR},
21810 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21811 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21812 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21813 // (LDSMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2209
21814 {AliasPatternCond::K_Reg, AArch64::WZR},
21815 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21816 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21817 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21818 // (LDSMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2213
21819 {AliasPatternCond::K_Reg, AArch64::WZR},
21820 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21821 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21822 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21823 // (LDSMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2217
21824 {AliasPatternCond::K_Reg, AArch64::XZR},
21825 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21826 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21827 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21828 // (LDSMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2221
21829 {AliasPatternCond::K_Reg, AArch64::WZR},
21830 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21831 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21832 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21833 // (LDSMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2225
21834 {AliasPatternCond::K_Reg, AArch64::XZR},
21835 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21836 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21837 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21838 // (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2229
21839 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21840 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21841 {AliasPatternCond::K_Imm, uint32_t(0)},
21842 // (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2232
21843 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21844 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21845 {AliasPatternCond::K_Imm, uint32_t(0)},
21846 // (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2235
21847 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21848 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21849 {AliasPatternCond::K_Imm, uint32_t(0)},
21850 // (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2238
21851 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21852 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21853 {AliasPatternCond::K_Imm, uint32_t(0)},
21854 // (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2241
21855 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21856 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21857 {AliasPatternCond::K_Imm, uint32_t(0)},
21858 // (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2244
21859 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21860 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21861 {AliasPatternCond::K_Imm, uint32_t(0)},
21862 // (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2247
21863 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21864 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21865 {AliasPatternCond::K_Imm, uint32_t(0)},
21866 // (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2250
21867 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21868 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21869 {AliasPatternCond::K_Imm, uint32_t(0)},
21870 // (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2253
21871 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21872 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21873 {AliasPatternCond::K_Imm, uint32_t(0)},
21874 // (LDUMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2256
21875 {AliasPatternCond::K_Reg, AArch64::WZR},
21876 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21877 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21878 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21879 // (LDUMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2260
21880 {AliasPatternCond::K_Reg, AArch64::WZR},
21881 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21882 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21883 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21884 // (LDUMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2264
21885 {AliasPatternCond::K_Reg, AArch64::WZR},
21886 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21887 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21888 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21889 // (LDUMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2268
21890 {AliasPatternCond::K_Reg, AArch64::WZR},
21891 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21892 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21893 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21894 // (LDUMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2272
21895 {AliasPatternCond::K_Reg, AArch64::WZR},
21896 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21897 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21898 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21899 // (LDUMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2276
21900 {AliasPatternCond::K_Reg, AArch64::XZR},
21901 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21902 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21903 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21904 // (LDUMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2280
21905 {AliasPatternCond::K_Reg, AArch64::WZR},
21906 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21907 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21908 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21909 // (LDUMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2284
21910 {AliasPatternCond::K_Reg, AArch64::XZR},
21911 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21912 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21913 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21914 // (LDUMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2288
21915 {AliasPatternCond::K_Reg, AArch64::WZR},
21916 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21917 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21918 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21919 // (LDUMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2292
21920 {AliasPatternCond::K_Reg, AArch64::WZR},
21921 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21922 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21923 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21924 // (LDUMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2296
21925 {AliasPatternCond::K_Reg, AArch64::WZR},
21926 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21927 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21928 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21929 // (LDUMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2300
21930 {AliasPatternCond::K_Reg, AArch64::WZR},
21931 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21932 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21933 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21934 // (LDUMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2304
21935 {AliasPatternCond::K_Reg, AArch64::WZR},
21936 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21937 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21938 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21939 // (LDUMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2308
21940 {AliasPatternCond::K_Reg, AArch64::XZR},
21941 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21942 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21943 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21944 // (LDUMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2312
21945 {AliasPatternCond::K_Reg, AArch64::WZR},
21946 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21947 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21948 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21949 // (LDUMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2316
21950 {AliasPatternCond::K_Reg, AArch64::XZR},
21951 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21952 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21953 {AliasPatternCond::K_Feature, AArch64::FeatureLSE},
21954 // (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2320
21955 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21956 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21957 {AliasPatternCond::K_Imm, uint32_t(0)},
21958 // (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 2323
21959 {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID},
21960 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21961 {AliasPatternCond::K_Imm, uint32_t(0)},
21962 // (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 2326
21963 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
21964 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21965 {AliasPatternCond::K_Imm, uint32_t(0)},
21966 // (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2329
21967 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21968 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21969 {AliasPatternCond::K_Imm, uint32_t(0)},
21970 // (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 2332
21971 {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID},
21972 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21973 {AliasPatternCond::K_Imm, uint32_t(0)},
21974 // (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 2335
21975 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
21976 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21977 {AliasPatternCond::K_Imm, uint32_t(0)},
21978 // (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2338
21979 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21980 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21981 {AliasPatternCond::K_Imm, uint32_t(0)},
21982 // (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2341
21983 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21984 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21985 {AliasPatternCond::K_Imm, uint32_t(0)},
21986 // (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2344
21987 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
21988 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21989 {AliasPatternCond::K_Imm, uint32_t(0)},
21990 // (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2347
21991 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21992 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21993 {AliasPatternCond::K_Imm, uint32_t(0)},
21994 // (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2350
21995 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
21996 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
21997 {AliasPatternCond::K_Imm, uint32_t(0)},
21998 // (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 2353
21999 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
22000 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22001 {AliasPatternCond::K_Imm, uint32_t(0)},
22002 // (LDURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 2356
22003 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22004 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22005 {AliasPatternCond::K_Imm, uint32_t(0)},
22006 // (LDURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 2359
22007 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22008 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22009 {AliasPatternCond::K_Imm, uint32_t(0)},
22010 // (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 2362
22011 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22012 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22013 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22014 {AliasPatternCond::K_Reg, AArch64::WZR},
22015 // (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 2366
22016 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22017 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22018 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22019 {AliasPatternCond::K_Reg, AArch64::XZR},
22020 // (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 2370
22021 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22022 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22023 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22024 {AliasPatternCond::K_Reg, AArch64::WZR},
22025 // (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 2374
22026 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22027 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22028 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22029 {AliasPatternCond::K_Reg, AArch64::XZR},
22030 // (NOTv16i8 V128:$Vd, V128:$Vn) - 2378
22031 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22032 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22033 // (NOTv8i8 V64:$Vd, V64:$Vn) - 2380
22034 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22035 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22036 // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0) - 2382
22037 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22038 {AliasPatternCond::K_Reg, AArch64::WZR},
22039 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22040 {AliasPatternCond::K_Imm, uint32_t(0)},
22041 // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh) - 2386
22042 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22043 {AliasPatternCond::K_Reg, AArch64::WZR},
22044 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22045 // (ORNWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 2389
22046 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22047 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22048 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22049 {AliasPatternCond::K_Imm, uint32_t(0)},
22050 // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0) - 2393
22051 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22052 {AliasPatternCond::K_Reg, AArch64::XZR},
22053 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22054 {AliasPatternCond::K_Imm, uint32_t(0)},
22055 // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh) - 2397
22056 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22057 {AliasPatternCond::K_Reg, AArch64::XZR},
22058 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22059 // (ORNXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 2400
22060 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22061 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22062 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22063 {AliasPatternCond::K_Imm, uint32_t(0)},
22064 // (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 2404
22065 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22066 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22067 {AliasPatternCond::K_TiedReg, 1},
22068 {AliasPatternCond::K_TiedReg, 1},
22069 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22070 // (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0) - 2409
22071 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22072 {AliasPatternCond::K_Reg, AArch64::WZR},
22073 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22074 {AliasPatternCond::K_Imm, uint32_t(0)},
22075 // (ORRWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 2413
22076 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22077 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22078 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22079 {AliasPatternCond::K_Imm, uint32_t(0)},
22080 // (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0) - 2417
22081 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22082 {AliasPatternCond::K_Reg, AArch64::XZR},
22083 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22084 {AliasPatternCond::K_Imm, uint32_t(0)},
22085 // (ORRXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 2421
22086 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22087 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22088 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22089 {AliasPatternCond::K_Imm, uint32_t(0)},
22090 // (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 2425
22091 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22092 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22093 {AliasPatternCond::K_TiedReg, 1},
22094 {AliasPatternCond::K_TiedReg, 1},
22095 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22096 // (ORR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 2430
22097 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22098 {AliasPatternCond::K_Ignore, 0},
22099 {AliasPatternCond::K_Custom, 1},
22100 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22101 // (ORR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 2434
22102 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22103 {AliasPatternCond::K_Ignore, 0},
22104 {AliasPatternCond::K_Custom, 2},
22105 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22106 // (ORR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 2438
22107 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22108 {AliasPatternCond::K_Ignore, 0},
22109 {AliasPatternCond::K_Custom, 3},
22110 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22111 // (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn) - 2442
22112 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22113 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22114 {AliasPatternCond::K_TiedReg, 1},
22115 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22116 // (ORRv16i8 V128:$dst, V128:$src, V128:$src) - 2446
22117 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22118 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22119 {AliasPatternCond::K_TiedReg, 1},
22120 // (ORRv8i8 V64:$dst, V64:$src, V64:$src) - 2449
22121 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22122 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22123 {AliasPatternCond::K_TiedReg, 1},
22124 // (PACIA1716) - 2452
22125 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
22126 // (PACIASP) - 2453
22127 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
22128 // (PACIAZ) - 2454
22129 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
22130 // (PACIB1716) - 2455
22131 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
22132 // (PACIBSP) - 2456
22133 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
22134 // (PACIBZ) - 2457
22135 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
22136 // (PRFB_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2458
22137 {AliasPatternCond::K_Ignore, 0},
22138 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22139 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22140 {AliasPatternCond::K_Imm, uint32_t(0)},
22141 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22142 // (PRFB_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2463
22143 {AliasPatternCond::K_Ignore, 0},
22144 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22145 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22146 {AliasPatternCond::K_Imm, uint32_t(0)},
22147 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22148 // (PRFB_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2468
22149 {AliasPatternCond::K_Ignore, 0},
22150 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22151 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22152 {AliasPatternCond::K_Imm, uint32_t(0)},
22153 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22154 // (PRFD_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2473
22155 {AliasPatternCond::K_Ignore, 0},
22156 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22157 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22158 {AliasPatternCond::K_Imm, uint32_t(0)},
22159 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22160 // (PRFD_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2478
22161 {AliasPatternCond::K_Ignore, 0},
22162 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22163 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22164 {AliasPatternCond::K_Imm, uint32_t(0)},
22165 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22166 // (PRFD_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2483
22167 {AliasPatternCond::K_Ignore, 0},
22168 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22169 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22170 {AliasPatternCond::K_Imm, uint32_t(0)},
22171 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22172 // (PRFH_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2488
22173 {AliasPatternCond::K_Ignore, 0},
22174 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22175 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22176 {AliasPatternCond::K_Imm, uint32_t(0)},
22177 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22178 // (PRFH_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2493
22179 {AliasPatternCond::K_Ignore, 0},
22180 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22181 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22182 {AliasPatternCond::K_Imm, uint32_t(0)},
22183 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22184 // (PRFH_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2498
22185 {AliasPatternCond::K_Ignore, 0},
22186 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22187 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22188 {AliasPatternCond::K_Imm, uint32_t(0)},
22189 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22190 // (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2503
22191 {AliasPatternCond::K_Ignore, 0},
22192 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22193 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22194 {AliasPatternCond::K_Imm, uint32_t(0)},
22195 {AliasPatternCond::K_Imm, uint32_t(0)},
22196 // (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) - 2508
22197 {AliasPatternCond::K_Ignore, 0},
22198 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22199 {AliasPatternCond::K_Imm, uint32_t(0)},
22200 // (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) - 2511
22201 {AliasPatternCond::K_Ignore, 0},
22202 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22203 {AliasPatternCond::K_Imm, uint32_t(0)},
22204 // (PRFW_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2514
22205 {AliasPatternCond::K_Ignore, 0},
22206 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22207 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22208 {AliasPatternCond::K_Imm, uint32_t(0)},
22209 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22210 // (PRFW_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2519
22211 {AliasPatternCond::K_Ignore, 0},
22212 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22213 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22214 {AliasPatternCond::K_Imm, uint32_t(0)},
22215 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22216 // (PRFW_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2524
22217 {AliasPatternCond::K_Ignore, 0},
22218 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22219 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22220 {AliasPatternCond::K_Imm, uint32_t(0)},
22221 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22222 // (PTRUES_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 2529
22223 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22224 {AliasPatternCond::K_Imm, uint32_t(31)},
22225 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22226 // (PTRUES_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 2532
22227 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22228 {AliasPatternCond::K_Imm, uint32_t(31)},
22229 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22230 // (PTRUES_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 2535
22231 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22232 {AliasPatternCond::K_Imm, uint32_t(31)},
22233 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22234 // (PTRUES_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 2538
22235 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22236 {AliasPatternCond::K_Imm, uint32_t(31)},
22237 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22238 // (PTRUE_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 2541
22239 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22240 {AliasPatternCond::K_Imm, uint32_t(31)},
22241 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22242 // (PTRUE_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 2544
22243 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22244 {AliasPatternCond::K_Imm, uint32_t(31)},
22245 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22246 // (PTRUE_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 2547
22247 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22248 {AliasPatternCond::K_Imm, uint32_t(31)},
22249 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22250 // (PTRUE_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 2550
22251 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22252 {AliasPatternCond::K_Imm, uint32_t(31)},
22253 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22254 // (RET LR) - 2553
22255 {AliasPatternCond::K_Reg, AArch64::LR},
22256 // (SBCSWr GPR32:$dst, WZR, GPR32:$src) - 2554
22257 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22258 {AliasPatternCond::K_Reg, AArch64::WZR},
22259 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22260 // (SBCSXr GPR64:$dst, XZR, GPR64:$src) - 2557
22261 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22262 {AliasPatternCond::K_Reg, AArch64::XZR},
22263 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22264 // (SBCWr GPR32:$dst, WZR, GPR32:$src) - 2560
22265 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22266 {AliasPatternCond::K_Reg, AArch64::WZR},
22267 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22268 // (SBCXr GPR64:$dst, XZR, GPR64:$src) - 2563
22269 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22270 {AliasPatternCond::K_Reg, AArch64::XZR},
22271 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22272 // (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 2566
22273 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22274 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22275 {AliasPatternCond::K_Ignore, 0},
22276 {AliasPatternCond::K_Imm, uint32_t(31)},
22277 // (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 2570
22278 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22279 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22280 {AliasPatternCond::K_Imm, uint32_t(0)},
22281 {AliasPatternCond::K_Imm, uint32_t(7)},
22282 // (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 2574
22283 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22284 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22285 {AliasPatternCond::K_Imm, uint32_t(0)},
22286 {AliasPatternCond::K_Imm, uint32_t(15)},
22287 // (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 2578
22288 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22289 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22290 {AliasPatternCond::K_Ignore, 0},
22291 {AliasPatternCond::K_Imm, uint32_t(63)},
22292 // (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 2582
22293 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22294 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22295 {AliasPatternCond::K_Imm, uint32_t(0)},
22296 {AliasPatternCond::K_Imm, uint32_t(7)},
22297 // (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 2586
22298 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22299 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22300 {AliasPatternCond::K_Imm, uint32_t(0)},
22301 {AliasPatternCond::K_Imm, uint32_t(15)},
22302 // (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 2590
22303 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22304 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22305 {AliasPatternCond::K_Imm, uint32_t(0)},
22306 {AliasPatternCond::K_Imm, uint32_t(31)},
22307 // (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd) - 2594
22308 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22309 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22310 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22311 {AliasPatternCond::K_TiedReg, 0},
22312 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22313 // (SEL_ZPZZ_B ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd) - 2599
22314 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22315 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22316 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22317 {AliasPatternCond::K_TiedReg, 0},
22318 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22319 // (SEL_ZPZZ_D ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd) - 2604
22320 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22321 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22322 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22323 {AliasPatternCond::K_TiedReg, 0},
22324 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22325 // (SEL_ZPZZ_H ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd) - 2609
22326 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22327 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22328 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22329 {AliasPatternCond::K_TiedReg, 0},
22330 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22331 // (SEL_ZPZZ_S ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd) - 2614
22332 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22333 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
22334 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22335 {AliasPatternCond::K_TiedReg, 0},
22336 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22337 // (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 2619
22338 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22339 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22340 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22341 {AliasPatternCond::K_Reg, AArch64::XZR},
22342 // (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 2623
22343 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22344 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22345 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
22346 {AliasPatternCond::K_Reg, AArch64::XZR},
22347 // (SQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2627
22348 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22349 {AliasPatternCond::K_Ignore, 0},
22350 {AliasPatternCond::K_Imm, uint32_t(31)},
22351 {AliasPatternCond::K_Imm, uint32_t(1)},
22352 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22353 // (SQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2632
22354 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22355 {AliasPatternCond::K_Ignore, 0},
22356 {AliasPatternCond::K_Ignore, 0},
22357 {AliasPatternCond::K_Imm, uint32_t(1)},
22358 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22359 // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2637
22360 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22361 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22362 {AliasPatternCond::K_Imm, uint32_t(31)},
22363 {AliasPatternCond::K_Imm, uint32_t(1)},
22364 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22365 // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2642
22366 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22367 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22368 {AliasPatternCond::K_Ignore, 0},
22369 {AliasPatternCond::K_Imm, uint32_t(1)},
22370 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22371 // (SQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2647
22372 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22373 {AliasPatternCond::K_Ignore, 0},
22374 {AliasPatternCond::K_Imm, uint32_t(31)},
22375 {AliasPatternCond::K_Imm, uint32_t(1)},
22376 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22377 // (SQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2652
22378 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22379 {AliasPatternCond::K_Ignore, 0},
22380 {AliasPatternCond::K_Ignore, 0},
22381 {AliasPatternCond::K_Imm, uint32_t(1)},
22382 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22383 // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2657
22384 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22385 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22386 {AliasPatternCond::K_Imm, uint32_t(31)},
22387 {AliasPatternCond::K_Imm, uint32_t(1)},
22388 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22389 // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2662
22390 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22391 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22392 {AliasPatternCond::K_Ignore, 0},
22393 {AliasPatternCond::K_Imm, uint32_t(1)},
22394 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22395 // (SQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2667
22396 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22397 {AliasPatternCond::K_Ignore, 0},
22398 {AliasPatternCond::K_Imm, uint32_t(31)},
22399 {AliasPatternCond::K_Imm, uint32_t(1)},
22400 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22401 // (SQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 2672
22402 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22403 {AliasPatternCond::K_Ignore, 0},
22404 {AliasPatternCond::K_Ignore, 0},
22405 {AliasPatternCond::K_Imm, uint32_t(1)},
22406 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22407 // (SQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2677
22408 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22409 {AliasPatternCond::K_Ignore, 0},
22410 {AliasPatternCond::K_Imm, uint32_t(31)},
22411 {AliasPatternCond::K_Imm, uint32_t(1)},
22412 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22413 // (SQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2682
22414 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22415 {AliasPatternCond::K_Ignore, 0},
22416 {AliasPatternCond::K_Ignore, 0},
22417 {AliasPatternCond::K_Imm, uint32_t(1)},
22418 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22419 // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2687
22420 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22421 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22422 {AliasPatternCond::K_Imm, uint32_t(31)},
22423 {AliasPatternCond::K_Imm, uint32_t(1)},
22424 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22425 // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2692
22426 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22427 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22428 {AliasPatternCond::K_Ignore, 0},
22429 {AliasPatternCond::K_Imm, uint32_t(1)},
22430 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22431 // (SQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2697
22432 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22433 {AliasPatternCond::K_Ignore, 0},
22434 {AliasPatternCond::K_Imm, uint32_t(31)},
22435 {AliasPatternCond::K_Imm, uint32_t(1)},
22436 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22437 // (SQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 2702
22438 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22439 {AliasPatternCond::K_Ignore, 0},
22440 {AliasPatternCond::K_Ignore, 0},
22441 {AliasPatternCond::K_Imm, uint32_t(1)},
22442 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22443 // (SQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2707
22444 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22445 {AliasPatternCond::K_Ignore, 0},
22446 {AliasPatternCond::K_Imm, uint32_t(31)},
22447 {AliasPatternCond::K_Imm, uint32_t(1)},
22448 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22449 // (SQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2712
22450 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22451 {AliasPatternCond::K_Ignore, 0},
22452 {AliasPatternCond::K_Ignore, 0},
22453 {AliasPatternCond::K_Imm, uint32_t(1)},
22454 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22455 // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2717
22456 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22457 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22458 {AliasPatternCond::K_Imm, uint32_t(31)},
22459 {AliasPatternCond::K_Imm, uint32_t(1)},
22460 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22461 // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2722
22462 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22463 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22464 {AliasPatternCond::K_Ignore, 0},
22465 {AliasPatternCond::K_Imm, uint32_t(1)},
22466 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22467 // (SQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2727
22468 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22469 {AliasPatternCond::K_Ignore, 0},
22470 {AliasPatternCond::K_Imm, uint32_t(31)},
22471 {AliasPatternCond::K_Imm, uint32_t(1)},
22472 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22473 // (SQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 2732
22474 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22475 {AliasPatternCond::K_Ignore, 0},
22476 {AliasPatternCond::K_Ignore, 0},
22477 {AliasPatternCond::K_Imm, uint32_t(1)},
22478 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22479 // (SQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2737
22480 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22481 {AliasPatternCond::K_Ignore, 0},
22482 {AliasPatternCond::K_Imm, uint32_t(31)},
22483 {AliasPatternCond::K_Imm, uint32_t(1)},
22484 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22485 // (SQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2742
22486 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22487 {AliasPatternCond::K_Ignore, 0},
22488 {AliasPatternCond::K_Ignore, 0},
22489 {AliasPatternCond::K_Imm, uint32_t(1)},
22490 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22491 // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2747
22492 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22493 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22494 {AliasPatternCond::K_Imm, uint32_t(31)},
22495 {AliasPatternCond::K_Imm, uint32_t(1)},
22496 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22497 // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2752
22498 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22499 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22500 {AliasPatternCond::K_Ignore, 0},
22501 {AliasPatternCond::K_Imm, uint32_t(1)},
22502 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22503 // (SQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2757
22504 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22505 {AliasPatternCond::K_Ignore, 0},
22506 {AliasPatternCond::K_Imm, uint32_t(31)},
22507 {AliasPatternCond::K_Imm, uint32_t(1)},
22508 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22509 // (SQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2762
22510 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22511 {AliasPatternCond::K_Ignore, 0},
22512 {AliasPatternCond::K_Ignore, 0},
22513 {AliasPatternCond::K_Imm, uint32_t(1)},
22514 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22515 // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2767
22516 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22517 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22518 {AliasPatternCond::K_Imm, uint32_t(31)},
22519 {AliasPatternCond::K_Imm, uint32_t(1)},
22520 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22521 // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2772
22522 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22523 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22524 {AliasPatternCond::K_Ignore, 0},
22525 {AliasPatternCond::K_Imm, uint32_t(1)},
22526 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22527 // (SQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2777
22528 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22529 {AliasPatternCond::K_Ignore, 0},
22530 {AliasPatternCond::K_Imm, uint32_t(31)},
22531 {AliasPatternCond::K_Imm, uint32_t(1)},
22532 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22533 // (SQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 2782
22534 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22535 {AliasPatternCond::K_Ignore, 0},
22536 {AliasPatternCond::K_Ignore, 0},
22537 {AliasPatternCond::K_Imm, uint32_t(1)},
22538 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22539 // (SQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2787
22540 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22541 {AliasPatternCond::K_Ignore, 0},
22542 {AliasPatternCond::K_Imm, uint32_t(31)},
22543 {AliasPatternCond::K_Imm, uint32_t(1)},
22544 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22545 // (SQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2792
22546 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22547 {AliasPatternCond::K_Ignore, 0},
22548 {AliasPatternCond::K_Ignore, 0},
22549 {AliasPatternCond::K_Imm, uint32_t(1)},
22550 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22551 // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2797
22552 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22553 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22554 {AliasPatternCond::K_Imm, uint32_t(31)},
22555 {AliasPatternCond::K_Imm, uint32_t(1)},
22556 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22557 // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2802
22558 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22559 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22560 {AliasPatternCond::K_Ignore, 0},
22561 {AliasPatternCond::K_Imm, uint32_t(1)},
22562 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22563 // (SQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2807
22564 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22565 {AliasPatternCond::K_Ignore, 0},
22566 {AliasPatternCond::K_Imm, uint32_t(31)},
22567 {AliasPatternCond::K_Imm, uint32_t(1)},
22568 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22569 // (SQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 2812
22570 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22571 {AliasPatternCond::K_Ignore, 0},
22572 {AliasPatternCond::K_Ignore, 0},
22573 {AliasPatternCond::K_Imm, uint32_t(1)},
22574 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22575 // (SQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2817
22576 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22577 {AliasPatternCond::K_Ignore, 0},
22578 {AliasPatternCond::K_Imm, uint32_t(31)},
22579 {AliasPatternCond::K_Imm, uint32_t(1)},
22580 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22581 // (SQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2822
22582 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22583 {AliasPatternCond::K_Ignore, 0},
22584 {AliasPatternCond::K_Ignore, 0},
22585 {AliasPatternCond::K_Imm, uint32_t(1)},
22586 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22587 // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2827
22588 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22589 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22590 {AliasPatternCond::K_Imm, uint32_t(31)},
22591 {AliasPatternCond::K_Imm, uint32_t(1)},
22592 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22593 // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2832
22594 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22595 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
22596 {AliasPatternCond::K_Ignore, 0},
22597 {AliasPatternCond::K_Imm, uint32_t(1)},
22598 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22599 // (SQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2837
22600 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22601 {AliasPatternCond::K_Ignore, 0},
22602 {AliasPatternCond::K_Imm, uint32_t(31)},
22603 {AliasPatternCond::K_Imm, uint32_t(1)},
22604 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22605 // (SQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 2842
22606 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22607 {AliasPatternCond::K_Ignore, 0},
22608 {AliasPatternCond::K_Ignore, 0},
22609 {AliasPatternCond::K_Imm, uint32_t(1)},
22610 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22611 // (SST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2847
22612 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22613 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22614 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22615 {AliasPatternCond::K_Imm, uint32_t(0)},
22616 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22617 // (SST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2852
22618 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22619 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22620 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22621 {AliasPatternCond::K_Imm, uint32_t(0)},
22622 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22623 // (SST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2857
22624 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22625 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22626 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22627 {AliasPatternCond::K_Imm, uint32_t(0)},
22628 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22629 // (SST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2862
22630 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22631 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22632 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22633 {AliasPatternCond::K_Imm, uint32_t(0)},
22634 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22635 // (SST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2867
22636 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22637 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22638 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22639 {AliasPatternCond::K_Imm, uint32_t(0)},
22640 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22641 // (SST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2872
22642 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22643 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22644 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22645 {AliasPatternCond::K_Imm, uint32_t(0)},
22646 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22647 // (SST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2877
22648 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22649 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22650 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22651 {AliasPatternCond::K_Imm, uint32_t(0)},
22652 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22653 // (ST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2882
22654 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22655 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22656 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22657 {AliasPatternCond::K_Imm, uint32_t(0)},
22658 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22659 // (ST1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2887
22660 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22661 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22662 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22663 {AliasPatternCond::K_Imm, uint32_t(0)},
22664 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22665 // (ST1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2892
22666 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22667 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22668 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22669 {AliasPatternCond::K_Imm, uint32_t(0)},
22670 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22671 // (ST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2897
22672 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22673 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22674 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22675 {AliasPatternCond::K_Imm, uint32_t(0)},
22676 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22677 // (ST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2902
22678 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22679 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22680 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22681 {AliasPatternCond::K_Imm, uint32_t(0)},
22682 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22683 // (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 2907
22684 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22685 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
22686 {AliasPatternCond::K_Ignore, 0},
22687 {AliasPatternCond::K_Reg, AArch64::XZR},
22688 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22689 // (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 2912
22690 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22691 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
22692 {AliasPatternCond::K_Ignore, 0},
22693 {AliasPatternCond::K_Reg, AArch64::XZR},
22694 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22695 // (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 2917
22696 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22697 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
22698 {AliasPatternCond::K_Ignore, 0},
22699 {AliasPatternCond::K_Reg, AArch64::XZR},
22700 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22701 // (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 2922
22702 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22703 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
22704 {AliasPatternCond::K_Ignore, 0},
22705 {AliasPatternCond::K_Reg, AArch64::XZR},
22706 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22707 // (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 2927
22708 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22709 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
22710 {AliasPatternCond::K_Ignore, 0},
22711 {AliasPatternCond::K_Reg, AArch64::XZR},
22712 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22713 // (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 2932
22714 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22715 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
22716 {AliasPatternCond::K_Ignore, 0},
22717 {AliasPatternCond::K_Reg, AArch64::XZR},
22718 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22719 // (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 2937
22720 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22721 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
22722 {AliasPatternCond::K_Ignore, 0},
22723 {AliasPatternCond::K_Reg, AArch64::XZR},
22724 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22725 // (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 2942
22726 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22727 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
22728 {AliasPatternCond::K_Ignore, 0},
22729 {AliasPatternCond::K_Reg, AArch64::XZR},
22730 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22731 // (ST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2947
22732 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22733 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22734 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22735 {AliasPatternCond::K_Imm, uint32_t(0)},
22736 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22737 // (ST1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2952
22738 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22739 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22740 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22741 {AliasPatternCond::K_Imm, uint32_t(0)},
22742 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22743 // (ST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2957
22744 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22745 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22746 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22747 {AliasPatternCond::K_Imm, uint32_t(0)},
22748 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22749 // (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 2962
22750 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22751 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22752 {AliasPatternCond::K_Ignore, 0},
22753 {AliasPatternCond::K_Reg, AArch64::XZR},
22754 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22755 // (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 2967
22756 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22757 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22758 {AliasPatternCond::K_Ignore, 0},
22759 {AliasPatternCond::K_Reg, AArch64::XZR},
22760 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22761 // (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 2972
22762 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22763 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22764 {AliasPatternCond::K_Ignore, 0},
22765 {AliasPatternCond::K_Reg, AArch64::XZR},
22766 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22767 // (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 2977
22768 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22769 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22770 {AliasPatternCond::K_Ignore, 0},
22771 {AliasPatternCond::K_Reg, AArch64::XZR},
22772 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22773 // (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 2982
22774 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22775 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22776 {AliasPatternCond::K_Ignore, 0},
22777 {AliasPatternCond::K_Reg, AArch64::XZR},
22778 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22779 // (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 2987
22780 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22781 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22782 {AliasPatternCond::K_Ignore, 0},
22783 {AliasPatternCond::K_Reg, AArch64::XZR},
22784 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22785 // (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 2992
22786 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22787 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
22788 {AliasPatternCond::K_Ignore, 0},
22789 {AliasPatternCond::K_Reg, AArch64::XZR},
22790 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22791 // (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 2997
22792 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22793 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22794 {AliasPatternCond::K_Ignore, 0},
22795 {AliasPatternCond::K_Reg, AArch64::XZR},
22796 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22797 // (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 3002
22798 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22799 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
22800 {AliasPatternCond::K_Ignore, 0},
22801 {AliasPatternCond::K_Reg, AArch64::XZR},
22802 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22803 // (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 3007
22804 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22805 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
22806 {AliasPatternCond::K_Ignore, 0},
22807 {AliasPatternCond::K_Reg, AArch64::XZR},
22808 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22809 // (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 3012
22810 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22811 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
22812 {AliasPatternCond::K_Ignore, 0},
22813 {AliasPatternCond::K_Reg, AArch64::XZR},
22814 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22815 // (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 3017
22816 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22817 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
22818 {AliasPatternCond::K_Ignore, 0},
22819 {AliasPatternCond::K_Reg, AArch64::XZR},
22820 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22821 // (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 3022
22822 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22823 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
22824 {AliasPatternCond::K_Ignore, 0},
22825 {AliasPatternCond::K_Reg, AArch64::XZR},
22826 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22827 // (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 3027
22828 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22829 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
22830 {AliasPatternCond::K_Ignore, 0},
22831 {AliasPatternCond::K_Reg, AArch64::XZR},
22832 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22833 // (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 3032
22834 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22835 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
22836 {AliasPatternCond::K_Ignore, 0},
22837 {AliasPatternCond::K_Reg, AArch64::XZR},
22838 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22839 // (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 3037
22840 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22841 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
22842 {AliasPatternCond::K_Ignore, 0},
22843 {AliasPatternCond::K_Reg, AArch64::XZR},
22844 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22845 // (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 3042
22846 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22847 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22848 {AliasPatternCond::K_Ignore, 0},
22849 {AliasPatternCond::K_Reg, AArch64::XZR},
22850 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22851 // (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 3047
22852 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22853 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
22854 {AliasPatternCond::K_Ignore, 0},
22855 {AliasPatternCond::K_Reg, AArch64::XZR},
22856 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22857 // (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 3052
22858 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22859 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22860 {AliasPatternCond::K_Ignore, 0},
22861 {AliasPatternCond::K_Reg, AArch64::XZR},
22862 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22863 // (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 3057
22864 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22865 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
22866 {AliasPatternCond::K_Ignore, 0},
22867 {AliasPatternCond::K_Reg, AArch64::XZR},
22868 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22869 // (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 3062
22870 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22871 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
22872 {AliasPatternCond::K_Ignore, 0},
22873 {AliasPatternCond::K_Reg, AArch64::XZR},
22874 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22875 // (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 3067
22876 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22877 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22878 {AliasPatternCond::K_Ignore, 0},
22879 {AliasPatternCond::K_Reg, AArch64::XZR},
22880 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22881 // (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 3072
22882 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22883 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
22884 {AliasPatternCond::K_Ignore, 0},
22885 {AliasPatternCond::K_Reg, AArch64::XZR},
22886 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22887 // (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 3077
22888 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22889 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22890 {AliasPatternCond::K_Ignore, 0},
22891 {AliasPatternCond::K_Reg, AArch64::XZR},
22892 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22893 // (ST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3082
22894 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22895 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22896 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22897 {AliasPatternCond::K_Imm, uint32_t(0)},
22898 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22899 // (ST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3087
22900 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
22901 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22902 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22903 {AliasPatternCond::K_Imm, uint32_t(0)},
22904 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22905 // (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 3092
22906 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22907 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22908 {AliasPatternCond::K_Ignore, 0},
22909 {AliasPatternCond::K_Ignore, 0},
22910 {AliasPatternCond::K_Reg, AArch64::XZR},
22911 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22912 // (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 3098
22913 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22914 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22915 {AliasPatternCond::K_Ignore, 0},
22916 {AliasPatternCond::K_Ignore, 0},
22917 {AliasPatternCond::K_Reg, AArch64::XZR},
22918 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22919 // (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 3104
22920 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22921 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22922 {AliasPatternCond::K_Ignore, 0},
22923 {AliasPatternCond::K_Ignore, 0},
22924 {AliasPatternCond::K_Reg, AArch64::XZR},
22925 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22926 // (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 3110
22927 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22928 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
22929 {AliasPatternCond::K_Ignore, 0},
22930 {AliasPatternCond::K_Ignore, 0},
22931 {AliasPatternCond::K_Reg, AArch64::XZR},
22932 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22933 // (ST2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3116
22934 {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID},
22935 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22936 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22937 {AliasPatternCond::K_Imm, uint32_t(0)},
22938 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22939 // (ST2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3121
22940 {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID},
22941 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22942 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22943 {AliasPatternCond::K_Imm, uint32_t(0)},
22944 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22945 // (ST2GOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 3126
22946 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22947 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22948 {AliasPatternCond::K_Imm, uint32_t(0)},
22949 {AliasPatternCond::K_Feature, AArch64::FeatureMTE},
22950 // (ST2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3130
22951 {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID},
22952 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
22953 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22954 {AliasPatternCond::K_Imm, uint32_t(0)},
22955 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
22956 // (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 3135
22957 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22958 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22959 {AliasPatternCond::K_Ignore, 0},
22960 {AliasPatternCond::K_Reg, AArch64::XZR},
22961 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22962 // (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 3140
22963 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22964 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22965 {AliasPatternCond::K_Ignore, 0},
22966 {AliasPatternCond::K_Reg, AArch64::XZR},
22967 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22968 // (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 3145
22969 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22970 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
22971 {AliasPatternCond::K_Ignore, 0},
22972 {AliasPatternCond::K_Reg, AArch64::XZR},
22973 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22974 // (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 3150
22975 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22976 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
22977 {AliasPatternCond::K_Ignore, 0},
22978 {AliasPatternCond::K_Reg, AArch64::XZR},
22979 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22980 // (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 3155
22981 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22982 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22983 {AliasPatternCond::K_Ignore, 0},
22984 {AliasPatternCond::K_Reg, AArch64::XZR},
22985 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22986 // (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 3160
22987 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22988 {AliasPatternCond::K_RegClass, AArch64::DDRegClassID},
22989 {AliasPatternCond::K_Ignore, 0},
22990 {AliasPatternCond::K_Reg, AArch64::XZR},
22991 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22992 // (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 3165
22993 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
22994 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
22995 {AliasPatternCond::K_Ignore, 0},
22996 {AliasPatternCond::K_Reg, AArch64::XZR},
22997 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
22998 // (ST2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3170
22999 {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID},
23000 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23001 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23002 {AliasPatternCond::K_Imm, uint32_t(0)},
23003 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23004 // (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 3175
23005 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23006 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
23007 {AliasPatternCond::K_Ignore, 0},
23008 {AliasPatternCond::K_Ignore, 0},
23009 {AliasPatternCond::K_Reg, AArch64::XZR},
23010 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23011 // (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 3181
23012 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23013 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
23014 {AliasPatternCond::K_Ignore, 0},
23015 {AliasPatternCond::K_Ignore, 0},
23016 {AliasPatternCond::K_Reg, AArch64::XZR},
23017 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23018 // (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 3187
23019 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23020 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
23021 {AliasPatternCond::K_Ignore, 0},
23022 {AliasPatternCond::K_Ignore, 0},
23023 {AliasPatternCond::K_Reg, AArch64::XZR},
23024 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23025 // (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 3193
23026 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23027 {AliasPatternCond::K_RegClass, AArch64::QQRegClassID},
23028 {AliasPatternCond::K_Ignore, 0},
23029 {AliasPatternCond::K_Ignore, 0},
23030 {AliasPatternCond::K_Reg, AArch64::XZR},
23031 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23032 // (ST3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3199
23033 {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID},
23034 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23035 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23036 {AliasPatternCond::K_Imm, uint32_t(0)},
23037 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23038 // (ST3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3204
23039 {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID},
23040 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23041 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23042 {AliasPatternCond::K_Imm, uint32_t(0)},
23043 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23044 // (ST3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3209
23045 {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID},
23046 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23047 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23048 {AliasPatternCond::K_Imm, uint32_t(0)},
23049 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23050 // (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 3214
23051 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23052 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
23053 {AliasPatternCond::K_Ignore, 0},
23054 {AliasPatternCond::K_Reg, AArch64::XZR},
23055 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23056 // (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 3219
23057 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23058 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
23059 {AliasPatternCond::K_Ignore, 0},
23060 {AliasPatternCond::K_Reg, AArch64::XZR},
23061 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23062 // (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 3224
23063 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23064 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
23065 {AliasPatternCond::K_Ignore, 0},
23066 {AliasPatternCond::K_Reg, AArch64::XZR},
23067 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23068 // (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 3229
23069 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23070 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
23071 {AliasPatternCond::K_Ignore, 0},
23072 {AliasPatternCond::K_Reg, AArch64::XZR},
23073 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23074 // (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 3234
23075 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23076 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
23077 {AliasPatternCond::K_Ignore, 0},
23078 {AliasPatternCond::K_Reg, AArch64::XZR},
23079 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23080 // (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 3239
23081 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23082 {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID},
23083 {AliasPatternCond::K_Ignore, 0},
23084 {AliasPatternCond::K_Reg, AArch64::XZR},
23085 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23086 // (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 3244
23087 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23088 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
23089 {AliasPatternCond::K_Ignore, 0},
23090 {AliasPatternCond::K_Reg, AArch64::XZR},
23091 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23092 // (ST3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3249
23093 {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID},
23094 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23095 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23096 {AliasPatternCond::K_Imm, uint32_t(0)},
23097 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23098 // (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 3254
23099 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23100 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
23101 {AliasPatternCond::K_Ignore, 0},
23102 {AliasPatternCond::K_Ignore, 0},
23103 {AliasPatternCond::K_Reg, AArch64::XZR},
23104 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23105 // (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 3260
23106 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23107 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
23108 {AliasPatternCond::K_Ignore, 0},
23109 {AliasPatternCond::K_Ignore, 0},
23110 {AliasPatternCond::K_Reg, AArch64::XZR},
23111 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23112 // (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 3266
23113 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23114 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
23115 {AliasPatternCond::K_Ignore, 0},
23116 {AliasPatternCond::K_Ignore, 0},
23117 {AliasPatternCond::K_Reg, AArch64::XZR},
23118 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23119 // (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 3272
23120 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23121 {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID},
23122 {AliasPatternCond::K_Ignore, 0},
23123 {AliasPatternCond::K_Ignore, 0},
23124 {AliasPatternCond::K_Reg, AArch64::XZR},
23125 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23126 // (ST4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3278
23127 {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID},
23128 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23129 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23130 {AliasPatternCond::K_Imm, uint32_t(0)},
23131 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23132 // (ST4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3283
23133 {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID},
23134 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23135 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23136 {AliasPatternCond::K_Imm, uint32_t(0)},
23137 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23138 // (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 3288
23139 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23140 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
23141 {AliasPatternCond::K_Ignore, 0},
23142 {AliasPatternCond::K_Reg, AArch64::XZR},
23143 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23144 // (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 3293
23145 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23146 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
23147 {AliasPatternCond::K_Ignore, 0},
23148 {AliasPatternCond::K_Reg, AArch64::XZR},
23149 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23150 // (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 3298
23151 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23152 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
23153 {AliasPatternCond::K_Ignore, 0},
23154 {AliasPatternCond::K_Reg, AArch64::XZR},
23155 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23156 // (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 3303
23157 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23158 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
23159 {AliasPatternCond::K_Ignore, 0},
23160 {AliasPatternCond::K_Reg, AArch64::XZR},
23161 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23162 // (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 3308
23163 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23164 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
23165 {AliasPatternCond::K_Ignore, 0},
23166 {AliasPatternCond::K_Reg, AArch64::XZR},
23167 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23168 // (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 3313
23169 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23170 {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID},
23171 {AliasPatternCond::K_Ignore, 0},
23172 {AliasPatternCond::K_Reg, AArch64::XZR},
23173 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23174 // (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 3318
23175 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23176 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
23177 {AliasPatternCond::K_Ignore, 0},
23178 {AliasPatternCond::K_Reg, AArch64::XZR},
23179 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23180 // (ST4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3323
23181 {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID},
23182 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23183 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23184 {AliasPatternCond::K_Imm, uint32_t(0)},
23185 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23186 // (ST4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3328
23187 {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID},
23188 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23189 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23190 {AliasPatternCond::K_Imm, uint32_t(0)},
23191 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23192 // (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 3333
23193 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23194 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
23195 {AliasPatternCond::K_Ignore, 0},
23196 {AliasPatternCond::K_Ignore, 0},
23197 {AliasPatternCond::K_Reg, AArch64::XZR},
23198 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23199 // (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 3339
23200 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23201 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
23202 {AliasPatternCond::K_Ignore, 0},
23203 {AliasPatternCond::K_Ignore, 0},
23204 {AliasPatternCond::K_Reg, AArch64::XZR},
23205 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23206 // (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 3345
23207 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23208 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
23209 {AliasPatternCond::K_Ignore, 0},
23210 {AliasPatternCond::K_Ignore, 0},
23211 {AliasPatternCond::K_Reg, AArch64::XZR},
23212 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23213 // (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 3351
23214 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23215 {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID},
23216 {AliasPatternCond::K_Ignore, 0},
23217 {AliasPatternCond::K_Ignore, 0},
23218 {AliasPatternCond::K_Reg, AArch64::XZR},
23219 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23220 // (STGOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 3357
23221 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23222 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23223 {AliasPatternCond::K_Imm, uint32_t(0)},
23224 {AliasPatternCond::K_Feature, AArch64::FeatureMTE},
23225 // (STGPi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3361
23226 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23227 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23228 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23229 {AliasPatternCond::K_Imm, uint32_t(0)},
23230 {AliasPatternCond::K_Feature, AArch64::FeatureMTE},
23231 // (STLURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 3366
23232 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23233 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23234 {AliasPatternCond::K_Imm, uint32_t(0)},
23235 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
23236 // (STLURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 3370
23237 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23238 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23239 {AliasPatternCond::K_Imm, uint32_t(0)},
23240 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
23241 // (STLURWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3374
23242 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23243 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23244 {AliasPatternCond::K_Imm, uint32_t(0)},
23245 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
23246 // (STLURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3378
23247 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23248 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23249 {AliasPatternCond::K_Imm, uint32_t(0)},
23250 {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO},
23251 // (STNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 3382
23252 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
23253 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
23254 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23255 {AliasPatternCond::K_Imm, uint32_t(0)},
23256 // (STNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3386
23257 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
23258 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
23259 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23260 {AliasPatternCond::K_Imm, uint32_t(0)},
23261 // (STNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 3390
23262 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
23263 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
23264 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23265 {AliasPatternCond::K_Imm, uint32_t(0)},
23266 // (STNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 3394
23267 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23268 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23269 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23270 {AliasPatternCond::K_Imm, uint32_t(0)},
23271 // (STNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3398
23272 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23273 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23274 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23275 {AliasPatternCond::K_Imm, uint32_t(0)},
23276 // (STNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3402
23277 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23278 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23279 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23280 {AliasPatternCond::K_Imm, uint32_t(0)},
23281 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23282 // (STNT1B_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3407
23283 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23284 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23285 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23286 {AliasPatternCond::K_Reg, AArch64::XZR},
23287 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
23288 // (STNT1B_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3412
23289 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23290 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23291 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23292 {AliasPatternCond::K_Reg, AArch64::XZR},
23293 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
23294 // (STNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3417
23295 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23296 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23297 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23298 {AliasPatternCond::K_Imm, uint32_t(0)},
23299 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23300 // (STNT1D_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3422
23301 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23302 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23303 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23304 {AliasPatternCond::K_Reg, AArch64::XZR},
23305 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
23306 // (STNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3427
23307 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23308 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23309 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23310 {AliasPatternCond::K_Imm, uint32_t(0)},
23311 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23312 // (STNT1H_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3432
23313 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23314 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23315 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23316 {AliasPatternCond::K_Reg, AArch64::XZR},
23317 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
23318 // (STNT1H_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3437
23319 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23320 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23321 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23322 {AliasPatternCond::K_Reg, AArch64::XZR},
23323 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
23324 // (STNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3442
23325 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23326 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23327 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23328 {AliasPatternCond::K_Imm, uint32_t(0)},
23329 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23330 // (STNT1W_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3447
23331 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23332 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23333 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23334 {AliasPatternCond::K_Reg, AArch64::XZR},
23335 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
23336 // (STNT1W_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3452
23337 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23338 {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID},
23339 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23340 {AliasPatternCond::K_Reg, AArch64::XZR},
23341 {AliasPatternCond::K_Feature, AArch64::FeatureSVE2},
23342 // (STPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 3457
23343 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
23344 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
23345 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23346 {AliasPatternCond::K_Imm, uint32_t(0)},
23347 // (STPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3461
23348 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
23349 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
23350 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23351 {AliasPatternCond::K_Imm, uint32_t(0)},
23352 // (STPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 3465
23353 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
23354 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
23355 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23356 {AliasPatternCond::K_Imm, uint32_t(0)},
23357 // (STPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 3469
23358 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23359 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23360 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23361 {AliasPatternCond::K_Imm, uint32_t(0)},
23362 // (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3473
23363 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23364 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23365 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23366 {AliasPatternCond::K_Imm, uint32_t(0)},
23367 // (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3477
23368 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23369 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23370 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23371 {AliasPatternCond::K_Imm, uint32_t(0)},
23372 {AliasPatternCond::K_Imm, uint32_t(0)},
23373 // (STRBBui GPR32z:$Rt, GPR64sp:$Rn, 0) - 3482
23374 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23375 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23376 {AliasPatternCond::K_Imm, uint32_t(0)},
23377 // (STRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3485
23378 {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID},
23379 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23380 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23381 {AliasPatternCond::K_Imm, uint32_t(0)},
23382 {AliasPatternCond::K_Imm, uint32_t(0)},
23383 // (STRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 3490
23384 {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID},
23385 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23386 {AliasPatternCond::K_Imm, uint32_t(0)},
23387 // (STRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3493
23388 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
23389 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23390 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23391 {AliasPatternCond::K_Imm, uint32_t(0)},
23392 {AliasPatternCond::K_Imm, uint32_t(0)},
23393 // (STRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 3498
23394 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
23395 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23396 {AliasPatternCond::K_Imm, uint32_t(0)},
23397 // (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3501
23398 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23399 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23400 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23401 {AliasPatternCond::K_Imm, uint32_t(0)},
23402 {AliasPatternCond::K_Imm, uint32_t(0)},
23403 // (STRHHui GPR32z:$Rt, GPR64sp:$Rn, 0) - 3506
23404 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23405 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23406 {AliasPatternCond::K_Imm, uint32_t(0)},
23407 // (STRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3509
23408 {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID},
23409 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23410 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23411 {AliasPatternCond::K_Imm, uint32_t(0)},
23412 {AliasPatternCond::K_Imm, uint32_t(0)},
23413 // (STRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 3514
23414 {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID},
23415 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23416 {AliasPatternCond::K_Imm, uint32_t(0)},
23417 // (STRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3517
23418 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
23419 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23420 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23421 {AliasPatternCond::K_Imm, uint32_t(0)},
23422 {AliasPatternCond::K_Imm, uint32_t(0)},
23423 // (STRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 3522
23424 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
23425 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23426 {AliasPatternCond::K_Imm, uint32_t(0)},
23427 // (STRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3525
23428 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
23429 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23430 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23431 {AliasPatternCond::K_Imm, uint32_t(0)},
23432 {AliasPatternCond::K_Imm, uint32_t(0)},
23433 // (STRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 3530
23434 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
23435 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23436 {AliasPatternCond::K_Imm, uint32_t(0)},
23437 // (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3533
23438 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23439 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23440 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23441 {AliasPatternCond::K_Imm, uint32_t(0)},
23442 {AliasPatternCond::K_Imm, uint32_t(0)},
23443 // (STRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 3538
23444 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23445 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23446 {AliasPatternCond::K_Imm, uint32_t(0)},
23447 // (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3541
23448 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23449 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23450 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23451 {AliasPatternCond::K_Imm, uint32_t(0)},
23452 {AliasPatternCond::K_Imm, uint32_t(0)},
23453 // (STRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 3546
23454 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23455 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23456 {AliasPatternCond::K_Imm, uint32_t(0)},
23457 // (STR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) - 3549
23458 {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID},
23459 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23460 {AliasPatternCond::K_Imm, uint32_t(0)},
23461 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23462 // (STR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 3553
23463 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23464 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23465 {AliasPatternCond::K_Imm, uint32_t(0)},
23466 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23467 // (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 3557
23468 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23469 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23470 {AliasPatternCond::K_Imm, uint32_t(0)},
23471 // (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 3560
23472 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23473 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23474 {AliasPatternCond::K_Imm, uint32_t(0)},
23475 // (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3563
23476 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23477 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23478 {AliasPatternCond::K_Imm, uint32_t(0)},
23479 // (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3566
23480 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23481 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23482 {AliasPatternCond::K_Imm, uint32_t(0)},
23483 // (STURBBi GPR32z:$Rt, GPR64sp:$Rn, 0) - 3569
23484 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23485 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23486 {AliasPatternCond::K_Imm, uint32_t(0)},
23487 // (STURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 3572
23488 {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID},
23489 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23490 {AliasPatternCond::K_Imm, uint32_t(0)},
23491 // (STURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 3575
23492 {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID},
23493 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23494 {AliasPatternCond::K_Imm, uint32_t(0)},
23495 // (STURHHi GPR32z:$Rt, GPR64sp:$Rn, 0) - 3578
23496 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23497 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23498 {AliasPatternCond::K_Imm, uint32_t(0)},
23499 // (STURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 3581
23500 {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID},
23501 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23502 {AliasPatternCond::K_Imm, uint32_t(0)},
23503 // (STURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 3584
23504 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
23505 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23506 {AliasPatternCond::K_Imm, uint32_t(0)},
23507 // (STURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 3587
23508 {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID},
23509 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23510 {AliasPatternCond::K_Imm, uint32_t(0)},
23511 // (STURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 3590
23512 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23513 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23514 {AliasPatternCond::K_Imm, uint32_t(0)},
23515 // (STURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 3593
23516 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23517 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23518 {AliasPatternCond::K_Imm, uint32_t(0)},
23519 // (STZ2GOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 3596
23520 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23521 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23522 {AliasPatternCond::K_Imm, uint32_t(0)},
23523 {AliasPatternCond::K_Feature, AArch64::FeatureMTE},
23524 // (STZGOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 3600
23525 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23526 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23527 {AliasPatternCond::K_Imm, uint32_t(0)},
23528 {AliasPatternCond::K_Feature, AArch64::FeatureMTE},
23529 // (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 3604
23530 {AliasPatternCond::K_Reg, AArch64::WZR},
23531 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
23532 // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 3606
23533 {AliasPatternCond::K_Reg, AArch64::WZR},
23534 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23535 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23536 {AliasPatternCond::K_Imm, uint32_t(0)},
23537 // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - 3610
23538 {AliasPatternCond::K_Reg, AArch64::WZR},
23539 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23540 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23541 // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0) - 3613
23542 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23543 {AliasPatternCond::K_Reg, AArch64::WZR},
23544 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23545 {AliasPatternCond::K_Imm, uint32_t(0)},
23546 // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) - 3617
23547 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23548 {AliasPatternCond::K_Reg, AArch64::WZR},
23549 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23550 // (SUBSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 3620
23551 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23552 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23553 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23554 {AliasPatternCond::K_Imm, uint32_t(0)},
23555 // (SUBSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - 3624
23556 {AliasPatternCond::K_Reg, AArch64::WZR},
23557 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
23558 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23559 {AliasPatternCond::K_Imm, uint32_t(16)},
23560 // (SUBSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - 3628
23561 {AliasPatternCond::K_Reg, AArch64::WZR},
23562 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
23563 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23564 // (SUBSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 3631
23565 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23566 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
23567 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23568 {AliasPatternCond::K_Imm, uint32_t(16)},
23569 // (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 3635
23570 {AliasPatternCond::K_Reg, AArch64::XZR},
23571 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23572 // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 3637
23573 {AliasPatternCond::K_Reg, AArch64::XZR},
23574 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23575 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23576 {AliasPatternCond::K_Imm, uint32_t(0)},
23577 // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - 3641
23578 {AliasPatternCond::K_Reg, AArch64::XZR},
23579 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23580 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23581 // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0) - 3644
23582 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23583 {AliasPatternCond::K_Reg, AArch64::XZR},
23584 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23585 {AliasPatternCond::K_Imm, uint32_t(0)},
23586 // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) - 3648
23587 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23588 {AliasPatternCond::K_Reg, AArch64::XZR},
23589 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23590 // (SUBSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 3651
23591 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23592 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23593 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23594 {AliasPatternCond::K_Imm, uint32_t(0)},
23595 // (SUBSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - 3655
23596 {AliasPatternCond::K_Reg, AArch64::XZR},
23597 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23598 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23599 // (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 3658
23600 {AliasPatternCond::K_Reg, AArch64::XZR},
23601 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
23602 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23603 {AliasPatternCond::K_Imm, uint32_t(24)},
23604 // (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 3662
23605 {AliasPatternCond::K_Reg, AArch64::XZR},
23606 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23607 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23608 // (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 3665
23609 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23610 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
23611 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23612 {AliasPatternCond::K_Imm, uint32_t(24)},
23613 // (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0) - 3669
23614 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23615 {AliasPatternCond::K_Reg, AArch64::WZR},
23616 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23617 {AliasPatternCond::K_Imm, uint32_t(0)},
23618 // (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) - 3673
23619 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23620 {AliasPatternCond::K_Reg, AArch64::WZR},
23621 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23622 // (SUBWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 3676
23623 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23624 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23625 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23626 {AliasPatternCond::K_Imm, uint32_t(0)},
23627 // (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - 3680
23628 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
23629 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
23630 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23631 {AliasPatternCond::K_Imm, uint32_t(16)},
23632 // (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 3684
23633 {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID},
23634 {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID},
23635 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23636 {AliasPatternCond::K_Imm, uint32_t(16)},
23637 // (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0) - 3688
23638 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23639 {AliasPatternCond::K_Reg, AArch64::XZR},
23640 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23641 {AliasPatternCond::K_Imm, uint32_t(0)},
23642 // (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) - 3692
23643 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23644 {AliasPatternCond::K_Reg, AArch64::XZR},
23645 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23646 // (SUBXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 3695
23647 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23648 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23649 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23650 {AliasPatternCond::K_Imm, uint32_t(0)},
23651 // (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 3699
23652 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
23653 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23654 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23655 {AliasPatternCond::K_Imm, uint32_t(24)},
23656 // (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 3703
23657 {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID},
23658 {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID},
23659 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23660 {AliasPatternCond::K_Imm, uint32_t(24)},
23661 // (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) - 3707
23662 {AliasPatternCond::K_Ignore, 0},
23663 {AliasPatternCond::K_Ignore, 0},
23664 {AliasPatternCond::K_Ignore, 0},
23665 {AliasPatternCond::K_Ignore, 0},
23666 {AliasPatternCond::K_Reg, AArch64::XZR},
23667 // (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 3712
23668 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23669 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23670 {AliasPatternCond::K_Ignore, 0},
23671 {AliasPatternCond::K_Imm, uint32_t(31)},
23672 // (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 3716
23673 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23674 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23675 {AliasPatternCond::K_Imm, uint32_t(0)},
23676 {AliasPatternCond::K_Imm, uint32_t(7)},
23677 // (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 3720
23678 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23679 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23680 {AliasPatternCond::K_Imm, uint32_t(0)},
23681 {AliasPatternCond::K_Imm, uint32_t(15)},
23682 // (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 3724
23683 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23684 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23685 {AliasPatternCond::K_Ignore, 0},
23686 {AliasPatternCond::K_Imm, uint32_t(63)},
23687 // (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 3728
23688 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23689 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23690 {AliasPatternCond::K_Imm, uint32_t(0)},
23691 {AliasPatternCond::K_Imm, uint32_t(7)},
23692 // (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 3732
23693 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23694 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23695 {AliasPatternCond::K_Imm, uint32_t(0)},
23696 {AliasPatternCond::K_Imm, uint32_t(15)},
23697 // (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 3736
23698 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23699 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23700 {AliasPatternCond::K_Imm, uint32_t(0)},
23701 {AliasPatternCond::K_Imm, uint32_t(31)},
23702 // (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 3740
23703 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23704 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23705 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23706 {AliasPatternCond::K_Reg, AArch64::XZR},
23707 // (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) - 3744
23708 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23709 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
23710 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23711 // (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) - 3747
23712 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23713 {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID},
23714 {AliasPatternCond::K_Feature, AArch64::FeatureNEON},
23715 // (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 3750
23716 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23717 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23718 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23719 {AliasPatternCond::K_Reg, AArch64::XZR},
23720 // (UQDECB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3754
23721 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23722 {AliasPatternCond::K_Ignore, 0},
23723 {AliasPatternCond::K_Imm, uint32_t(31)},
23724 {AliasPatternCond::K_Imm, uint32_t(1)},
23725 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23726 // (UQDECB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3759
23727 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23728 {AliasPatternCond::K_Ignore, 0},
23729 {AliasPatternCond::K_Ignore, 0},
23730 {AliasPatternCond::K_Imm, uint32_t(1)},
23731 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23732 // (UQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3764
23733 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23734 {AliasPatternCond::K_Ignore, 0},
23735 {AliasPatternCond::K_Imm, uint32_t(31)},
23736 {AliasPatternCond::K_Imm, uint32_t(1)},
23737 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23738 // (UQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3769
23739 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23740 {AliasPatternCond::K_Ignore, 0},
23741 {AliasPatternCond::K_Ignore, 0},
23742 {AliasPatternCond::K_Imm, uint32_t(1)},
23743 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23744 // (UQDECD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3774
23745 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23746 {AliasPatternCond::K_Ignore, 0},
23747 {AliasPatternCond::K_Imm, uint32_t(31)},
23748 {AliasPatternCond::K_Imm, uint32_t(1)},
23749 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23750 // (UQDECD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3779
23751 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23752 {AliasPatternCond::K_Ignore, 0},
23753 {AliasPatternCond::K_Ignore, 0},
23754 {AliasPatternCond::K_Imm, uint32_t(1)},
23755 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23756 // (UQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3784
23757 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23758 {AliasPatternCond::K_Ignore, 0},
23759 {AliasPatternCond::K_Imm, uint32_t(31)},
23760 {AliasPatternCond::K_Imm, uint32_t(1)},
23761 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23762 // (UQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3789
23763 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23764 {AliasPatternCond::K_Ignore, 0},
23765 {AliasPatternCond::K_Ignore, 0},
23766 {AliasPatternCond::K_Imm, uint32_t(1)},
23767 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23768 // (UQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3794
23769 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23770 {AliasPatternCond::K_Ignore, 0},
23771 {AliasPatternCond::K_Imm, uint32_t(31)},
23772 {AliasPatternCond::K_Imm, uint32_t(1)},
23773 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23774 // (UQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 3799
23775 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23776 {AliasPatternCond::K_Ignore, 0},
23777 {AliasPatternCond::K_Ignore, 0},
23778 {AliasPatternCond::K_Imm, uint32_t(1)},
23779 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23780 // (UQDECH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3804
23781 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23782 {AliasPatternCond::K_Ignore, 0},
23783 {AliasPatternCond::K_Imm, uint32_t(31)},
23784 {AliasPatternCond::K_Imm, uint32_t(1)},
23785 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23786 // (UQDECH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3809
23787 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23788 {AliasPatternCond::K_Ignore, 0},
23789 {AliasPatternCond::K_Ignore, 0},
23790 {AliasPatternCond::K_Imm, uint32_t(1)},
23791 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23792 // (UQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3814
23793 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23794 {AliasPatternCond::K_Ignore, 0},
23795 {AliasPatternCond::K_Imm, uint32_t(31)},
23796 {AliasPatternCond::K_Imm, uint32_t(1)},
23797 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23798 // (UQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3819
23799 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23800 {AliasPatternCond::K_Ignore, 0},
23801 {AliasPatternCond::K_Ignore, 0},
23802 {AliasPatternCond::K_Imm, uint32_t(1)},
23803 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23804 // (UQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3824
23805 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23806 {AliasPatternCond::K_Ignore, 0},
23807 {AliasPatternCond::K_Imm, uint32_t(31)},
23808 {AliasPatternCond::K_Imm, uint32_t(1)},
23809 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23810 // (UQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 3829
23811 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23812 {AliasPatternCond::K_Ignore, 0},
23813 {AliasPatternCond::K_Ignore, 0},
23814 {AliasPatternCond::K_Imm, uint32_t(1)},
23815 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23816 // (UQDECW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3834
23817 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23818 {AliasPatternCond::K_Ignore, 0},
23819 {AliasPatternCond::K_Imm, uint32_t(31)},
23820 {AliasPatternCond::K_Imm, uint32_t(1)},
23821 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23822 // (UQDECW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3839
23823 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23824 {AliasPatternCond::K_Ignore, 0},
23825 {AliasPatternCond::K_Ignore, 0},
23826 {AliasPatternCond::K_Imm, uint32_t(1)},
23827 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23828 // (UQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3844
23829 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23830 {AliasPatternCond::K_Ignore, 0},
23831 {AliasPatternCond::K_Imm, uint32_t(31)},
23832 {AliasPatternCond::K_Imm, uint32_t(1)},
23833 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23834 // (UQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3849
23835 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23836 {AliasPatternCond::K_Ignore, 0},
23837 {AliasPatternCond::K_Ignore, 0},
23838 {AliasPatternCond::K_Imm, uint32_t(1)},
23839 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23840 // (UQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3854
23841 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23842 {AliasPatternCond::K_Ignore, 0},
23843 {AliasPatternCond::K_Imm, uint32_t(31)},
23844 {AliasPatternCond::K_Imm, uint32_t(1)},
23845 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23846 // (UQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 3859
23847 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23848 {AliasPatternCond::K_Ignore, 0},
23849 {AliasPatternCond::K_Ignore, 0},
23850 {AliasPatternCond::K_Imm, uint32_t(1)},
23851 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23852 // (UQINCB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3864
23853 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23854 {AliasPatternCond::K_Ignore, 0},
23855 {AliasPatternCond::K_Imm, uint32_t(31)},
23856 {AliasPatternCond::K_Imm, uint32_t(1)},
23857 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23858 // (UQINCB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3869
23859 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23860 {AliasPatternCond::K_Ignore, 0},
23861 {AliasPatternCond::K_Ignore, 0},
23862 {AliasPatternCond::K_Imm, uint32_t(1)},
23863 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23864 // (UQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3874
23865 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23866 {AliasPatternCond::K_Ignore, 0},
23867 {AliasPatternCond::K_Imm, uint32_t(31)},
23868 {AliasPatternCond::K_Imm, uint32_t(1)},
23869 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23870 // (UQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3879
23871 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23872 {AliasPatternCond::K_Ignore, 0},
23873 {AliasPatternCond::K_Ignore, 0},
23874 {AliasPatternCond::K_Imm, uint32_t(1)},
23875 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23876 // (UQINCD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3884
23877 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23878 {AliasPatternCond::K_Ignore, 0},
23879 {AliasPatternCond::K_Imm, uint32_t(31)},
23880 {AliasPatternCond::K_Imm, uint32_t(1)},
23881 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23882 // (UQINCD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3889
23883 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23884 {AliasPatternCond::K_Ignore, 0},
23885 {AliasPatternCond::K_Ignore, 0},
23886 {AliasPatternCond::K_Imm, uint32_t(1)},
23887 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23888 // (UQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3894
23889 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23890 {AliasPatternCond::K_Ignore, 0},
23891 {AliasPatternCond::K_Imm, uint32_t(31)},
23892 {AliasPatternCond::K_Imm, uint32_t(1)},
23893 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23894 // (UQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3899
23895 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23896 {AliasPatternCond::K_Ignore, 0},
23897 {AliasPatternCond::K_Ignore, 0},
23898 {AliasPatternCond::K_Imm, uint32_t(1)},
23899 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23900 // (UQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3904
23901 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23902 {AliasPatternCond::K_Ignore, 0},
23903 {AliasPatternCond::K_Imm, uint32_t(31)},
23904 {AliasPatternCond::K_Imm, uint32_t(1)},
23905 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23906 // (UQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 3909
23907 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23908 {AliasPatternCond::K_Ignore, 0},
23909 {AliasPatternCond::K_Ignore, 0},
23910 {AliasPatternCond::K_Imm, uint32_t(1)},
23911 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23912 // (UQINCH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3914
23913 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23914 {AliasPatternCond::K_Ignore, 0},
23915 {AliasPatternCond::K_Imm, uint32_t(31)},
23916 {AliasPatternCond::K_Imm, uint32_t(1)},
23917 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23918 // (UQINCH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3919
23919 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23920 {AliasPatternCond::K_Ignore, 0},
23921 {AliasPatternCond::K_Ignore, 0},
23922 {AliasPatternCond::K_Imm, uint32_t(1)},
23923 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23924 // (UQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3924
23925 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23926 {AliasPatternCond::K_Ignore, 0},
23927 {AliasPatternCond::K_Imm, uint32_t(31)},
23928 {AliasPatternCond::K_Imm, uint32_t(1)},
23929 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23930 // (UQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3929
23931 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23932 {AliasPatternCond::K_Ignore, 0},
23933 {AliasPatternCond::K_Ignore, 0},
23934 {AliasPatternCond::K_Imm, uint32_t(1)},
23935 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23936 // (UQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3934
23937 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23938 {AliasPatternCond::K_Ignore, 0},
23939 {AliasPatternCond::K_Imm, uint32_t(31)},
23940 {AliasPatternCond::K_Imm, uint32_t(1)},
23941 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23942 // (UQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 3939
23943 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23944 {AliasPatternCond::K_Ignore, 0},
23945 {AliasPatternCond::K_Ignore, 0},
23946 {AliasPatternCond::K_Imm, uint32_t(1)},
23947 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23948 // (UQINCW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3944
23949 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23950 {AliasPatternCond::K_Ignore, 0},
23951 {AliasPatternCond::K_Imm, uint32_t(31)},
23952 {AliasPatternCond::K_Imm, uint32_t(1)},
23953 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23954 // (UQINCW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3949
23955 {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID},
23956 {AliasPatternCond::K_Ignore, 0},
23957 {AliasPatternCond::K_Ignore, 0},
23958 {AliasPatternCond::K_Imm, uint32_t(1)},
23959 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23960 // (UQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3954
23961 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23962 {AliasPatternCond::K_Ignore, 0},
23963 {AliasPatternCond::K_Imm, uint32_t(31)},
23964 {AliasPatternCond::K_Imm, uint32_t(1)},
23965 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23966 // (UQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3959
23967 {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID},
23968 {AliasPatternCond::K_Ignore, 0},
23969 {AliasPatternCond::K_Ignore, 0},
23970 {AliasPatternCond::K_Imm, uint32_t(1)},
23971 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23972 // (UQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3964
23973 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23974 {AliasPatternCond::K_Ignore, 0},
23975 {AliasPatternCond::K_Imm, uint32_t(31)},
23976 {AliasPatternCond::K_Imm, uint32_t(1)},
23977 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23978 // (UQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 3969
23979 {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID},
23980 {AliasPatternCond::K_Ignore, 0},
23981 {AliasPatternCond::K_Ignore, 0},
23982 {AliasPatternCond::K_Imm, uint32_t(1)},
23983 {AliasPatternCond::K_Feature, AArch64::FeatureSVE},
23984 // (XPACLRI) - 3974
23985 {AliasPatternCond::K_Feature, AArch64::FeaturePAuth},
23986 };
23987
23988 static const char AsmStrings[] =
23989 /* 0 */ "cmn $\x02, $\xFF\x03\x01\0"
23990 /* 13 */ "cmn $\x02, $\x03\0"
23991 /* 24 */ "cmn $\x02, $\x03$\xFF\x04\x02\0"
23992 /* 39 */ "adds $\x01, $\x02, $\x03\0"
23993 /* 55 */ "cmn $\x02, $\x03$\xFF\x04\x03\0"
23994 /* 70 */ "mov $\x01, $\x02\0"
23995 /* 81 */ "add $\x01, $\x02, $\x03\0"
23996 /* 96 */ "tst $\x02, $\xFF\x03\x04\0"
23997 /* 109 */ "tst $\x02, $\x03\0"
23998 /* 120 */ "tst $\x02, $\x03$\xFF\x04\x02\0"
23999 /* 135 */ "ands $\x01, $\x02, $\x03\0"
24000 /* 151 */ "tst $\x02, $\xFF\x03\x05\0"
24001 /* 164 */ "movs $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0"
24002 /* 188 */ "and $\x01, $\x02, $\x03\0"
24003 /* 203 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0"
24004 /* 226 */ "and $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0"
24005 /* 247 */ "and $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0"
24006 /* 268 */ "and $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0"
24007 /* 289 */ "autia1716\0"
24008 /* 299 */ "autiasp\0"
24009 /* 307 */ "autiaz\0"
24010 /* 314 */ "autib1716\0"
24011 /* 324 */ "autibsp\0"
24012 /* 332 */ "autibz\0"
24013 /* 339 */ "bics $\x01, $\x02, $\x03\0"
24014 /* 355 */ "bic $\x01, $\x02, $\x03\0"
24015 /* 370 */ "clrex\0"
24016 /* 376 */ "cntb $\x01\0"
24017 /* 384 */ "cntb $\x01, $\xFF\x02\x0E\0"
24018 /* 398 */ "cntd $\x01\0"
24019 /* 406 */ "cntd $\x01, $\xFF\x02\x0E\0"
24020 /* 420 */ "cnth $\x01\0"
24021 /* 428 */ "cnth $\x01, $\xFF\x02\x0E\0"
24022 /* 442 */ "cntw $\x01\0"
24023 /* 450 */ "cntw $\x01, $\xFF\x02\x0E\0"
24024 /* 464 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x0F\0"
24025 /* 487 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x11\0"
24026 /* 510 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x12\0"
24027 /* 533 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x13\0"
24028 /* 556 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04\0"
24029 /* 577 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04\0"
24030 /* 598 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04\0"
24031 /* 619 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04\0"
24032 /* 640 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x0F\0"
24033 /* 663 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/z, $\xFF\x03\x11\0"
24034 /* 686 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/z, $\xFF\x03\x12\0"
24035 /* 709 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/z, $\xFF\x03\x13\0"
24036 /* 732 */ "cset $\x01, $\xFF\x04\x14\0"
24037 /* 746 */ "cinc $\x01, $\x02, $\xFF\x04\x14\0"
24038 /* 764 */ "csetm $\x01, $\xFF\x04\x14\0"
24039 /* 779 */ "cinv $\x01, $\x02, $\xFF\x04\x14\0"
24040 /* 797 */ "cneg $\x01, $\x02, $\xFF\x04\x14\0"
24041 /* 815 */ "dcps1\0"
24042 /* 821 */ "dcps2\0"
24043 /* 827 */ "dcps3\0"
24044 /* 833 */ "decb $\x01\0"
24045 /* 841 */ "decb $\x01, $\xFF\x03\x0E\0"
24046 /* 855 */ "decd $\x01\0"
24047 /* 863 */ "decd $\x01, $\xFF\x03\x0E\0"
24048 /* 877 */ "decd $\xFF\x01\x10\0"
24049 /* 887 */ "decd $\xFF\x01\x10, $\xFF\x03\x0E\0"
24050 /* 903 */ "dech $\x01\0"
24051 /* 911 */ "dech $\x01, $\xFF\x03\x0E\0"
24052 /* 925 */ "dech $\xFF\x01\x09\0"
24053 /* 935 */ "dech $\xFF\x01\x09, $\xFF\x03\x0E\0"
24054 /* 951 */ "decw $\x01\0"
24055 /* 959 */ "decw $\x01, $\xFF\x03\x0E\0"
24056 /* 973 */ "decw $\xFF\x01\x0B\0"
24057 /* 983 */ "decw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
24058 /* 999 */ "ssbb\0"
24059 /* 1004 */ "pssbb\0"
24060 /* 1010 */ "mov $\xFF\x01\x09, $\xFF\x02\x15\0"
24061 /* 1025 */ "mov $\xFF\x01\x0B, $\xFF\x02\x16\0"
24062 /* 1040 */ "mov $\xFF\x01\x10, $\xFF\x02\x17\0"
24063 /* 1055 */ "dupm $\xFF\x01\x06, $\xFF\x02\x08\0"
24064 /* 1071 */ "dupm $\xFF\x01\x09, $\xFF\x02\x0A\0"
24065 /* 1087 */ "dupm $\xFF\x01\x0B, $\xFF\x02\x04\0"
24066 /* 1103 */ "mov $\xFF\x01\x06, $\xFF\x02\x0F\0"
24067 /* 1118 */ "mov $\xFF\x01\x10, $\xFF\x02\x11\0"
24068 /* 1133 */ "fmov $\xFF\x01\x10, #0.0\0"
24069 /* 1149 */ "mov $\xFF\x01\x09, $\xFF\x02\x12\0"
24070 /* 1164 */ "fmov $\xFF\x01\x09, #0.0\0"
24071 /* 1180 */ "mov $\xFF\x01\x0B, $\xFF\x02\x13\0"
24072 /* 1195 */ "fmov $\xFF\x01\x0B, #0.0\0"
24073 /* 1211 */ "mov $\xFF\x01\x06, $\x02\0"
24074 /* 1224 */ "mov $\xFF\x01\x10, $\x02\0"
24075 /* 1237 */ "mov $\xFF\x01\x09, $\x02\0"
24076 /* 1250 */ "mov $\xFF\x01\x0B, $\x02\0"
24077 /* 1263 */ "mov $\xFF\x01\x06, $\xFF\x02\x18\0"
24078 /* 1278 */ "mov $\xFF\x01\x06, $\xFF\x02\x06$\xFF\x03\x19\0"
24079 /* 1297 */ "mov $\xFF\x01\x10, $\xFF\x02\x1A\0"
24080 /* 1312 */ "mov $\xFF\x01\x10, $\xFF\x02\x10$\xFF\x03\x19\0"
24081 /* 1331 */ "mov $\xFF\x01\x09, $\xFF\x02\x1B\0"
24082 /* 1346 */ "mov $\xFF\x01\x09, $\xFF\x02\x09$\xFF\x03\x19\0"
24083 /* 1365 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1D\0"
24084 /* 1380 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1C$\xFF\x03\x19\0"
24085 /* 1399 */ "mov $\xFF\x01\x0B, $\xFF\x02\x1E\0"
24086 /* 1414 */ "mov $\xFF\x01\x0B, $\xFF\x02\x0B$\xFF\x03\x19\0"
24087 /* 1433 */ "eon $\x01, $\x02, $\x03\0"
24088 /* 1448 */ "nots $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0"
24089 /* 1472 */ "eor $\x01, $\x02, $\x03\0"
24090 /* 1487 */ "not $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0"
24091 /* 1510 */ "eor $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0"
24092 /* 1531 */ "eor $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0"
24093 /* 1552 */ "eor $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0"
24094 /* 1573 */ "ror $\x01, $\x02, $\x04\0"
24095 /* 1588 */ "fmov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x1F\0"
24096 /* 1612 */ "fmov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x1F\0"
24097 /* 1636 */ "fmov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x1F\0"
24098 /* 1660 */ "fmov $\xFF\x01\x10, $\xFF\x02\x1F\0"
24099 /* 1676 */ "fmov $\xFF\x01\x09, $\xFF\x02\x1F\0"
24100 /* 1692 */ "fmov $\xFF\x01\x0B, $\xFF\x02\x1F\0"
24101 /* 1708 */ "ld1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24102 /* 1734 */ "ld1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
24103 /* 1760 */ "ld1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24104 /* 1786 */ "ld1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24105 /* 1812 */ "ld1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
24106 /* 1838 */ "ld1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24107 /* 1865 */ "ld1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
24108 /* 1892 */ "ld1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24109 /* 1919 */ "ld1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
24110 /* 1946 */ "ld1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24111 /* 1973 */ "ld1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24112 /* 1999 */ "ld1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
24113 /* 2025 */ "ldff1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24114 /* 2053 */ "ldff1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
24115 /* 2081 */ "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24116 /* 2109 */ "ldff1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24117 /* 2137 */ "ldff1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
24118 /* 2165 */ "ldff1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24119 /* 2194 */ "ldff1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
24120 /* 2223 */ "ldff1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24121 /* 2252 */ "ldff1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
24122 /* 2281 */ "ldff1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24123 /* 2310 */ "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24124 /* 2338 */ "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
24125 /* 2366 */ "nop\0"
24126 /* 2370 */ "yield\0"
24127 /* 2376 */ "wfe\0"
24128 /* 2380 */ "wfi\0"
24129 /* 2384 */ "sev\0"
24130 /* 2388 */ "sevl\0"
24131 /* 2393 */ "dgh\0"
24132 /* 2397 */ "esb\0"
24133 /* 2401 */ "csdb\0"
24134 /* 2406 */ "bti\0"
24135 /* 2410 */ "bti $\xFF\x01\x22\0"
24136 /* 2419 */ "psb $\xFF\x01\x23\0"
24137 /* 2428 */ "incb $\x01\0"
24138 /* 2436 */ "incb $\x01, $\xFF\x03\x0E\0"
24139 /* 2450 */ "incd $\x01\0"
24140 /* 2458 */ "incd $\x01, $\xFF\x03\x0E\0"
24141 /* 2472 */ "incd $\xFF\x01\x10\0"
24142 /* 2482 */ "incd $\xFF\x01\x10, $\xFF\x03\x0E\0"
24143 /* 2498 */ "inch $\x01\0"
24144 /* 2506 */ "inch $\x01, $\xFF\x03\x0E\0"
24145 /* 2520 */ "inch $\xFF\x01\x09\0"
24146 /* 2530 */ "inch $\xFF\x01\x09, $\xFF\x03\x0E\0"
24147 /* 2546 */ "incw $\x01\0"
24148 /* 2554 */ "incw $\x01, $\xFF\x03\x0E\0"
24149 /* 2568 */ "incw $\xFF\x01\x0B\0"
24150 /* 2578 */ "incw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
24151 /* 2594 */ "mov.h $\xFF\x01\x0C$\xFF\x03\x19, $\x04\0"
24152 /* 2613 */ "mov.h $\xFF\x01\x0C$\xFF\x03\x19, $\xFF\x04\x0C$\xFF\x05\x19\0"
24153 /* 2638 */ "mov.s $\xFF\x01\x0C$\xFF\x03\x19, $\x04\0"
24154 /* 2657 */ "mov.s $\xFF\x01\x0C$\xFF\x03\x19, $\xFF\x04\x0C$\xFF\x05\x19\0"
24155 /* 2682 */ "mov.d $\xFF\x01\x0C$\xFF\x03\x19, $\x04\0"
24156 /* 2701 */ "mov.d $\xFF\x01\x0C$\xFF\x03\x19, $\xFF\x04\x0C$\xFF\x05\x19\0"
24157 /* 2726 */ "mov.b $\xFF\x01\x0C$\xFF\x03\x19, $\x04\0"
24158 /* 2745 */ "mov.b $\xFF\x01\x0C$\xFF\x03\x19, $\xFF\x04\x0C$\xFF\x05\x19\0"
24159 /* 2770 */ "irg $\x01, $\x02\0"
24160 /* 2781 */ "isb\0"
24161 /* 2785 */ "ld1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24162 /* 2809 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24163 /* 2833 */ "ld1b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
24164 /* 2857 */ "ld1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24165 /* 2881 */ "ld1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24166 /* 2905 */ "ld1 $\xFF\x02\x26, [$\x01], #64\0"
24167 /* 2925 */ "ld1 $\xFF\x02\x27, [$\x01], #32\0"
24168 /* 2945 */ "ld1 $\xFF\x02\x28, [$\x01], #64\0"
24169 /* 2965 */ "ld1 $\xFF\x02\x29, [$\x01], #32\0"
24170 /* 2985 */ "ld1 $\xFF\x02\x2A, [$\x01], #32\0"
24171 /* 3005 */ "ld1 $\xFF\x02\x2B, [$\x01], #64\0"
24172 /* 3025 */ "ld1 $\xFF\x02\x2C, [$\x01], #32\0"
24173 /* 3045 */ "ld1 $\xFF\x02\x2D, [$\x01], #64\0"
24174 /* 3065 */ "ld1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24175 /* 3089 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24176 /* 3113 */ "ld1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24177 /* 3137 */ "ld1 $\xFF\x02\x26, [$\x01], #16\0"
24178 /* 3157 */ "ld1 $\xFF\x02\x27, [$\x01], #8\0"
24179 /* 3176 */ "ld1 $\xFF\x02\x28, [$\x01], #16\0"
24180 /* 3196 */ "ld1 $\xFF\x02\x29, [$\x01], #8\0"
24181 /* 3215 */ "ld1 $\xFF\x02\x2A, [$\x01], #8\0"
24182 /* 3234 */ "ld1 $\xFF\x02\x2B, [$\x01], #16\0"
24183 /* 3254 */ "ld1 $\xFF\x02\x2C, [$\x01], #8\0"
24184 /* 3273 */ "ld1 $\xFF\x02\x2D, [$\x01], #16\0"
24185 /* 3293 */ "ld1rb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24186 /* 3318 */ "ld1rb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24187 /* 3343 */ "ld1rb $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
24188 /* 3368 */ "ld1rb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24189 /* 3393 */ "ld1rd $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24190 /* 3418 */ "ld1rh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24191 /* 3443 */ "ld1rh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24192 /* 3468 */ "ld1rh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24193 /* 3493 */ "ld1rob $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
24194 /* 3519 */ "ld1rod $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24195 /* 3545 */ "ld1roh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24196 /* 3571 */ "ld1row $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24197 /* 3597 */ "ld1rqb $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
24198 /* 3623 */ "ld1rqd $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24199 /* 3649 */ "ld1rqh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24200 /* 3675 */ "ld1rqw $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24201 /* 3701 */ "ld1rsb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24202 /* 3727 */ "ld1rsb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24203 /* 3753 */ "ld1rsb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24204 /* 3779 */ "ld1rsh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24205 /* 3805 */ "ld1rsh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24206 /* 3831 */ "ld1rsw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24207 /* 3857 */ "ld1rw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24208 /* 3882 */ "ld1rw $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24209 /* 3907 */ "ld1r $\xFF\x02\x26, [$\x01], #1\0"
24210 /* 3927 */ "ld1r $\xFF\x02\x27, [$\x01], #8\0"
24211 /* 3947 */ "ld1r $\xFF\x02\x28, [$\x01], #8\0"
24212 /* 3967 */ "ld1r $\xFF\x02\x29, [$\x01], #4\0"
24213 /* 3987 */ "ld1r $\xFF\x02\x2A, [$\x01], #2\0"
24214 /* 4007 */ "ld1r $\xFF\x02\x2B, [$\x01], #4\0"
24215 /* 4027 */ "ld1r $\xFF\x02\x2C, [$\x01], #1\0"
24216 /* 4047 */ "ld1r $\xFF\x02\x2D, [$\x01], #2\0"
24217 /* 4067 */ "ld1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24218 /* 4092 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24219 /* 4117 */ "ld1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24220 /* 4142 */ "ld1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24221 /* 4167 */ "ld1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24222 /* 4192 */ "ld1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24223 /* 4217 */ "ld1 $\xFF\x02\x26, [$\x01], #48\0"
24224 /* 4237 */ "ld1 $\xFF\x02\x27, [$\x01], #24\0"
24225 /* 4257 */ "ld1 $\xFF\x02\x28, [$\x01], #48\0"
24226 /* 4277 */ "ld1 $\xFF\x02\x29, [$\x01], #24\0"
24227 /* 4297 */ "ld1 $\xFF\x02\x2A, [$\x01], #24\0"
24228 /* 4317 */ "ld1 $\xFF\x02\x2B, [$\x01], #48\0"
24229 /* 4337 */ "ld1 $\xFF\x02\x2C, [$\x01], #24\0"
24230 /* 4357 */ "ld1 $\xFF\x02\x2D, [$\x01], #48\0"
24231 /* 4377 */ "ld1 $\xFF\x02\x26, [$\x01], #32\0"
24232 /* 4397 */ "ld1 $\xFF\x02\x27, [$\x01], #16\0"
24233 /* 4417 */ "ld1 $\xFF\x02\x28, [$\x01], #32\0"
24234 /* 4437 */ "ld1 $\xFF\x02\x29, [$\x01], #16\0"
24235 /* 4457 */ "ld1 $\xFF\x02\x2A, [$\x01], #16\0"
24236 /* 4477 */ "ld1 $\xFF\x02\x2B, [$\x01], #32\0"
24237 /* 4497 */ "ld1 $\xFF\x02\x2C, [$\x01], #16\0"
24238 /* 4517 */ "ld1 $\xFF\x02\x2D, [$\x01], #32\0"
24239 /* 4537 */ "ld1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24240 /* 4561 */ "ld1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24241 /* 4585 */ "ld1 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #2\0"
24242 /* 4608 */ "ld1 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #4\0"
24243 /* 4631 */ "ld1 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #8\0"
24244 /* 4654 */ "ld1 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #1\0"
24245 /* 4677 */ "ld2b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
24246 /* 4701 */ "ld2d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24247 /* 4725 */ "ld2h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24248 /* 4749 */ "ld2r $\xFF\x02\x26, [$\x01], #2\0"
24249 /* 4769 */ "ld2r $\xFF\x02\x27, [$\x01], #16\0"
24250 /* 4790 */ "ld2r $\xFF\x02\x28, [$\x01], #16\0"
24251 /* 4811 */ "ld2r $\xFF\x02\x29, [$\x01], #8\0"
24252 /* 4831 */ "ld2r $\xFF\x02\x2A, [$\x01], #4\0"
24253 /* 4851 */ "ld2r $\xFF\x02\x2B, [$\x01], #8\0"
24254 /* 4871 */ "ld2r $\xFF\x02\x2C, [$\x01], #2\0"
24255 /* 4891 */ "ld2r $\xFF\x02\x2D, [$\x01], #4\0"
24256 /* 4911 */ "ld2 $\xFF\x02\x26, [$\x01], #32\0"
24257 /* 4931 */ "ld2 $\xFF\x02\x28, [$\x01], #32\0"
24258 /* 4951 */ "ld2 $\xFF\x02\x29, [$\x01], #16\0"
24259 /* 4971 */ "ld2 $\xFF\x02\x2A, [$\x01], #16\0"
24260 /* 4991 */ "ld2 $\xFF\x02\x2B, [$\x01], #32\0"
24261 /* 5011 */ "ld2 $\xFF\x02\x2C, [$\x01], #16\0"
24262 /* 5031 */ "ld2 $\xFF\x02\x2D, [$\x01], #32\0"
24263 /* 5051 */ "ld2w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24264 /* 5075 */ "ld2 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #4\0"
24265 /* 5098 */ "ld2 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #8\0"
24266 /* 5121 */ "ld2 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #16\0"
24267 /* 5145 */ "ld2 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #2\0"
24268 /* 5168 */ "ld3b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
24269 /* 5192 */ "ld3d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24270 /* 5216 */ "ld3h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24271 /* 5240 */ "ld3r $\xFF\x02\x26, [$\x01], #3\0"
24272 /* 5260 */ "ld3r $\xFF\x02\x27, [$\x01], #24\0"
24273 /* 5281 */ "ld3r $\xFF\x02\x28, [$\x01], #24\0"
24274 /* 5302 */ "ld3r $\xFF\x02\x29, [$\x01], #12\0"
24275 /* 5323 */ "ld3r $\xFF\x02\x2A, [$\x01], #6\0"
24276 /* 5343 */ "ld3r $\xFF\x02\x2B, [$\x01], #12\0"
24277 /* 5364 */ "ld3r $\xFF\x02\x2C, [$\x01], #3\0"
24278 /* 5384 */ "ld3r $\xFF\x02\x2D, [$\x01], #6\0"
24279 /* 5404 */ "ld3 $\xFF\x02\x26, [$\x01], #48\0"
24280 /* 5424 */ "ld3 $\xFF\x02\x28, [$\x01], #48\0"
24281 /* 5444 */ "ld3 $\xFF\x02\x29, [$\x01], #24\0"
24282 /* 5464 */ "ld3 $\xFF\x02\x2A, [$\x01], #24\0"
24283 /* 5484 */ "ld3 $\xFF\x02\x2B, [$\x01], #48\0"
24284 /* 5504 */ "ld3 $\xFF\x02\x2C, [$\x01], #24\0"
24285 /* 5524 */ "ld3 $\xFF\x02\x2D, [$\x01], #48\0"
24286 /* 5544 */ "ld3w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24287 /* 5568 */ "ld3 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #6\0"
24288 /* 5591 */ "ld3 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #12\0"
24289 /* 5615 */ "ld3 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #24\0"
24290 /* 5639 */ "ld3 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #3\0"
24291 /* 5662 */ "ld4b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
24292 /* 5686 */ "ld4d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24293 /* 5710 */ "ld4 $\xFF\x02\x26, [$\x01], #64\0"
24294 /* 5730 */ "ld4 $\xFF\x02\x28, [$\x01], #64\0"
24295 /* 5750 */ "ld4 $\xFF\x02\x29, [$\x01], #32\0"
24296 /* 5770 */ "ld4 $\xFF\x02\x2A, [$\x01], #32\0"
24297 /* 5790 */ "ld4 $\xFF\x02\x2B, [$\x01], #64\0"
24298 /* 5810 */ "ld4 $\xFF\x02\x2C, [$\x01], #32\0"
24299 /* 5830 */ "ld4 $\xFF\x02\x2D, [$\x01], #64\0"
24300 /* 5850 */ "ld4h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24301 /* 5874 */ "ld4r $\xFF\x02\x26, [$\x01], #4\0"
24302 /* 5894 */ "ld4r $\xFF\x02\x27, [$\x01], #32\0"
24303 /* 5915 */ "ld4r $\xFF\x02\x28, [$\x01], #32\0"
24304 /* 5936 */ "ld4r $\xFF\x02\x29, [$\x01], #16\0"
24305 /* 5957 */ "ld4r $\xFF\x02\x2A, [$\x01], #8\0"
24306 /* 5977 */ "ld4r $\xFF\x02\x2B, [$\x01], #16\0"
24307 /* 5998 */ "ld4r $\xFF\x02\x2C, [$\x01], #4\0"
24308 /* 6018 */ "ld4r $\xFF\x02\x2D, [$\x01], #8\0"
24309 /* 6038 */ "ld4w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24310 /* 6062 */ "ld4 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #8\0"
24311 /* 6085 */ "ld4 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #16\0"
24312 /* 6109 */ "ld4 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #32\0"
24313 /* 6133 */ "ld4 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #4\0"
24314 /* 6156 */ "staddb $\x02, [$\x03]\0"
24315 /* 6172 */ "staddh $\x02, [$\x03]\0"
24316 /* 6188 */ "staddlb $\x02, [$\x03]\0"
24317 /* 6205 */ "staddlh $\x02, [$\x03]\0"
24318 /* 6222 */ "staddl $\x02, [$\x03]\0"
24319 /* 6238 */ "stadd $\x02, [$\x03]\0"
24320 /* 6253 */ "ldapurb $\x01, [$\x02]\0"
24321 /* 6270 */ "ldapurh $\x01, [$\x02]\0"
24322 /* 6287 */ "ldapursb $\x01, [$\x02]\0"
24323 /* 6305 */ "ldapursh $\x01, [$\x02]\0"
24324 /* 6323 */ "ldapursw $\x01, [$\x02]\0"
24325 /* 6341 */ "ldapur $\x01, [$\x02]\0"
24326 /* 6357 */ "stclrb $\x02, [$\x03]\0"
24327 /* 6373 */ "stclrh $\x02, [$\x03]\0"
24328 /* 6389 */ "stclrlb $\x02, [$\x03]\0"
24329 /* 6406 */ "stclrlh $\x02, [$\x03]\0"
24330 /* 6423 */ "stclrl $\x02, [$\x03]\0"
24331 /* 6439 */ "stclr $\x02, [$\x03]\0"
24332 /* 6454 */ "steorb $\x02, [$\x03]\0"
24333 /* 6470 */ "steorh $\x02, [$\x03]\0"
24334 /* 6486 */ "steorlb $\x02, [$\x03]\0"
24335 /* 6503 */ "steorlh $\x02, [$\x03]\0"
24336 /* 6520 */ "steorl $\x02, [$\x03]\0"
24337 /* 6536 */ "steor $\x02, [$\x03]\0"
24338 /* 6551 */ "ldff1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24339 /* 6577 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24340 /* 6603 */ "ldff1b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
24341 /* 6629 */ "ldff1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24342 /* 6655 */ "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24343 /* 6681 */ "ldff1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24344 /* 6707 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24345 /* 6733 */ "ldff1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24346 /* 6759 */ "ldff1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24347 /* 6786 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24348 /* 6813 */ "ldff1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24349 /* 6840 */ "ldff1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24350 /* 6867 */ "ldff1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24351 /* 6894 */ "ldff1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24352 /* 6921 */ "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24353 /* 6947 */ "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24354 /* 6973 */ "ldg $\x01, [$\x03]\0"
24355 /* 6986 */ "ldnf1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24356 /* 7012 */ "ldnf1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24357 /* 7038 */ "ldnf1b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
24358 /* 7064 */ "ldnf1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24359 /* 7090 */ "ldnf1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24360 /* 7116 */ "ldnf1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24361 /* 7142 */ "ldnf1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24362 /* 7168 */ "ldnf1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24363 /* 7194 */ "ldnf1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24364 /* 7221 */ "ldnf1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24365 /* 7248 */ "ldnf1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24366 /* 7275 */ "ldnf1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24367 /* 7302 */ "ldnf1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24368 /* 7329 */ "ldnf1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24369 /* 7356 */ "ldnf1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24370 /* 7382 */ "ldnf1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24371 /* 7408 */ "ldnp $\x01, $\x02, [$\x03]\0"
24372 /* 7426 */ "ldnt1b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0"
24373 /* 7452 */ "ldnt1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24374 /* 7480 */ "ldnt1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
24375 /* 7508 */ "ldnt1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
24376 /* 7534 */ "ldnt1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24377 /* 7562 */ "ldnt1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0"
24378 /* 7588 */ "ldnt1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24379 /* 7616 */ "ldnt1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
24380 /* 7644 */ "ldnt1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24381 /* 7673 */ "ldnt1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
24382 /* 7702 */ "ldnt1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24383 /* 7731 */ "ldnt1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
24384 /* 7760 */ "ldnt1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24385 /* 7789 */ "ldnt1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0"
24386 /* 7815 */ "ldnt1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0"
24387 /* 7843 */ "ldnt1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0"
24388 /* 7871 */ "ldp $\x01, $\x02, [$\x03]\0"
24389 /* 7888 */ "ldpsw $\x01, $\x02, [$\x03]\0"
24390 /* 7907 */ "ldraa $\x01, [$\x02]\0"
24391 /* 7922 */ "ldrab $\x01, [$\x02]\0"
24392 /* 7937 */ "ldrb $\x01, [$\x02, $\x03]\0"
24393 /* 7955 */ "ldrb $\x01, [$\x02]\0"
24394 /* 7969 */ "ldr $\x01, [$\x02, $\x03]\0"
24395 /* 7986 */ "ldr $\x01, [$\x02]\0"
24396 /* 7999 */ "ldrh $\x01, [$\x02, $\x03]\0"
24397 /* 8017 */ "ldrh $\x01, [$\x02]\0"
24398 /* 8031 */ "ldrsb $\x01, [$\x02, $\x03]\0"
24399 /* 8050 */ "ldrsb $\x01, [$\x02]\0"
24400 /* 8065 */ "ldrsh $\x01, [$\x02, $\x03]\0"
24401 /* 8084 */ "ldrsh $\x01, [$\x02]\0"
24402 /* 8099 */ "ldrsw $\x01, [$\x02, $\x03]\0"
24403 /* 8118 */ "ldrsw $\x01, [$\x02]\0"
24404 /* 8133 */ "ldr $\xFF\x01\x07, [$\x02]\0"
24405 /* 8148 */ "stsetb $\x02, [$\x03]\0"
24406 /* 8164 */ "stseth $\x02, [$\x03]\0"
24407 /* 8180 */ "stsetlb $\x02, [$\x03]\0"
24408 /* 8197 */ "stsetlh $\x02, [$\x03]\0"
24409 /* 8214 */ "stsetl $\x02, [$\x03]\0"
24410 /* 8230 */ "stset $\x02, [$\x03]\0"
24411 /* 8245 */ "stsmaxb $\x02, [$\x03]\0"
24412 /* 8262 */ "stsmaxh $\x02, [$\x03]\0"
24413 /* 8279 */ "stsmaxlb $\x02, [$\x03]\0"
24414 /* 8297 */ "stsmaxlh $\x02, [$\x03]\0"
24415 /* 8315 */ "stsmaxl $\x02, [$\x03]\0"
24416 /* 8332 */ "stsmax $\x02, [$\x03]\0"
24417 /* 8348 */ "stsminb $\x02, [$\x03]\0"
24418 /* 8365 */ "stsminh $\x02, [$\x03]\0"
24419 /* 8382 */ "stsminlb $\x02, [$\x03]\0"
24420 /* 8400 */ "stsminlh $\x02, [$\x03]\0"
24421 /* 8418 */ "stsminl $\x02, [$\x03]\0"
24422 /* 8435 */ "stsmin $\x02, [$\x03]\0"
24423 /* 8451 */ "ldtrb $\x01, [$\x02]\0"
24424 /* 8466 */ "ldtrh $\x01, [$\x02]\0"
24425 /* 8481 */ "ldtrsb $\x01, [$\x02]\0"
24426 /* 8497 */ "ldtrsh $\x01, [$\x02]\0"
24427 /* 8513 */ "ldtrsw $\x01, [$\x02]\0"
24428 /* 8529 */ "ldtr $\x01, [$\x02]\0"
24429 /* 8543 */ "stumaxb $\x02, [$\x03]\0"
24430 /* 8560 */ "stumaxh $\x02, [$\x03]\0"
24431 /* 8577 */ "stumaxlb $\x02, [$\x03]\0"
24432 /* 8595 */ "stumaxlh $\x02, [$\x03]\0"
24433 /* 8613 */ "stumaxl $\x02, [$\x03]\0"
24434 /* 8630 */ "stumax $\x02, [$\x03]\0"
24435 /* 8646 */ "stuminb $\x02, [$\x03]\0"
24436 /* 8663 */ "stuminh $\x02, [$\x03]\0"
24437 /* 8680 */ "stuminlb $\x02, [$\x03]\0"
24438 /* 8698 */ "stuminlh $\x02, [$\x03]\0"
24439 /* 8716 */ "stuminl $\x02, [$\x03]\0"
24440 /* 8733 */ "stumin $\x02, [$\x03]\0"
24441 /* 8749 */ "ldurb $\x01, [$\x02]\0"
24442 /* 8764 */ "ldur $\x01, [$\x02]\0"
24443 /* 8778 */ "ldurh $\x01, [$\x02]\0"
24444 /* 8793 */ "ldursb $\x01, [$\x02]\0"
24445 /* 8809 */ "ldursh $\x01, [$\x02]\0"
24446 /* 8825 */ "ldursw $\x01, [$\x02]\0"
24447 /* 8841 */ "mul $\x01, $\x02, $\x03\0"
24448 /* 8856 */ "mneg $\x01, $\x02, $\x03\0"
24449 /* 8872 */ "mvn.16b $\xFF\x01\x0C, $\xFF\x02\x0C\0"
24450 /* 8891 */ "mvn.8b $\xFF\x01\x0C, $\xFF\x02\x0C\0"
24451 /* 8909 */ "mvn $\x01, $\x03\0"
24452 /* 8920 */ "mvn $\x01, $\x03$\xFF\x04\x02\0"
24453 /* 8935 */ "orn $\x01, $\x02, $\x03\0"
24454 /* 8950 */ "movs $\xFF\x01\x06, $\xFF\x02\x06\0"
24455 /* 8966 */ "mov $\x01, $\x03\0"
24456 /* 8977 */ "orr $\x01, $\x02, $\x03\0"
24457 /* 8992 */ "mov $\xFF\x01\x06, $\xFF\x02\x06\0"
24458 /* 9007 */ "orr $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0"
24459 /* 9028 */ "orr $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0"
24460 /* 9049 */ "orr $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0"
24461 /* 9070 */ "mov $\xFF\x01\x10, $\xFF\x02\x10\0"
24462 /* 9085 */ "mov.16b $\xFF\x01\x0C, $\xFF\x02\x0C\0"
24463 /* 9104 */ "mov.8b $\xFF\x01\x0C, $\xFF\x02\x0C\0"
24464 /* 9122 */ "pacia1716\0"
24465 /* 9132 */ "paciasp\0"
24466 /* 9140 */ "paciaz\0"
24467 /* 9147 */ "pacib1716\0"
24468 /* 9157 */ "pacibsp\0"
24469 /* 9165 */ "pacibz\0"
24470 /* 9172 */ "prfb $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
24471 /* 9196 */ "prfb $\xFF\x01\x33, $\xFF\x02\x07, [$\x03]\0"
24472 /* 9218 */ "prfb $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
24473 /* 9242 */ "prfd $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
24474 /* 9266 */ "prfd $\xFF\x01\x33, $\xFF\x02\x07, [$\x03]\0"
24475 /* 9288 */ "prfd $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
24476 /* 9312 */ "prfh $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
24477 /* 9336 */ "prfh $\xFF\x01\x33, $\xFF\x02\x07, [$\x03]\0"
24478 /* 9358 */ "prfh $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
24479 /* 9382 */ "prfm $\xFF\x01\x34, [$\x02, $\x03]\0"
24480 /* 9402 */ "prfm $\xFF\x01\x34, [$\x02]\0"
24481 /* 9418 */ "prfum $\xFF\x01\x34, [$\x02]\0"
24482 /* 9435 */ "prfw $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
24483 /* 9459 */ "prfw $\xFF\x01\x33, $\xFF\x02\x07, [$\x03]\0"
24484 /* 9481 */ "prfw $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
24485 /* 9505 */ "ptrues $\xFF\x01\x06\0"
24486 /* 9517 */ "ptrues $\xFF\x01\x10\0"
24487 /* 9529 */ "ptrues $\xFF\x01\x09\0"
24488 /* 9541 */ "ptrues $\xFF\x01\x0B\0"
24489 /* 9553 */ "ptrue $\xFF\x01\x06\0"
24490 /* 9564 */ "ptrue $\xFF\x01\x10\0"
24491 /* 9575 */ "ptrue $\xFF\x01\x09\0"
24492 /* 9586 */ "ptrue $\xFF\x01\x0B\0"
24493 /* 9597 */ "ret\0"
24494 /* 9601 */ "ngcs $\x01, $\x03\0"
24495 /* 9613 */ "ngc $\x01, $\x03\0"
24496 /* 9624 */ "asr $\x01, $\x02, $\x03\0"
24497 /* 9639 */ "sxtb $\x01, $\x02\0"
24498 /* 9651 */ "sxth $\x01, $\x02\0"
24499 /* 9663 */ "sxtw $\x01, $\x02\0"
24500 /* 9675 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06\0"
24501 /* 9698 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x10\0"
24502 /* 9721 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x09\0"
24503 /* 9744 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x0B\0"
24504 /* 9767 */ "smull $\x01, $\x02, $\x03\0"
24505 /* 9784 */ "smnegl $\x01, $\x02, $\x03\0"
24506 /* 9802 */ "sqdecb $\x01\0"
24507 /* 9812 */ "sqdecb $\x01, $\xFF\x03\x0E\0"
24508 /* 9828 */ "sqdecb $\x01, $\xFF\x02\x35\0"
24509 /* 9844 */ "sqdecb $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
24510 /* 9866 */ "sqdecd $\x01\0"
24511 /* 9876 */ "sqdecd $\x01, $\xFF\x03\x0E\0"
24512 /* 9892 */ "sqdecd $\x01, $\xFF\x02\x35\0"
24513 /* 9908 */ "sqdecd $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
24514 /* 9930 */ "sqdecd $\xFF\x01\x10\0"
24515 /* 9942 */ "sqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0"
24516 /* 9960 */ "sqdech $\x01\0"
24517 /* 9970 */ "sqdech $\x01, $\xFF\x03\x0E\0"
24518 /* 9986 */ "sqdech $\x01, $\xFF\x02\x35\0"
24519 /* 10002 */ "sqdech $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
24520 /* 10024 */ "sqdech $\xFF\x01\x09\0"
24521 /* 10036 */ "sqdech $\xFF\x01\x09, $\xFF\x03\x0E\0"
24522 /* 10054 */ "sqdecw $\x01\0"
24523 /* 10064 */ "sqdecw $\x01, $\xFF\x03\x0E\0"
24524 /* 10080 */ "sqdecw $\x01, $\xFF\x02\x35\0"
24525 /* 10096 */ "sqdecw $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
24526 /* 10118 */ "sqdecw $\xFF\x01\x0B\0"
24527 /* 10130 */ "sqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
24528 /* 10148 */ "sqincb $\x01\0"
24529 /* 10158 */ "sqincb $\x01, $\xFF\x03\x0E\0"
24530 /* 10174 */ "sqincb $\x01, $\xFF\x02\x35\0"
24531 /* 10190 */ "sqincb $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
24532 /* 10212 */ "sqincd $\x01\0"
24533 /* 10222 */ "sqincd $\x01, $\xFF\x03\x0E\0"
24534 /* 10238 */ "sqincd $\x01, $\xFF\x02\x35\0"
24535 /* 10254 */ "sqincd $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
24536 /* 10276 */ "sqincd $\xFF\x01\x10\0"
24537 /* 10288 */ "sqincd $\xFF\x01\x10, $\xFF\x03\x0E\0"
24538 /* 10306 */ "sqinch $\x01\0"
24539 /* 10316 */ "sqinch $\x01, $\xFF\x03\x0E\0"
24540 /* 10332 */ "sqinch $\x01, $\xFF\x02\x35\0"
24541 /* 10348 */ "sqinch $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
24542 /* 10370 */ "sqinch $\xFF\x01\x09\0"
24543 /* 10382 */ "sqinch $\xFF\x01\x09, $\xFF\x03\x0E\0"
24544 /* 10400 */ "sqincw $\x01\0"
24545 /* 10410 */ "sqincw $\x01, $\xFF\x03\x0E\0"
24546 /* 10426 */ "sqincw $\x01, $\xFF\x02\x35\0"
24547 /* 10442 */ "sqincw $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0"
24548 /* 10464 */ "sqincw $\xFF\x01\x0B\0"
24549 /* 10476 */ "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
24550 /* 10494 */ "st1b $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
24551 /* 10518 */ "st1b $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
24552 /* 10542 */ "st1d $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
24553 /* 10566 */ "st1h $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
24554 /* 10590 */ "st1h $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
24555 /* 10614 */ "st1w $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
24556 /* 10638 */ "st1w $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
24557 /* 10662 */ "st1b $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
24558 /* 10684 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
24559 /* 10706 */ "st1b $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0"
24560 /* 10728 */ "st1b $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0"
24561 /* 10750 */ "st1d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
24562 /* 10772 */ "st1 $\xFF\x02\x26, [$\x01], #64\0"
24563 /* 10792 */ "st1 $\xFF\x02\x27, [$\x01], #32\0"
24564 /* 10812 */ "st1 $\xFF\x02\x28, [$\x01], #64\0"
24565 /* 10832 */ "st1 $\xFF\x02\x29, [$\x01], #32\0"
24566 /* 10852 */ "st1 $\xFF\x02\x2A, [$\x01], #32\0"
24567 /* 10872 */ "st1 $\xFF\x02\x2B, [$\x01], #64\0"
24568 /* 10892 */ "st1 $\xFF\x02\x2C, [$\x01], #32\0"
24569 /* 10912 */ "st1 $\xFF\x02\x2D, [$\x01], #64\0"
24570 /* 10932 */ "st1h $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
24571 /* 10954 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
24572 /* 10976 */ "st1h $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0"
24573 /* 10998 */ "st1 $\xFF\x02\x26, [$\x01], #16\0"
24574 /* 11018 */ "st1 $\xFF\x02\x27, [$\x01], #8\0"
24575 /* 11037 */ "st1 $\xFF\x02\x28, [$\x01], #16\0"
24576 /* 11057 */ "st1 $\xFF\x02\x29, [$\x01], #8\0"
24577 /* 11076 */ "st1 $\xFF\x02\x2A, [$\x01], #8\0"
24578 /* 11095 */ "st1 $\xFF\x02\x2B, [$\x01], #16\0"
24579 /* 11115 */ "st1 $\xFF\x02\x2C, [$\x01], #8\0"
24580 /* 11134 */ "st1 $\xFF\x02\x2D, [$\x01], #16\0"
24581 /* 11154 */ "st1 $\xFF\x02\x26, [$\x01], #48\0"
24582 /* 11174 */ "st1 $\xFF\x02\x27, [$\x01], #24\0"
24583 /* 11194 */ "st1 $\xFF\x02\x28, [$\x01], #48\0"
24584 /* 11214 */ "st1 $\xFF\x02\x29, [$\x01], #24\0"
24585 /* 11234 */ "st1 $\xFF\x02\x2A, [$\x01], #24\0"
24586 /* 11254 */ "st1 $\xFF\x02\x2B, [$\x01], #48\0"
24587 /* 11274 */ "st1 $\xFF\x02\x2C, [$\x01], #24\0"
24588 /* 11294 */ "st1 $\xFF\x02\x2D, [$\x01], #48\0"
24589 /* 11314 */ "st1 $\xFF\x02\x26, [$\x01], #32\0"
24590 /* 11334 */ "st1 $\xFF\x02\x27, [$\x01], #16\0"
24591 /* 11354 */ "st1 $\xFF\x02\x28, [$\x01], #32\0"
24592 /* 11374 */ "st1 $\xFF\x02\x29, [$\x01], #16\0"
24593 /* 11394 */ "st1 $\xFF\x02\x2A, [$\x01], #16\0"
24594 /* 11414 */ "st1 $\xFF\x02\x2B, [$\x01], #32\0"
24595 /* 11434 */ "st1 $\xFF\x02\x2C, [$\x01], #16\0"
24596 /* 11454 */ "st1 $\xFF\x02\x2D, [$\x01], #32\0"
24597 /* 11474 */ "st1w $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
24598 /* 11496 */ "st1w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0"
24599 /* 11518 */ "st1 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #2\0"
24600 /* 11541 */ "st1 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #4\0"
24601 /* 11564 */ "st1 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #8\0"
24602 /* 11587 */ "st1 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #1\0"
24603 /* 11610 */ "st2b $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0"
24604 /* 11632 */ "st2d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
24605 /* 11654 */ "st2g $\x01, [$\x02]\0"
24606 /* 11668 */ "st2h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
24607 /* 11690 */ "st2 $\xFF\x02\x26, [$\x01], #32\0"
24608 /* 11710 */ "st2 $\xFF\x02\x28, [$\x01], #32\0"
24609 /* 11730 */ "st2 $\xFF\x02\x29, [$\x01], #16\0"
24610 /* 11750 */ "st2 $\xFF\x02\x2A, [$\x01], #16\0"
24611 /* 11770 */ "st2 $\xFF\x02\x2B, [$\x01], #32\0"
24612 /* 11790 */ "st2 $\xFF\x02\x2C, [$\x01], #16\0"
24613 /* 11810 */ "st2 $\xFF\x02\x2D, [$\x01], #32\0"
24614 /* 11830 */ "st2w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0"
24615 /* 11852 */ "st2 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #4\0"
24616 /* 11875 */ "st2 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #8\0"
24617 /* 11898 */ "st2 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #16\0"
24618 /* 11922 */ "st2 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #2\0"
24619 /* 11945 */ "st3b $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0"
24620 /* 11967 */ "st3d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
24621 /* 11989 */ "st3h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
24622 /* 12011 */ "st3 $\xFF\x02\x26, [$\x01], #48\0"
24623 /* 12031 */ "st3 $\xFF\x02\x28, [$\x01], #48\0"
24624 /* 12051 */ "st3 $\xFF\x02\x29, [$\x01], #24\0"
24625 /* 12071 */ "st3 $\xFF\x02\x2A, [$\x01], #24\0"
24626 /* 12091 */ "st3 $\xFF\x02\x2B, [$\x01], #48\0"
24627 /* 12111 */ "st3 $\xFF\x02\x2C, [$\x01], #24\0"
24628 /* 12131 */ "st3 $\xFF\x02\x2D, [$\x01], #48\0"
24629 /* 12151 */ "st3w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0"
24630 /* 12173 */ "st3 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #6\0"
24631 /* 12196 */ "st3 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #12\0"
24632 /* 12220 */ "st3 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #24\0"
24633 /* 12244 */ "st3 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #3\0"
24634 /* 12267 */ "st4b $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0"
24635 /* 12289 */ "st4d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
24636 /* 12311 */ "st4 $\xFF\x02\x26, [$\x01], #64\0"
24637 /* 12331 */ "st4 $\xFF\x02\x28, [$\x01], #64\0"
24638 /* 12351 */ "st4 $\xFF\x02\x29, [$\x01], #32\0"
24639 /* 12371 */ "st4 $\xFF\x02\x2A, [$\x01], #32\0"
24640 /* 12391 */ "st4 $\xFF\x02\x2B, [$\x01], #64\0"
24641 /* 12411 */ "st4 $\xFF\x02\x2C, [$\x01], #32\0"
24642 /* 12431 */ "st4 $\xFF\x02\x2D, [$\x01], #64\0"
24643 /* 12451 */ "st4h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
24644 /* 12473 */ "st4w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0"
24645 /* 12495 */ "st4 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #8\0"
24646 /* 12518 */ "st4 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #16\0"
24647 /* 12542 */ "st4 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #32\0"
24648 /* 12566 */ "st4 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #4\0"
24649 /* 12589 */ "stg $\x01, [$\x02]\0"
24650 /* 12602 */ "stgp $\x01, $\x02, [$\x03]\0"
24651 /* 12620 */ "stlurb $\x01, [$\x02]\0"
24652 /* 12636 */ "stlurh $\x01, [$\x02]\0"
24653 /* 12652 */ "stlur $\x01, [$\x02]\0"
24654 /* 12667 */ "stnp $\x01, $\x02, [$\x03]\0"
24655 /* 12685 */ "stnt1b $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0"
24656 /* 12709 */ "stnt1b $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
24657 /* 12735 */ "stnt1b $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
24658 /* 12761 */ "stnt1d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0"
24659 /* 12785 */ "stnt1d $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
24660 /* 12811 */ "stnt1h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
24661 /* 12835 */ "stnt1h $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
24662 /* 12861 */ "stnt1h $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
24663 /* 12887 */ "stnt1w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0"
24664 /* 12911 */ "stnt1w $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
24665 /* 12937 */ "stnt1w $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
24666 /* 12963 */ "stp $\x01, $\x02, [$\x03]\0"
24667 /* 12980 */ "strb $\x01, [$\x02, $\x03]\0"
24668 /* 12998 */ "strb $\x01, [$\x02]\0"
24669 /* 13012 */ "str $\x01, [$\x02, $\x03]\0"
24670 /* 13029 */ "str $\x01, [$\x02]\0"
24671 /* 13042 */ "strh $\x01, [$\x02, $\x03]\0"
24672 /* 13060 */ "strh $\x01, [$\x02]\0"
24673 /* 13074 */ "str $\xFF\x01\x07, [$\x02]\0"
24674 /* 13089 */ "sttrb $\x01, [$\x02]\0"
24675 /* 13104 */ "sttrh $\x01, [$\x02]\0"
24676 /* 13119 */ "sttr $\x01, [$\x02]\0"
24677 /* 13133 */ "sturb $\x01, [$\x02]\0"
24678 /* 13148 */ "stur $\x01, [$\x02]\0"
24679 /* 13162 */ "sturh $\x01, [$\x02]\0"
24680 /* 13177 */ "stz2g $\x01, [$\x02]\0"
24681 /* 13192 */ "stzg $\x01, [$\x02]\0"
24682 /* 13206 */ "cmp $\x02, $\xFF\x03\x01\0"
24683 /* 13219 */ "cmp $\x02, $\x03\0"
24684 /* 13230 */ "cmp $\x02, $\x03$\xFF\x04\x02\0"
24685 /* 13245 */ "negs $\x01, $\x03\0"
24686 /* 13257 */ "negs $\x01, $\x03$\xFF\x04\x02\0"
24687 /* 13273 */ "subs $\x01, $\x02, $\x03\0"
24688 /* 13289 */ "cmp $\x02, $\x03$\xFF\x04\x03\0"
24689 /* 13304 */ "neg $\x01, $\x03\0"
24690 /* 13315 */ "neg $\x01, $\x03$\xFF\x04\x02\0"
24691 /* 13330 */ "sub $\x01, $\x02, $\x03\0"
24692 /* 13345 */ "sys $\x01, $\xFF\x02\x36, $\xFF\x03\x36, $\x04\0"
24693 /* 13368 */ "lsr $\x01, $\x02, $\x03\0"
24694 /* 13383 */ "uxtb $\x01, $\x02\0"
24695 /* 13395 */ "uxth $\x01, $\x02\0"
24696 /* 13407 */ "uxtw $\x01, $\x02\0"
24697 /* 13419 */ "umull $\x01, $\x02, $\x03\0"
24698 /* 13436 */ "mov.s $\x01, $\xFF\x02\x0C$\xFF\x03\x19\0"
24699 /* 13455 */ "mov.d $\x01, $\xFF\x02\x0C$\xFF\x03\x19\0"
24700 /* 13474 */ "umnegl $\x01, $\x02, $\x03\0"
24701 /* 13492 */ "uqdecb $\x01\0"
24702 /* 13502 */ "uqdecb $\x01, $\xFF\x03\x0E\0"
24703 /* 13518 */ "uqdecd $\x01\0"
24704 /* 13528 */ "uqdecd $\x01, $\xFF\x03\x0E\0"
24705 /* 13544 */ "uqdecd $\xFF\x01\x10\0"
24706 /* 13556 */ "uqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0"
24707 /* 13574 */ "uqdech $\x01\0"
24708 /* 13584 */ "uqdech $\x01, $\xFF\x03\x0E\0"
24709 /* 13600 */ "uqdech $\xFF\x01\x09\0"
24710 /* 13612 */ "uqdech $\xFF\x01\x09, $\xFF\x03\x0E\0"
24711 /* 13630 */ "uqdecw $\x01\0"
24712 /* 13640 */ "uqdecw $\x01, $\xFF\x03\x0E\0"
24713 /* 13656 */ "uqdecw $\xFF\x01\x0B\0"
24714 /* 13668 */ "uqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
24715 /* 13686 */ "uqincb $\x01\0"
24716 /* 13696 */ "uqincb $\x01, $\xFF\x03\x0E\0"
24717 /* 13712 */ "uqincd $\x01\0"
24718 /* 13722 */ "uqincd $\x01, $\xFF\x03\x0E\0"
24719 /* 13738 */ "uqincd $\xFF\x01\x10\0"
24720 /* 13750 */ "uqincd $\xFF\x01\x10, $\xFF\x03\x0E\0"
24721 /* 13768 */ "uqinch $\x01\0"
24722 /* 13778 */ "uqinch $\x01, $\xFF\x03\x0E\0"
24723 /* 13794 */ "uqinch $\xFF\x01\x09\0"
24724 /* 13806 */ "uqinch $\xFF\x01\x09, $\xFF\x03\x0E\0"
24725 /* 13824 */ "uqincw $\x01\0"
24726 /* 13834 */ "uqincw $\x01, $\xFF\x03\x0E\0"
24727 /* 13850 */ "uqincw $\xFF\x01\x0B\0"
24728 /* 13862 */ "uqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0"
24729 /* 13880 */ "xpaclri\0"
24730 ;
24731
24732#ifndef NDEBUG
24733 static struct SortCheck {
24734 SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
24735 assert(std::is_sorted(
24736 OpToPatterns.begin(), OpToPatterns.end(),
24737 [](const PatternsForOpcode &L, const PatternsForOpcode &R) {
24738 return L.Opcode < R.Opcode;
24739 }) &&
24740 "tablegen failed to sort opcode patterns");
24741 }
24742 } sortCheckVar(OpToPatterns);
24743#endif
24744
24745 AliasMatchingData M {
24746 makeArrayRef(OpToPatterns),
24747 makeArrayRef(Patterns),
24748 makeArrayRef(Conds),
24749 StringRef(AsmStrings, array_lengthof(AsmStrings)),
24750 &AArch64AppleInstPrinterValidateMCOperand,
24751 };
24752 const char *AsmString = matchAliasPatterns(MI, &STI, M);
24753 if (!AsmString) return false;
24754
24755 unsigned I = 0;
24756 while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
24757 AsmString[I] != '$' && AsmString[I] != '\0')
24758 ++I;
24759 OS << '\t' << StringRef(AsmString, I);
24760 if (AsmString[I] != '\0') {
24761 if (AsmString[I] == ' ' || AsmString[I] == '\t') {
24762 OS << '\t';
24763 ++I;
24764 }
24765 do {
24766 if (AsmString[I] == '$') {
24767 ++I;
24768 if (AsmString[I] == (char)0xff) {
24769 ++I;
24770 int OpIdx = AsmString[I++] - 1;
24771 int PrintMethodIdx = AsmString[I++] - 1;
24772 printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, OS);
24773 } else
24774 printOperand(MI, unsigned(AsmString[I++]) - 1, STI, OS);
24775 } else {
24776 OS << AsmString[I++];
24777 }
24778 } while (AsmString[I] != '\0');
24779 }
24780
24781 return true;
24782}
24783
24784void AArch64AppleInstPrinter::printCustomAliasOperand(
24785 const MCInst *MI, uint64_t Address, unsigned OpIdx,
24786 unsigned PrintMethodIdx,
24787 const MCSubtargetInfo &STI,
24788 raw_ostream &OS) {
24789 switch (PrintMethodIdx) {
24790 default:
24791 llvm_unreachable("Unknown PrintMethod kind");
24792 break;
24793 case 0:
24794 printAddSubImm(MI, OpIdx, STI, OS);
24795 break;
24796 case 1:
24797 printShifter(MI, OpIdx, STI, OS);
24798 break;
24799 case 2:
24800 printArithExtend(MI, OpIdx, STI, OS);
24801 break;
24802 case 3:
24803 printLogicalImm<int32_t>(MI, OpIdx, STI, OS);
24804 break;
24805 case 4:
24806 printLogicalImm<int64_t>(MI, OpIdx, STI, OS);
24807 break;
24808 case 5:
24809 printSVERegOp<'b'>(MI, OpIdx, STI, OS);
24810 break;
24811 case 6:
24812 printSVERegOp<>(MI, OpIdx, STI, OS);
24813 break;
24814 case 7:
24815 printLogicalImm<int8_t>(MI, OpIdx, STI, OS);
24816 break;
24817 case 8:
24818 printSVERegOp<'h'>(MI, OpIdx, STI, OS);
24819 break;
24820 case 9:
24821 printLogicalImm<int16_t>(MI, OpIdx, STI, OS);
24822 break;
24823 case 10:
24824 printSVERegOp<'s'>(MI, OpIdx, STI, OS);
24825 break;
24826 case 11:
24827 printVRegOperand(MI, OpIdx, STI, OS);
24828 break;
24829 case 12:
24830 printImm(MI, OpIdx, STI, OS);
24831 break;
24832 case 13:
24833 printSVEPattern(MI, OpIdx, STI, OS);
24834 break;
24835 case 14:
24836 printImm8OptLsl<int8_t>(MI, OpIdx, STI, OS);
24837 break;
24838 case 15:
24839 printSVERegOp<'d'>(MI, OpIdx, STI, OS);
24840 break;
24841 case 16:
24842 printImm8OptLsl<int64_t>(MI, OpIdx, STI, OS);
24843 break;
24844 case 17:
24845 printImm8OptLsl<int16_t>(MI, OpIdx, STI, OS);
24846 break;
24847 case 18:
24848 printImm8OptLsl<int32_t>(MI, OpIdx, STI, OS);
24849 break;
24850 case 19:
24851 printInverseCondCode(MI, OpIdx, STI, OS);
24852 break;
24853 case 20:
24854 printSVELogicalImm<int16_t>(MI, OpIdx, STI, OS);
24855 break;
24856 case 21:
24857 printSVELogicalImm<int32_t>(MI, OpIdx, STI, OS);
24858 break;
24859 case 22:
24860 printSVELogicalImm<int64_t>(MI, OpIdx, STI, OS);
24861 break;
24862 case 23:
24863 printZPRasFPR<8>(MI, OpIdx, STI, OS);
24864 break;
24865 case 24:
24866 printVectorIndex(MI, OpIdx, STI, OS);
24867 break;
24868 case 25:
24869 printZPRasFPR<64>(MI, OpIdx, STI, OS);
24870 break;
24871 case 26:
24872 printZPRasFPR<16>(MI, OpIdx, STI, OS);
24873 break;
24874 case 27:
24875 printSVERegOp<'q'>(MI, OpIdx, STI, OS);
24876 break;
24877 case 28:
24878 printZPRasFPR<128>(MI, OpIdx, STI, OS);
24879 break;
24880 case 29:
24881 printZPRasFPR<32>(MI, OpIdx, STI, OS);
24882 break;
24883 case 30:
24884 printFPImmOperand(MI, OpIdx, STI, OS);
24885 break;
24886 case 31:
24887 printTypedVectorList<0,'d'>(MI, OpIdx, STI, OS);
24888 break;
24889 case 32:
24890 printTypedVectorList<0,'s'>(MI, OpIdx, STI, OS);
24891 break;
24892 case 33:
24893 printBTIHintOp(MI, OpIdx, STI, OS);
24894 break;
24895 case 34:
24896 printPSBHintOp(MI, OpIdx, STI, OS);
24897 break;
24898 case 35:
24899 printTypedVectorList<0,'h'>(MI, OpIdx, STI, OS);
24900 break;
24901 case 36:
24902 printTypedVectorList<0,'b'>(MI, OpIdx, STI, OS);
24903 break;
24904 case 37:
24905 printTypedVectorList<16, 'b'>(MI, OpIdx, STI, OS);
24906 break;
24907 case 38:
24908 printTypedVectorList<1, 'd'>(MI, OpIdx, STI, OS);
24909 break;
24910 case 39:
24911 printTypedVectorList<2, 'd'>(MI, OpIdx, STI, OS);
24912 break;
24913 case 40:
24914 printTypedVectorList<2, 's'>(MI, OpIdx, STI, OS);
24915 break;
24916 case 41:
24917 printTypedVectorList<4, 'h'>(MI, OpIdx, STI, OS);
24918 break;
24919 case 42:
24920 printTypedVectorList<4, 's'>(MI, OpIdx, STI, OS);
24921 break;
24922 case 43:
24923 printTypedVectorList<8, 'b'>(MI, OpIdx, STI, OS);
24924 break;
24925 case 44:
24926 printTypedVectorList<8, 'h'>(MI, OpIdx, STI, OS);
24927 break;
24928 case 45:
24929 printTypedVectorList<0, 'h'>(MI, OpIdx, STI, OS);
24930 break;
24931 case 46:
24932 printTypedVectorList<0, 's'>(MI, OpIdx, STI, OS);
24933 break;
24934 case 47:
24935 printTypedVectorList<0, 'd'>(MI, OpIdx, STI, OS);
24936 break;
24937 case 48:
24938 printTypedVectorList<0, 'b'>(MI, OpIdx, STI, OS);
24939 break;
24940 case 49:
24941 printImmHex(MI, OpIdx, STI, OS);
24942 break;
24943 case 50:
24944 printPrefetchOp<true>(MI, OpIdx, STI, OS);
24945 break;
24946 case 51:
24947 printPrefetchOp(MI, OpIdx, STI, OS);
24948 break;
24949 case 52:
24950 printGPR64as32(MI, OpIdx, STI, OS);
24951 break;
24952 case 53:
24953 printSysCROperand(MI, OpIdx, STI, OS);
24954 break;
24955 }
24956}
24957
24958static bool AArch64AppleInstPrinterValidateMCOperand(const MCOperand &MCOp,
24959 const MCSubtargetInfo &STI,
24960 unsigned PredicateIndex) {
24961 switch (PredicateIndex) {
24962 default:
24963 llvm_unreachable("Unknown MCOperandPredicate kind");
24964 break;
24965 case 1: {
24966
24967 if (!MCOp.isImm())
24968 return false;
24969 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
24970 return AArch64_AM::isSVEMaskOfIdenticalElements<int8_t>(Val);
24971
24972 }
24973 case 2: {
24974
24975 if (!MCOp.isImm())
24976 return false;
24977 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
24978 return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val);
24979
24980 }
24981 case 3: {
24982
24983 if (!MCOp.isImm())
24984 return false;
24985 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
24986 return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val);
24987
24988 }
24989 case 4: {
24990
24991 return MCOp.isImm() &&
24992 MCOp.getImm() != AArch64CC::AL &&
24993 MCOp.getImm() != AArch64CC::NV;
24994
24995 }
24996 case 5: {
24997
24998 if (!MCOp.isImm())
24999 return false;
25000 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
25001 return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val) &&
25002 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val);
25003
25004 }
25005 case 6: {
25006
25007 if (!MCOp.isImm())
25008 return false;
25009 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
25010 return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val) &&
25011 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val);
25012
25013 }
25014 case 7: {
25015
25016 if (!MCOp.isImm())
25017 return false;
25018 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
25019 return AArch64_AM::isSVEMaskOfIdenticalElements<int64_t>(Val) &&
25020 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val);
25021
25022 }
25023 case 8: {
25024
25025 // "bti" is an alias to "hint" only for certain values of CRm:Op2 fields.
25026 if (!MCOp.isImm())
25027 return false;
25028 return AArch64BTIHint::lookupBTIByEncoding((MCOp.getImm() ^ 32) >> 1) != nullptr;
25029
25030 }
25031 case 9: {
25032
25033 // Check, if operand is valid, to fix exhaustive aliasing in disassembly.
25034 // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields.
25035 if (!MCOp.isImm())
25036 return false;
25037 return AArch64PSBHint::lookupPSBByEncoding(MCOp.getImm()) != nullptr;
25038
25039 }
25040 }
25041}
25042
25043#endif // PRINT_ALIAS_INSTR
25044